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DS90UB924-Q1
SNLS512 – APRIL 2016
DS90UB924-Q1 5-MHz to 96-MHz 24-bit Color FPD-Link III to OpenLDI Deserializer With
Bidirectional Control Channel
1 Features
3 Description
•
The DS90UB924-Q1 deserializer, in conjunction with
a DS90UB921-Q1, DS90UB925Q-Q1, DS90UB927QQ1,
DS90UB929-Q1,
DS90UB949-Q1,
or
DS90UB947-Q1 serializer, provides a solution for
distribution of digital video and audio within
automotive infotainment systems. The device
converts a high-speed serialized interface with an
embedded clock, delivered over a single signal pair
(FPD-Link III), to four LVDS data/control streams, one
LVDS clock pair (OpenLDI), and I2S audio data. The
serial bus scheme, FPD-Link III, supports high-speed
forward channel data transmission and low-speed full
duplex back channel communication over a single
differential link. Consolidation of audio, video data
and control over a single differential pair reduces the
interconnect size and weight, while also eliminating
skew issues and simplifying system design.
1
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications AEC-Q100
– Device Temperature Grade 2: –40°C to
+105°C Ambient Operating Temperature
Range
– Device HBM ESD Classification Level ±8 kV
– Device CDM ESD Classification Level C6
5-MHz to 96-MHz Pixel Clock Support
Bidirectional Control Channel Interface with I2CCompatible Serial Control Bus
Low EMI OpenLDI Video Output
Supports High Definition (720p) Digital Video
RGB888 + VS, HS, DE and I2S Audio Supported
Up to 4 I2S Digital Audio Outputs for Surround
Sound Applications
4 Bidirectional GPIO Channels With 2 Dedicated
Pins
Single 3.3-V Supply With 1.8-V or 3.3-V
Compatible LVCMOS I/O Interface
DC-Balanced and Scrambled Data with
Embedded Clock
Adaptive Cable Equalization
Internal Pattern Generation
Backward Compatible Modes
Adaptive input equalization of the serial input stream
provides compensation for transmission medium
losses and deterministic jitter. EMI is minimized by
the use of low voltage differential signaling.
Device Information
PART NUMBER
DS90UB924-Q1
PACKAGE
WQFN (48)
(1)
BODY SIZE (NOM)
7.00 mm x 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
Automotive Touch Screen Display
Automotive Display for Navigation
Automotive Instrument Cluster
FPD-Link
(Open LDI)
VDD33
VDDIO
(3.3V) (1.8V or 3.3V)
HOST
Graphics
Processor
RGB Digital Display Interface
VDDIO
VDD33
(1.8V or 3.3V) (3.3V)
R[7:0]
G[7:0]
B[7:0]
HS
VS
DE
PCLK
TxOUT3+/-
FPD-Link III
1 Pair/AC Coupled
DOUT+
TxOUT2+/-
RIN+
RIN-
DOUT100Q STP Cable
PDB
I2S AUDIO
(STEREO)
SCL
SDA
IDx
3
DS90UB921-Q1
Serializer
DAP
OEN
OSS_SEL
MODE_SEL
PDB
INTB
MAPSEL
LFMODE
BISTEN
MODE_SEL
DS90UB924-Q1
Deserializer
TxOUT1+/TxOUT0+/-
LVDS Display
720p or
Graphic
Proccesor
TxCLKOUT+/INTB_IN
LOCK
PASS
6
I2S
MCLK
SCL
SDA
IDx
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DS90UB924-Q1
SNLS512 – APRIL 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
7
7.4 Device Functional Modes........................................ 27
7.5 Programming........................................................... 33
7.6 Register Maps ......................................................... 35
1
1
1
2
3
6
8
Application and Implementation ........................ 50
8.1 Application Information............................................ 50
8.2 Typical Application .................................................. 50
9
Absolute Maximum Ratings ..................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
DC Electrical Characteristics .................................... 7
AC Electrical Characteristics..................................... 9
DC and AC Serial Control Bus Characteristics....... 10
Timing Requirements for the Serial Control Bus .... 10
Timing Requirements .............................................. 11
Typical Characteristics .......................................... 15
Power Supply Recommendations...................... 53
9.1 Power Up Requirements and PDB Pin ................... 53
9.2 Analog Power Signal Routing ................................. 55
10 Layout................................................................... 55
10.1 Layout Guidelines ................................................. 55
10.2 Layout Example .................................................... 57
11 Device and Documentation Support ................. 58
11.1
11.2
11.3
11.4
11.5
Detailed Description ............................................ 16
7.1 Overview ................................................................. 16
7.2 Functional Block Diagram ....................................... 16
7.3 Feature Description................................................. 17
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
58
58
58
58
58
12 Mechanical, Packaging, and Orderable
Information ........................................................... 58
4 Revision History
2
DATE
REVISION
NOTES
April 2016
*
Initial release.
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SNLS512 – APRIL 2016
5 Pin Configuration and Functions
I2S_DD/GPIO3
OSS_SEL
RES0
CAPL12
LFMODE
VDD33_B
OEN
CAPLV12
PASS
LOCK
MAPSEL
CAPLV25
36
35
34
33
32
31
30
29
28
27
26
25
RHS Package
48-Pin WQFN
Top View
I2S_DC/GPIO2
37
24
TxOUT0-
VDD33_A
38
23
TxOUT0+
RES1
39
22
TxOUT1-
RIN+
40
21
TxOUT1+
RIN-
41
20
TxOUT2-
CMF
42
19
TxOUT2+
BISTC/INTB_IN
43
18
TxCLKOUT-
CMLOUTP
44
DS90UB924-Q1
TOP VIEW
DAP = GND
17
TxCLKOUT+
10
11
12
I2S_WC/GPIO_REG7
MCLK
IDx
9
8
I2S_CLK/GPIO_REG8
BISTEN
7
GPIO1/SDOUT
I2S_DA/GPIO_REG6
13
6
48
VDDIO
MODE_SEL
5
GPIO0/SWC
SCL
14
4
47
SDA
CAPP12
3
TxOUT3+
I2S_DB/GPIO_REG5
15
2
46
CAPI2S
16
1
45
CAPR12
PDB
CMLOUTN
TxOUT3-
Pin Functions
PIN
NAME
NO.
I/O, TYPE
DESCRIPTION
FPD-LINK (OpenLDI) OUTPUT INTERFACE
TxCLKOUT-
18
O, LVDS
Inverting LVDS Clock Output
The pair requires external 100-Ω differential termination for standard LVDS levels
TxCLKOUT+
17
O, LVDS
True LVDS Clock Output
The pair requires external 100-Ω differential termination for standard LVDS levels
TxOUT[3:0]-
16, 20, 22,
24
O, LVDS
Inverting LVDS Data Outputs
Each pair requires external 100-Ω differential termination for standard LVDS levels
TxOUT[3:0]+
15, 19, 21,
23
O, LVDS
True LVDS Data Outputs
Each pair requires external 100-Ω differential termination for standard LVDS levels
LVCMOS INTERFACE
GPIO[1:0]
13, 14
I/O, LVCMOS General Purpose IO
with pulldown Shared with SDOUT, SWC
GPIO[3:2]
36, 37
I/O, LVCMOS General Purpose I/O
with pulldown Shared with I2S_DD, I2S_DC
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SNLS512 – APRIL 2016
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Pin Functions (continued)
PIN
NAME
NO.
GPIO_REG[8
:5]
8, 10, 7, 3
I/O, TYPE
DESCRIPTION
I/O, LVCMOS General Purpose I/O, register access only
with pulldown Shared with I2S_CLK, I2S_WC, I2S_DA, I2S_DB
I2S_DA
I2S_DB
I2S_DC
I2S_DD
7
3
37
36
O, LVCMOS
Digital Audio Interface I2S Data Outputs
Shared with GPIO_REG6, GPIO_REG5, GPIO2, GPIO3
INTB_IN
43
I, LVCMOS Interrupt Input
with pulldown Shared with BISTC
MCLK
I2S_WC
I2S_CLK
11
10
8
O, LVCMOS
SDOUT
SWC
13
14
O, LVCMOS Auxiliary Digital Audio Interface I2S Data Output and Word Clock
with pulldown Shared with GPIO1 and GPIO0
Digital Audio Interface I2S Master Clock, Word Clock and I2S Bit Clock Outputs
I2S_WC and I2S_CLK are shared with GPIO_REG7 and GPIO_REG8
CONTROL AND CONFIGURATION
BISTC
43
I, LVCMOS BIST Clock Select
with pulldown Shared with INTB_IN
Requires a 10-KΩ pullup if set HIGH
BISTEN
9
I, LVCMOS BIST Enable
with pulldown Requires a 10-KΩ pullup if set HIGH
IDx
12
LFMODE
32
I, LVCMOS Low Frequency Mode Select
with pulldown LFMODE = 0, 15-MHz ≤ TxCLKOUT ≤ 96-MHz (Default)
LFMODE = 1, 5-MHz ≤ TxCLKOUT < 15-MHz
Requires a 10-KΩ pullup if set HIGH
MAPSEL
26
I, LVCMOS FPD-Link (OpenLDI) Output Map Select
with pulldown MAPSEL = 0, LSBs on TxOUT3± (Default)
MAPSEL = 1, MSBs on TxOUT3±
Requires a 10-KΩ pullup if set HIGH
MODE_SEL
48
OEN
30
I, LVCMOS Output Enable
with pulldown Requires a 10-KΩ pullup if set HIGH
See Table 5
OSS_SEL
35
I, LVCMOS Output Sleep State Select
with pulldown Requires a 10 KΩ pullup if set HIGH
See Table 5
PDB
1
I, LVCMOS
SCL
5
I/O, Open
Drain
I2C Clock Input/Output Interface
Must have an external pullup to VDD33. DO NOT FLOAT
Recommended pullup: 4.7 KΩ
SDA
4
I/O, Open
Drain
I2C Data Input/Output Interface
Must have an external pullup to VDD33. DO NOT FLOAT
Recommended pullup: 4.7 kΩ
4
I, Analog
I, Analog
I2C Address Select
External pullup to VDD33 is required under all conditions. DO NOT FLOAT.
Connect to external pullup to VDD33 and pulldown to GND to create a voltage divider.
See Table 7
Device Configuration Select
Configures Backwards Compatibility (BKWD), Repeater (REPEAT), I2S 4 channel (I2S_B),
and Long Cable (LCBL) modes
Connect to external pullup to VDD33 and pulldown to GND resistors to create a voltage
divider. DO NOT FLOAT
See Table 6
Power-down Mode Input Pin
Must be driven or pulled up to VDD33. Refer to Power Up Requirements and PDB PinPower
Up Requirements and PDB Pin in Application and Implementation.
PDB = H, device is enabled (normal operation)
PDB = L, device is powered down
When the device is in the powered down state, the LVDS and LVCMOS outputs are tri-state,
the PLL is shutdown, and IDD is minimized. Control Registers are RESET.
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SNLS512 – APRIL 2016
Pin Functions (continued)
PIN
NAME
I/O, TYPE
NO.
DESCRIPTION
STATUS
LOCK
27
O, LVCMOS
LOCK Status Output
0: PLL is unlocked, I2S, GPIO, TxOUT[3:0]±, and TxCLKOUT± are idle with output states
controlled by OEN and OSS_SEL. May be used to indicate Link Status or Display Enable.
1: PLL is locked, outputs are active with output states controlled by OEN and OSS_SEL
Route to test point or pad (recommended). Float if unused.
PASS
28
O, LVCMOS
PASS Status Output
0: One or more errors were detected in the received BIST payload (BIST Mode)
1: Error-free transmission (BIST Mode)
Route to test point or pad (Recommended). Float if unused.
FPD-LINK III SERIAL INTERFACE
CMF
42
Analog
CMLOUTN
45
O, LVDS
Inverting Loop-through Driver Output
Monitor point for equalized forward channel differential signal
CMLOUTP
44
O, LVDS
True Loop-through Driver Output
Monitor point for equalized forward channel differential signal
RIN-
41
I/O, LVDS
FPD-Link III Inverting Input
The output must be AC-coupled with a 0.1-µF capacitor
RIN+
40
I/O, LVDS
FPD-Link III True Input
The output must be AC-coupled with a 0.1-µF capacitor
POWER AND GROUND
GND
Common Mode Filter
Requires a 0.1-µF capacitor to GND
(1)
DAP
Ground
Large metal contact at the bottom center of the device package
Connect to the ground plane (GND) with at least 9 vias
VDD33_A
VDD33_B
38
31
Power
3.3-V power to on-chip regulator
Each pin requires a 4.7-µF capacitor to GND
VDDIO
6
Power
1.8-V / 3.3-V LVCMOS I/O Power
Requires a 4.7-µF capacitor to GND
REGULATOR CAPACITOR
CAPI2S
CAPLV25
CAPLV12
CAPR12
CAPP12
2
25
29
46
47
CAP
Decoupling capacitor connection for on-chip regulator
Each requires a 4.7-µF decoupling capacitor to GND
CAPL12
33
CAP
Decoupling capacitor connection for on-chip regulator
Requires two 4.7-µF decoupling capacitors to GND
39, 34
GND
Reserved
Connect to GND
OTHER
RES[1:0]
(1)
The VDD (VDD33 and VDDIO) supply ramp must be faster than 1.5 ms with a monotonic rise.
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless othewise noted) (1)
(2)
MIN
MAX
UNIT
Supply voltage – VDD33
(3)
−0.3
4
V
Supply voltage – VDDIO
(3)
−0.3
4
V
−0.3
(VDDIO +
0.3)
V
−0.3
2.75
V
150
°C
150
°C
LVCMOS I/O voltage
Deserializer input voltage
Junction temperature
−65
Storage temperature, Tstg
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
For soldering specifications, see product folder at www.ti.com and Absolute Maximum Ratings for Soldering SNOA549.
The DS90UB924-Q1 VDD33 and VDDIO voltages require a specific ramp rate during power up. The power supply ramp time must be less
than 1.5 ms with a monotonic rise.
6.2 ESD Ratings
VALUE
UNIT
(1)
±8000
V
Charged device model (CDM), per AEC Q100-011, all pins
±1250
V
Human body model (HBM), per AEC Q100-002, all pins
Machine model (MM)
V(ESD)
(1)
Electrostatic
discharge
±250
V
(IEC, powered-up only)
RD = 330 Ω, CS = 150 pF
Air Discharge (Pins 40, 41, 44, and 45)
±15000
V
Contact Discharge (Pins 40, 41, 44, and 45)
±8000
V
(ISO10605)
RD = 330 Ω, CS = 150 pF
Air Discharge (Pins 40, 41, 44, and 45)
±15000
V
Contact Discharge (Pins 40, 41, 44, and 45)
±8000
V
(ISO10605)
RD = 2 kΩ, CS = 150 pF or
330 pF
Air Discharge (Pins 40, 41, 44, and 45)
±15000
V
Contact Discharge (Pins 40, 41, 44, and 45)
±8000
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
Supply Voltage (VDD33)
MIN
NOM
MAX
3
3.3
3.6
V
Connect VDDIO to 3.3 V and use 3.3-V IOs
3
3.3
3.6
V
Connect VDDIO to 1.8 V and use 1.8-V IOs
1.71
1.8
1.89
V
−40
25
105
°C
96
MHz
(1)
LVCMOS Supply Voltage (VDDIO)
(1) (2)
Operating Free Air
Temperature (TA)
PCLK Frequency (out of TxCLKOUT±)
Supply Noise
(1)
(2)
(3)
6
5
(3)
UNIT
100 mVP-P
The DS90UB924-Q1 VDD33 and VDDIO voltages require a specific ramp rate during power up. The power supply ramp time must be less
than 1.5 ms with a monotonic rise.
VDDIO must not exceed VDD33 by more than 300 mV (VDDIO < VDD33 + 0.3 V).
Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC-coupled to the VDD33 and VDDIO supplies
with amplitude >100 mVp-p measured at the device VDD33 and VDDIO pins. Bit error rate testing of input to the Ser and output of the
Des shows no error when the noise frequency on the Ser is less than 50 MHz. The Des on the other hand shows no error when the
noise frequency is less than 50 MHz.
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6.4 Thermal Information
DS90UB924-Q1
THERMAL METRIC
(1)
RHS (WQFN)
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
26.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
4.4
°C/W
RθJB
Junction-to-board thermal resistance
4.3
°C/W
ψJT
Junction-to-top characterization parameter
0.1
°C/W
ψJB
Junction-to-board characterization parameter
4.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
0.8
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
PIN/FREQ.
(1) (2) (3)
MIN
TYP
MAX
UNIT
2
VDDIO
V
GND
0.8
V
10
μA
3.3 V LVCMOS I/O
VIH
High Level Input Voltage
VIL
Low Level Input Voltage
GPIO[3:0],
REG_GPIO[8:
5], LFMODE,
MAPSEL,
BISTEN,
BISTC,
= 3.0 V to 3.6 V
INTB_IN,
OEN,
OSS_SEL
IIN
Input Current
VIH
High Level Input Voltage
2
VDDIO
V
VIL
Low Level Input Voltage
GND
0.7
V
IIN
Input Current
VIN = 0 V or VIN = 3.0 V to 3.6 V
10
μA
VOH
HIGH Level Output Voltage
IOH = -4 mA
2.4
VDDIO
V
VOL
LOW Level Output Voltage
IOL = 4 mA
0
0.4
V
VDDIO = 3.0 V to 3.6 V
VIN = 0 V or VIN
(4)
PDB
IOS
Output Short Circuit Current
VOUT = 0 V
IOZ
Tri-state Output Current
VOUT = 0 V or VDDIO, PDB = L
(1)
(2)
(3)
(4)
(5)
-10
(4)
(5)
-10
GPIO[3:0],
REG_GPIO[8:
5], MCLK,
I2S_WC,
I2S_CLK,
I2S_D[A:D],
LOCK, PASS
±1
±1
-55
-20
mA
20
μA
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at VDD33 = 3.3 V, VDDIO = 1.8 V or 3.3 V, TA = 25°C, and at the Recommended
Operating Conditions at the time of product characterization and are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD, which are differential voltages.
PDB is specified to 3.3 V LVCMOS only and must be driven or pulled up to VDD33 or to VDDIO ≥ 3 V.
IOS is not specified for an indefinite period of time. Do not hold in short circuit for more than 500 ms or part damage may result.
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DC Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
PIN/FREQ.
(1) (2) (3)
MIN
TYP
MAX
UNIT
1.8 V LVCMOS I/O
VIH
High Level Input Voltage
VDDIO = 1.71 V to 1.89 V
VIL
Low Level Input Voltage
IIN
Input Current
VIN = 0 V or VIN = 1.71 V to
1.89 V
VOH
HIGH Level Output Voltage
IOH = -4 mA
VOL
LOW Level Output Voltage
IOL = +4 mA
IOS
Output Short Circuit Current
VOUT = 0 V
IOZ
TRI-STATE® Output Current
VOUT = 0 V or VDDIO, PDB = L,
(5)
GPIO[3:0],
REG_GPIO[8:
5], LFMODE,
MAPSEL,
BISTEN,
BISTC,
INTB_IN,
OEN,
OSS_SEL
0.65 *
VDDIO
VDDIO
V
0
0.35 *
VDDIO
V
-10
10
μA
GPIO[3:0],
REG_GPIO[8:
5], MCLK,
I2S_WC,
I2S_CLK,
I2S_D[A:D],
LOCK, PASS
VDDIO 0.45
VDDIO
V
0
0.45
-35
-20
V
mA
20
μA
FPD-LINK (OpenLDI) LVDS OUTPUT
VOD
VODp-p
Output Voltage Swing (singleended)
Differential Output Voltage
Register 0x4B[1:0] = b'00
RL = 100 Ω
140
200
300
mV
Register 0x4B[1:0] = b'01
RL = 100 Ω
220
300
380
mV
Register 0x4B[1:0] = b'00
RL = 100 Ω
Register 0x4B[1:0] = b'01
RL = 100 Ω
ΔVOD
Output Voltage Unbalance
VOS
Common Mode Voltage
ΔVOS
Offset Voltage Unbalance
IOS
Output Short Circuit Current
VOUT = GND
Output TRI-STATE® Current
OEN = GND, VOUT = VDDIO or
GND, 0.8 V ≤ VIN ≤ 1.6 V
IOZ
TxCLK±,
TxOUT[3:0]±
RL = 100 Ω
1
400
mV
600
mV
1
50
1.2
1.5
V
1
50
mV
-5
-500
mV
mA
500
μA
50
mV
FPD-LINK III RECEIVER
VTH
Input Threshold High
VTL
Input Threshold Low
VID
Input Differential Threshold
VCM
Common-mode Voltage
RT
Internal Termination Resistance
(Differential)
VCM = 2.1 V (Internal VBIAS)
-50
mV
100
RIN±
2.1
mV
V
100
120
Ω
VDD33= 3.6 V
200
260
mA
VDDIO = 3.6 V
30
250
μA
VDDIO = 1.89 V
30
250
μA
80
SUPPLY CURRENT
IDD33
IDDIO
Supply Current
RL = 100 Ω,
PCLK = 96 MHz
IDDZ
IDDIOZ
8
Supply Current — Power Down
PDB = 0 V, All other LVCMOS
inputs = 0 V
VDD33 = 3.6 V
3
8
mA
VDDIO = 3.6 V
100
500
μA
VDDIO = 1.89 V
50
250
μA
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6.6 AC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
PARAMETER
TEST CONDITIONS
(1) (2) (3)
PIN/FREQ.
MIN
TYP
MAX
UNIT
GPIO[3:0],
PCLK =
5MHz to
96MHz
2/PCLK
s
20
µs
2
ms
GPIO
tGPIO,FC
GPIO Pulse Width, Forward
Channel
See
(4)
tGPIO,BC
GPIO Pulse Width, Back Channel
See
(4)
GPIO[3:0]
PDB Reset Low Pulse
See
(4)
PDB
RESET
tLRST
LOOP-THROUGH MONITOR OUTPUT
EW
Differential Output Eye Opening
Width (4)
EH
Differential Output Eye Height
RL = 100 Ω, Jitter freq > f/40
CMLOUTP,
CMLOUTN
0.4
UI
300
mV
FPD-LINK (OpenLDI) LVDS OUTPUT
RL = 100 Ω
TxCLK±,
TxOUT[3:0]±
Cycle-to-Cycle Output Jitter
5 MHz ≤ PCLK ≤ 96 MHz
TxCLK±
tTTPn
Transmitter Pulse Position
5 MHz ≤ PCLK ≤ 96 MHz
n=[6:0] for bits [6:0]
See Figure 13
TxOUT[3:0]±
ΔtTTP
Offset Transmitter Pulse Position
(bit 6 - bit 0)
PCLK = 96 MHz
tDD
Delay Latency
tTPDD
Power Down Delay Active to OFF
tTXZR
Enable Delay OFF to Active
tTLHT
Low -to-High Transition Time
tTHLT
High-to-Low Transition Time
tDCCJ
0.25
0.5
ns
0.25
0.5
ns
40
65
ps
0.5 + n
UI
0.1
UI
147*T
T
900
µs
6
ns
FPD-LINK III INPUT
tDDLT
Lock Time
(4)
5 MHz ≤ PCLK ≤ 96 MHz
RIN±, LOCK
6
40
ms
CL = 8 pF
LOCK, PASS
3
7
ns
2
5
ns
LVCMOS OUTPUTS
tCLH
Low-to-High Transition Time
tCHL
High-to-Low Transition Time
BIST MODE
tPASS
BIST PASS Valid Time
PASS
800
ns
2
ns
I2S TRANSMITTER
tJ
Clock Output Jitter
TI2S
I2S Clock Period
Figure 10, (4) (5)
THC_I2S
I2S Clock High Time Figure 10,
TLC_I2S
I2S Clock Low Time Figure 10,
tSR_I2S
I2S Set-up Time Figure 10,
tHR_I2S
I2S Hold Time Figure 10
(1)
(2)
(3)
(4)
(5)
MCLK
PCLK=5 MHz to 96 MHz
(5)
(5)
I2S_CLK,
PCLK =
5MHz to
96MHz
4/PCLK
or
1/12.288
MHz
ns
I2S_CLK
0.35
TI2S
I2S_CLK
0.35
TI2S
I2S_WC
I2S_D[A:D]
0.2
TI2S
I2S_WC
I2S_D[A:D]
0.2
TI2S
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at VDD33 = 3.3 V, VDDIO = 1.8 V or 3.3 V, TA = 25°C, and at the Recommended
Operating Conditions at the time of product characterization and are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD, which are differential voltages.
Specification is ensured by design and is not tested in production.
I2S specifications for tLC and tHC pulses must each be greater than 2 PCLK period to ensure sampling and supersedes the 0.35*TI2S_CLK
requirement. tLC and tHC must be longer than the greater of either 0.35*TI2S_CLK or 2*PCLK.
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6.7 DC and AC Serial Control Bus Characteristics
Over 3.3-V supply and temperature ranges unless otherwise specified.
PARAMETER
(1) (2) (3)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VIH
Input High Level
SDA and SCL
0.7*
VDDIO
VDD33
V
VIL
Input Low Level Voltage
SDA and SCL
GND
0.3*
VDD33
V
VHY
Input Hysteresis
50
VOL
SDA or SCL, IOL = 1.25 mA
Iin
SDA or SCL, VIN = VDDIO or GND
tSP
Input Filter
Cin
Input Capacitance
(1)
(2)
(3)
mV
0
0.36
V
-10
10
µA
SDA or SCL
50
ns
5
pF
The Electrical Characteristics tables list specifications under the listed Recommended Operating Conditions except as otherwise
modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not
ensured.
Typical values represent most likely parametric norms at VDD33 = 3.3 V, VDDIO = 1.8 V or 3.3 V, TA = 25°C, and at the Recommended
Operating Conditions at the time of product characterization and are not ensured.
Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground
except VOD and ΔVOD, which are differential voltages.
6.8 Timing Requirements for the Serial Control Bus
Over 3.3-V supply and temperature ranges unless otherwise specified.
(1) (2)
MIN
fSCL
Standard Mode
SCL Clock Frequency
tLOW
SCL Low Period
tHIGH
SCL High Period
tHD;STA
tSU:STA
tHD;DAT
Fast Mode
Hold time for a start or a repeated start condition
Set Up time for a start or a repeated start condition
Data Hold Time
(3)
(3)
tSU;STO
Set Up Time for STOP Condition
tBUF
Bus Free Time
Between STOP and START
(1)
(2)
(3)
10
SCL & SDA Rise Time,
SCL & SDA Fall Time,
(3)
(3)
(3)
(3)
UNIT
100
kHz
0
400
kHz
4.7
µs
Fast Mode
1.3
µs
Standard Mode
4.0
µs
Fast Mode
0.6
µs
Standard Mode
4.0
µs
Fast Mode
0.6
µs
Standard Mode
4.7
µs
Fast Mode
0.6
Fast Mode
Data Set Up Time
tf
(3)
TYP
Standard Mode
Standard Mode
tSU;DAT
tr
(3)
MAX
0
µs
0
3.45
µs
0
0.9
µs
Standard Mode
250
ns
Fast Mode
100
ns
Standard Mode
4
µs
Fast Mode
0.6
µs
Standard Mode
4.7
µs
Fast Mode
1.3
Standard Mode
µs
1000
ns
Fast Mode
300
ns
Standard Mode
300
ns
Fast mode
300
ns
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at VDD33 = 3.3 V, VDDIO = 1.8 V or 3.3 V, TA = +25°C, and at the Recommended
Operating Conditions at the time of product characterization and are not ensured.
Specification is ensured by design and is not tested in production.
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6.9 Timing Requirements
MIN
tR
SDA RiseTime – READ
tF
SDA Fall Time – READ
tSU;DAT
Set Up Time – READ
tHD;DAT
Hold Up Time – READ
NOM
MAX
UNIT
430
ns
20
ns
Figure 9
560
ns
Figure 9
615
ns
SDA, RPU = 10 kΩ, Cb ≤ 400 pF, Figure 9
+VOD
TxCLKOUT
-VOD
+VOD
TxOUT3
-VOD
+VOD
TxOUT2
-VOD
+VOD
TxOUT1
-VOD
+VOD
TxOUT0
-VOD
Cycle N+1
Cycle N
Figure 1. Checkerboard Data Pattern
EW
VOD (+)
RIN
(Diff.)
EH
0V
EH
VOD (-)
tBIT (1 UI)
Figure 2. CML Output Driver
VDDIO
80%
20%
GND
tCLH
tCHL
Figure 3. LVCMOS Transition Times
START
STOP
BIT SYMBOL N+3 BIT
§
START
STOP
BIT SYMBOL N+2 BIT
§
§
§
START
STOP
BIT SYMBOL N+1 BIT
§
START
STOP
BIT SYMBOL N BIT
§
RIN
§
§
DCA, DCB
tDD
TxCLKOUT
TxOUT[3:0]
SYMBOL N-3
SYMBOL N-2
SYMBOL N-1
SYMBOL N
Figure 4. Latency Delay
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PDB
VILmax
RIN
X
tTPDD
LOCK
Z
PASS
Z
TxCLKOUT
Z
TxOUT[3:0]
Z
Figure 5. FPD-Link (OpenLDI) and LVCMOS Power Down Delay
PDB
LOCK
tTXZR
OEN
VIHmin
Z
TxCLKOUT
Z
TxOUT[3:0]
Figure 6. FPD-Link (OpenLDI) Outputs Enable Delay
PDB
VIH(min)
RIN±
tDDLT
LOCK
VOH(min)
TRI-STATE
Figure 7. CML PLL Lock Time
RIN+
VTL
VCM
VTH
RIN-
GND
Figure 8. FPD-Link III Receiver DC VTH/VTL Definition
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VDDIO
I2S_CLK,
MCLK
1/2 VDDIO
GND
GPIO,
I2S_WC,
I2S_D[D:A]
VDDIO
VOHmin
VOLmax
GND
tROH
tROS
Figure 9. Output Data Valid (Setup and Hold) Times
tI2S
tLC_I2S
tHC_I2S
VIH
I2S_CLK
VIL
tSR_I2S
tHR_I2S
VIH
I2S_WC
I2S_D[A,B,C,D]
VIL
Figure 10. Output State (Setup and Hold) Times
+VOD
80%
TxOUT[3:0]
TxCLKOUT
(Differential)
0V
20%
-VOD
tLHT
tHLT
TxOUT[3:0]+
TxCLKOUT+
TxOUT[3:0]TxCLKOUT-
Single-Ended
Figure 11. Input Transition Times
VOD-
VOD+
VOS
(TxOUT[3:0]+) (TxOUT[3:0]-) or
(TxCLKOUT+) (TxCLKOUT-)
VOD+
VODp-p
0V
VOD-
Differential
GND
Figure 12. FPD-Link (OpenLDI) Single-Ended and Differential Waveforms
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T
TxCLKOUT±
bit 1
TxOUT[3:0]±
bit 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
tTTP1
0.5UI
tTTP2
1.5UI
tTTP3
2.5UI
3.5UI
2¨tTTP
tTTP4
tTTP5
4.5UI
tTTP6
5.5UI
tTTP7
6.5UI
Figure 13. FPD-Link (OpenLDI) Transmitter Pulse Positions
Ideal Data
Bit End
Sampling
Window
Ideal Data Bit
Beginning
RxIN_TOL
Left
VTH
0V
VTL
RxIN_TOL
Right
Ideal Center Position (tBIT/2)
tBIT (1 UI)
tIJIT
= RxIN_TOL (Left + Right)
- tIJIT
Sampling Window = 1 UI
Figure 14. Receiver Input Jitter Tolerance
BISTEN
1/2 VDDIO
tPASS
PASS
(w/errors)
1/2 VDDIO
Prior BIST Result
Current BIST Test - Toggle on Error
Result Held
Figure 15. BIST PASS Waveform
SDA
tf
tHD;STA
tLOW
tr
tr
tBUF
tf
SCL
tSU;STA
tHD;STA
tHIGH
tHD;DAT
START
tSU;STO
tSU;DAT
STOP
REPEATED
START
START
Figure 16. Serial Control Bus Timing Diagram
14
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921 LVCMOS Clock
(1 V/DIV)
924 OLDI Clock
(500 mV/DIV)
CML Serializer Data Throughput
(80 mV/DIV)
6.10 Typical Characteristics
Time (4 ns/DIV)
Time (1.0 ns/DIV)
Figure 17. Serializer Output Stream with 96 MHz Input Clock
Figure 18. 96 MHz Clock at Serializer and Deserializer
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7 Detailed Description
7.1 Overview
The DS90UB924-Q1 receives a 35-bit symbol over a single serial FPD-Link III pair operating at up to 3.36 Gbps
line rate and converts this stream into an FPD-Link (OpenLDI) Interface (4 LVDS data channels + 1 LVDS
Clock). The FPD-Link III serial stream contains an embedded clock, video control signals, and the DC-balanced
video data and audio data which enhance signal quality to support AC coupling.
The DS90UB924-Q1 deserializer attains lock to a data stream without the use of a separate reference clock
source, which greatly simplifies system complexity and overall cost. The deserializer also synchronizes to the
serializer regardless of the data pattern, delivering true automatic plug and lock performance. It can lock to the
incoming serial stream without the need of special training patterns or sync characters. The deserializer recovers
the clock and data by extracting the embedded clock information, validating then deserializing the incoming data
stream.
The DS90UB924-Q1 deserializer incorporates an I2C-compatible interface. The I2C-compatible interface allows
programming of serializer or deserializer devices from a local host controller. In addition, the
serializer/deserializer devices incorporate a bidirectional control channel (BCC) that allows communication
between serializer/deserializer as well as remote I2C slave devices.
The bidirectional control channel (BCC) is implemented via embedded signaling in the high-speed forward
channel (serializer to deserializer) combined with lower speed signaling in the reverse channel (deserializer to
serializer). Through this interface, the BCC provides a mechanism to bridge I2C transactions across the serial link
from one I2C bus to another. The implementation allows for arbitration with other I2C compatible masters at either
side of the serial link.
The DS90UB924-Q1 deserializer is intended for use with DS90UB921-Q1, DS90UB925Q-Q1, or DS90UB927QQ1 serializers, but is also backward compatible with DS90UR905Q and DS90UR907Q FPD-Link III serializers.
7.2 Functional Block Diagram
OEN
OSS_SEL
REGULATOR
Parallel to Serial
RIN-
TxOUT3±
Data Receive
RIN+
DC Balance Decoder
Serial to Parallel
CMF
TxOUT2±
TxOUT1±
TxOUT0±
TxCLKOUT±
8
BISTEN
BISTC
LFMODE
MAPSEL
PDB
SCL
SCA
IDx
MODE_SEL
Error
Detector
Timing and
Control
Clock and
Data
Recovery
I2S / GPIO
PASS
LOCK
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7.3 Feature Description
7.3.1 High-Speed Forward Channel Data Transfer
The high-speed Forward Channel is composed of a 35-bit frame containing video data, sync signals, I2C, and I2S
audio transmitted from serializer to deserializer. Figure 19 shows the serial stream PCLK cycle. This data
payload is optimized for signal transmission over an AC-coupled link. Data is randomized, DC-balanced and
scrambled.
C0
C1
Figure 19. FPD-Link III Serial Stream
The device supports pixel clock ranges of 5 MHz to 15 MHz (LFMODE=1) and 15 MHz to 96 MHz (LFMODE=0).
This corresponds to an application payload rate range of 155 Mbps to 2.976 Gbps, with an actual line rate range
of 525 Mbps to 3.36 Gbps.
7.3.2 Low-Speed Back Channel Data Transfer
The low-speed back channel of the DS90UB924-Q1 provides bidirectional communication between the display
and host processor. The back channel control data is transferred over the single serial link along with the highspeed forward data, DC balance coding, and embedded clock information. Together, the forward channel and
back channel form the bidirectional control channel (BCC). This architecture provides a backward path across
the serial link together with a high speed forward channel. The back channel contains the I2C, CRC and 4 bits of
standard GPIO information with 10 Mbps line rate.
7.3.3 Backward Compatible Mode
The DS90UB924-Q1 is also backward compatible to the DS90UR905Q and DS90UR907Q for PCLK frequencies
ranging from 15 MHz to 65 MHz. The deserializer receives 28 bits of data over a single serial FPD-Link III pair
operating at a payload rate of 120 Mbps to 1.8 Gbps, corresponding to a line rate of 140 Mbps to 2.1 Gbps. The
backward compatibility configuration can be selected through the MODE_SEL pin or programmed through the
device control registers (Table 8). The bidirectional control channel, bidirectional GPIOs, I2S, and interrupt
(INTB) are not active in this mode. However, local I2C access to the serializer is still available.
7.3.4 Input Equalization
An FPD-Link III input adaptive equalizer provides compensation for transmission medium losses and reduces
medium-induced deterministic jitter.
The adaptive equalizer may be set to a Long Cable Mode (LCBL), using the MODE_SEL pin (Table 6). This
mode is typically used with longer cables where it may be desirable to start adaptive equalization from a higher
default gain. In this mode, the device attempts to lock from a minimum floor AEQ value, defined by a value
stored in the control registers (Table 8).
7.3.5 Common Mode Filter Pin (CMF)
The deserializer provides access to the center tap of the internal CML termination. A 0.1 μF capacitor must be
connected from this pin to GND for additional common-mode filtering of the differential pair (Figure 37). This
increases noise rejection capability in high-noise environments.
7.3.6 Power Down (PDB)
The deserializer has a PDB input pin to enable or power down the device. This pin may be controlled by an
external device, or through VDDIO, where VDDIO = 3 V to 3.6 V or VDD33. To save power, disable the link when the
display is not needed (PDB = LOW). Ensure that this pin is not driven HIGH before VDD33 and VDDIO have
reached final levels. When PDB is driven low, ensure that the pin is driven to 0 V for at least 1.5 ms before
releasing or driving high (See Recommended Operating Conditions ). If the PDB is pulled up to VDDIO = 3.0 V to
3.6 V or VDD33 directly, a 10 kΩ pullup resistor and a >10 µF capacitor to ground are required (See Figure 37).
Toggling PDB low POWER DOWN the device and RESET all control registers to default. During this time, PDB
must be held low for a minimum of 2 ms (see AC Electrical Characteristics).
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Feature Description (continued)
7.3.7 Video Control Signals
The video control signal bits embedded in the high-speed FPD-Link (OpenLDI) LVDS are subject to certain
limitations relative to the video pixel clock period (PCLK). By default, the device applies a minimum pulse width
filter on these signals to help eliminate spurious transitions.
Normal Mode Control Signals (VS, HS, DE) have the following restrictions:
• Horizontal Sync (HS): The video control signal pulse width must be 3 PCLKs or longer when the Control
Signal Filter (register bit 0x03[4]) is enabled (default). Disabling the Control Signal Filter removes this
restriction (minimum is 1 PCLK). See Table 8. HS can have at most two transitions per 130 PCLKs.
• Vertical Sync (VS): The video control signal pulse is limited to 1 transition per 130 PCLKs. Thus, the minimum
pulse width is 130 PCLKs.
• Data Enable Input (DE): The video control signal pulse width must be 3 PCLKs or longer when the Control
Signal Filter (register bit 0x03[4]) is enabled (default). Disabling the Control Signal Filter removes this
restriction (minimum is 1 PCLK). See Table 8. DE can have at most two transitions per 130 PCLKs.
7.3.8 EMI Reduction Features
7.3.8.1 LVCMOS VDDIO Option
The 1.8 V/3.3 V LVCMOS inputs and outputs are powered from a separate VDDIO supply pin to offer
compatibility with external system interface signals. Note: When configuring the VDDIO power supplies, all the
single-ended control input pins (except PDB) for device need to scale together with the same operating VDDIO
levels. If VDDIO is selected to operate in the 3.0 V to 3.6 V range, VDDIO must be operated within 300 mV of VDD33
(See Recommended Operating Conditions).
7.3.9 Built In Self Test (BIST)
An optional At-speed Built-In Self Test (BIST) feature supports testing of the high-speed serial link and the lowspeed back channel without external data connections. This is useful in the prototype stage, equipment
production, in-system test, and system diagnostics.
7.3.9.1 BIST Configuration and Status
The BIST mode is enabled at the deserializer by pin (BISTEN) or BIST configuration register. The test may
select either an external PCLK or the 33 MHz internal oscillator clock (OSC) frequency. In the absence of PCLK,
the user can select the internal OSC frequency at the deserializer through the BISTC pin or BIST configuration
register.
When BIST is activated at the deserializer, a BIST enable signal is sent to the serializer through the back
channel. The serializer outputs a test pattern and drives the link at speed. The deserializer detects the test
pattern and monitors it for errors. The deserializer PASS output pin toggles to flag each frame received
containing one or more errors. The serializer also tracks errors indicated by the CRC fields in each back channel
frame.
The BIST status can be monitored real time on the deserializer PASS pin, with each detected error resulting in a
half pixel clock period toggled LOW. After BIST is deactivated, the result of the last test is held on the PASS
output until reset (new BIST test or Power Down). A high on PASS indicates NO ERRORS were detected. A Low
on PASS indicates one or more errors were detected. The duration of the test is controlled by the pulse width
applied to the deserializer BISTEN pin. LOCK status is valid throughout the entire duration of BIST.
See Figure 20 for the BIST mode flow diagram.
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Feature Description (continued)
7.3.9.1.1 Sample BIST Sequence
1. BIST Mode is enabled via the BISTEN pin of Deserializer. The desired clock source is selected through the
deserializer BISTC pin.
2. The serializer is awakened through the back channel if it is not already on. An all zeros pattern is balanced,
scrambled, randomized, and sent through the FPD-Link III interface to the deserializer. Once the serializer
and the deserializer are in BIST mode and the deserializer acquires LOCK, the PASS pin of the deserializer
goes high, and BIST starts checking the data stream. If an error in the payload (1 to 35) is detected, the
PASS pin switches low for one half of the clock period. During the BIST test, the PASS output can be
monitored and counted to determine the payload error rate.
3. To stop BIST mode, set the BISTEN pin LOW. The deserializer stops checking the data, and the final test
result is held on the PASS pin. If the test ran error free, the PASS output remains HIGH. If there one or more
errors were detected, the PASS output outputs constant LOW. The PASS output state is held until a new
BIST is run, the device is RESET, or the device is powered down. BIST duration is user-controlled and may
be of any length.
The link returns to normal operation after the deserializer BISTEN pin is low. Figure 21 shows the waveform
diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one with multiple errors. In
most cases it is difficult to generate errors due to the robustness of the link (differential data transmission, and so
forth.), thus they may be introduced by greatly extending the cable length, faulting the interconnect medium, or
reducing signal condition enhancements (Rx equalization).
Normal
Step 1: DES in BIST
BIST
Wait
Step 2: Wait, SER in BIST
BIST
start
Step 3: DES in Normal
Mode - check PASS
BIST
stop
Step 4: DES/SER in Normal
Figure 20. BIST Mode Flow Diagram
7.3.9.2 Forward Channel and Back Channel Error Checking
The deserializer, on locking to the serial stream, compares the recovered serial stream with all zeroes and
records any errors in status registers. Errors are also dynamically reported on the PASS pin of the deserializer.
Forward channel errors may also be read from register 0x25 ( Table 8).
The back-channel data is checked for CRC errors once the serializer locks onto the back-channel serial stream,
as indicated by link detect status (register bit 0x1C[0] - Table 8). CRC errors are recorded in an 8-bit register in
the deserializer. The register is cleared when the serializer enters the BIST mode. As soon as the serializer
enters BIST mode, the functional mode CRC register starts recording any back channel CRC errors. The BIST
mode CRC error register is active in BIST mode only and keeps the record of the last BIST run until cleared or
the serializer enters BIST mode again.
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Feature Description (continued)
DES Outputs
BISTEN
(DES)
TxCLKOUT
Case 1 - Pass
TxOUT[3:0]
7 bits/frame
DATA
(internal)
PASS
Prior Result
PASS
DATA
(internal)
PASS
X
X
X
FAIL
Prior Result
Normal
SSO
Case 2 - Fail
X = bit error(s)
BIST Test
BIST Duration
BIST
Result
Held
Normal
Figure 21. BIST Waveforms
7.3.10 Internal Pattern Generation
The DS90UB924-Q1 deserializer features an internal pattern generator. It allows basic testing and debugging of
an integrated panel. The test patterns are simple and repetitive and allow for a quick visual verification of panel
operation. As long as the device is not in power down mode, the test pattern is displayed even if no input is
applied. If no clock is received, the test pattern can be configured to use a programmed oscillator frequency. For
detailed information, refer to TI Application Note: (AN-2198).
7.3.10.1 Pattern Options
The DS90UB924-Q1 deserializer pattern generator is capable of generating 17 default patterns for use in basic
testing and debugging of panels. Each pattern can be inverted using register bits (see Table 8). The 17 default
patterns are listed as follows:
1. White/Black (default/inverted)
2. Black/White
3. Red/Cyan
4. Green/Magenta
5. Blue/Yellow
6. Horizontally Scaled Black to White/White to Black
7. Horizontally Scaled Black to Red/Cyan to White
8. Horizontally Scaled Black to Green/Magenta to White
9. Horizontally Scaled Black to Blue/Yellow to White
10. Vertically Scaled Black to White/White to Black
11. Vertically Scaled Black to Red/Cyan to White
12. Vertically Scaled Black to Green/Magenta to White
13. Vertically Scaled Black to Blue/Yellow to White
14. Custom Color / Inverted configured in PGRS
15. Black-White/White-Black Checkerboard (or custom checkerboard color, configured in PGCTL)
16. YCBR/RBCY VCOM pattern, orientation is configurable from PGCTL
17. Color Bars (White, Yellow, Cyan, Green, Magenta, Red, Blue, Black) – Note: not included in the autoscrolling feature
20
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Feature Description (continued)
7.3.10.2 Color Modes
By default, the Pattern Generator operates in 24-bit color mode, where all bits of the red, green, and blue outputs
are enabled. 18-bit color mode can be activated from the configuration registers (Table 8). In 18-bit mode, the 6
most significant bits (bits 7-2) of the Red, Green, and Blue outputs are enabled; the 2 least significant bits are 0.
7.3.10.3 Video Timing Modes
The Pattern Generator has two video timing modes – external and internal. In external timing mode, the Pattern
Generator detects the video frame timing present on the DE and VS inputs. If Vertical Sync signaling is not
present on VS, the Pattern Generator determines Vertical Blank by detecting when the number of inactive pixel
clocks (DE = 0) exceeds twice the detected active line length. In internal timing mode, the Pattern Generator
uses custom video timing as configured in the control registers. The internal timing generation may also be
driven by an external clock. By default, external timing mode is enabled. Internal timing or Internal timing with
External Clock are enabled by the control registers (Table 8). If internal clock generation is used, register 0x39
bit 1 must be set.
7.3.10.4 External Timing
In external timing mode, the pattern generator passes the incoming DE, HS, and VS signals unmodified to the
video control outputs after a two-pixel clock delay. It extracts the active frame dimensions from the incoming
signals in order to properly scale the brightness patterns. If the incoming video stream does not use the VS
signal, the Pattern Generator determines the Vertical Blank time by detecting a long period of pixel clocks without
DE asserted.
7.3.10.5 Pattern Inversion
The Pattern Generator also incorporates a global inversion control, located in the PGCFG register, which causes
the output pattern to be bitwise-inverted. For example, the full-screen Red pattern becomes full-screen cyan, and
the Vertically Scaled Black to Green pattern becomes Vertically Scaled White to Magenta.
7.3.10.6 Auto Scrolling
The Pattern Generator supports an Auto-Scrolling mode, in which the output pattern cycles through a list of
enabled pattern types. A sequence of up to 16 patterns may be defined in the registers. The patterns may
appear in any order in the sequence and may also appear more than once.
7.3.10.7 Additional Features
Additional pattern generator features can be accessed through the Pattern Generator Indirect Register Map. It
consists of the Pattern Generator Indirect Address (PGIA — Table 8) and the Pattern Generator Indirect Data
(PGID — Table 8).
7.3.11 Serial Link Fault Detect
The DS90UB924-Q1 can detect fault conditions in the FPD-Link III interconnect. If a fault condition occurs, the
Link Detect Status is 0 (cable is not detected) on bit 0 of address 0x1C (Table 8). The device detects any of the
following conditions:
1. Cable open
2. RIN+ to - short
3. RIN+ to GND short
4. RIN- to GND short
5. RIN+ to battery short
6. RIN- to battery short
7. Cable is linked incorrectly (RIN+/RIN- connections reversed)
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Feature Description (continued)
NOTE
The device detects any of the above conditions, but does not report specifically which one
has occurred.
7.3.12 Oscillator Output
The deserializer provides an optional TxCLKOUT± output when the input clock (serial stream) has been lost.
This is based on an internal oscillator and may be controlled from register 0x02, bit 5 (OSC Clock Output Enable)
Table 8.
7.3.13 Interrupt Pin (INTB / INTB_IN)
1. Read HDCP_ISR Register 0xC7. (Table 8)
2. On the serializer, set register (ICR) 0xC6[5] = 1 and 0xC6[0] = 1 to configure the interrupt.
3. On the serializer, read from ISR register 0xC7 to arm the interrupt for the first time.
4. When INTB_IN is set LOW, the INTB pin on the serializer also pulls low, indicating an interrupt condition.
5. The external controller detects INTB = LOW and reads the ISR register to determine the interrupt source.
Reading this register also clears and resets the interrupt.
The INTB_IN signal is sampled and required approximately 8.6 μs of the minimum setup and hold time.
8.6 μs = 30 bit per back channel frame / (5 Mbps rate × ±30% Variation) = 30 / (5E6 × 0.7)
Note that -30% is the worst case.
7.3.14 General-Purpose I/O
7.3.14.1 GPIO[3:0]
In normal operation, GPIO[3:0] may be used as general purpose IOs in either forward channel (outputs) or back
channel (inputs) mode. GPIO modes may be configured from the registers (Table 8). GPIO[1:0] are dedicated
pins and GPIO[3:2] are shared with I2S_DC and I2S_DD respectively. Note: if the DS90UB924-Q1 is paired with
a DS90UB921-Q1 or DS90UB925Q-Q1 serializer, the devices must be configured into 18-bit mode to allow
usage of GPIO pins on the serializer. To enable 18-bit mode, set serializer register 0x12[2] = 1. 18-bit mode is
auto-loaded into the deserializer from the serializer. See Table 1 for GPIO enable and configuration.
Table 1. DS90UB921-Q1/DS90UB925Q-Q1 GPIO Enable and Configuration
DESCRIPTION
DEVICE
FORWARD CHANNEL
BACK CHANNEL
GPIO3
DS90UB921-Q1/
DS90UB925Q-Q1
0x0F = 0x03
0x0F = 0x05
DS90UB924-Q1
0x1F = 0x05
0x1F = 0x03
GPIO2
DS90UB921-Q1/
DS90UB925Q-Q1
0x0E = 0x30
0x0E = 0x50
DS90UB924-Q1
0x1E = 0x50
0x1E = 0x30
GPIO1/GPIO1
(SER/DES)
DS90UB921-Q1/
DS90UB925Q-Q1
N/A
0x0E = 0x05
DS90UB924-Q1
N/A
0x1E = 0x03
GPO_REG5/GPIO1
(SER/DES)
DS90UB921-Q1/
DS90UB925Q-Q1
0x10 = 0x03
N/A
DS90UB924-Q1
0x1E = 0x05
N/A
GPIO0/GPIO0
(SER/DES)
DS90UB921-Q1/
DS90UB925Q-Q1
N/A
0x0D = 0x05
DS90UB924-Q1
N/A
0x1D = 0x03
GPO_REG4/GPIO0
(SER/DES)
DS90UB921-Q1/
DS90UB925Q-Q1
0x0F = 0x30
N/A
DS90UB924-Q1
0x1D = 0x05
N/A
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Table 2. DS90UB927Q-Q1 GPIO Enable and Configuration
DESCRIPTION
DEVICE
FORWARD CHANNEL
BACK CHANNEL
GPIO3
DS90UB927Q-Q1
0x0F = 0x03
0x0F = 0x05
DS90UB924-Q1
0x1F = 0x05
0x1F = 0x03
GPIO2
DS90UB927Q-Q1
0x0E = 0x30
0x0E = 0x50
DS90UB924-Q1
0x1E = 0x50
0x1E = 0x30
GPIO1
DS90UB927Q-Q1
0x0E = 0x03
0x0E = 0x05
DS90UB924-Q1
0x1E = 0x05
0x1E = 0x03
GPIO0
DS90UB927Q-Q1
0x0D = 0x03
0x0D = 0x05
DS90UB924-Q1
0x1D = 0x05
0x1D = 0x03
Note: GPO_REG4 of the DS90UB921-Q1 or DS90UB925-Q1 can be used as a forward channel GPIO,
outputting on GPIO0 of DS90UB924-Q1. This can be set as follows:
• Set DS90UB921-Q1 or DS90UB925-Q1 in 18-bit mode by mode pin = 1 or by register 0x12[2] = 1.
• Set DS90UB924-Q1 register 0x1D[0] = 1 and 0x1D[2] = 1; this will enable GPIO0 of DS90UB924-Q1 as
output.
• Set DS90UB921-Q1 or DS90UB925-Q1 register 0x0F[4] = 1 and 0x0F[5] = 1; this will enable GPO_REG4 of
DS90UB921-Q1 or DS90UB925-Q1 as input.
Similarly GPO_REG5 of DS90UB921-Q1 or DS90UB925-Q1 can output to GPIO1 of DS90UB924-Q1:
• Set DS90UB921-Q1 or DS90UB925-Q1 in 18-bit mode by mode pin = 1 or by register 0x12[2] = 1.
• Set DS90UB924-Q1 register 0x1E[0] = 1 and 0x1E[2] = 1; this will enable GPIO1 of DS90UB924-Q1 as
output.
• Set DS90UB921-Q1 or DS90UB925-Q1 register 0x10[0] = 1 and 0x10[1] = 1; this will enable GPO_REG5
DS90UB921-Q1 or DS90UB925-Q1 as input.
The input value present on GPIO[3:0] may also be read from register or configured to local output mode
(Table 8).
7.3.14.2 GPIO[8:5]
GPIO_REG[8:5] are register-only GPIOs and may be programmed as outputs or read as inputs through local
register bits only. Where applicable, these bits are shared with I2S pins and override I2S input if enabled into
GPIO_REG mode. See Table 3 for GPIO enable and configuration.
Note: Local GPIO value may be configured and read either through local register access, or remote register
access through the Low-Speed Bidirectional Control Channel. Configuration and state of these pins are not
transported from serializer to deserializer as is the case for GPIO[3:0].
Table 3. GPIO_REG and GPIO Local Enable and Configuration
DESCRIPTION
REGISTER CONFIGURATION
GPIO_REG8
0x21 = 0x01
Output, L
0x21 = 0x09
Output, H
0x21 = 0x03
Input, Read: 0x6F[0]
GPIO_REG7
GPIO_REG6
GPIO_REG5
FUNCTION
0x21 = 0x01
Output, L
0x21 = 0x09
Output, H
0x21 = 0x03
Input, Read: 0x6E[7]
0x20 = 0x01
Output, L
0x20 = 0x09
Output, H
0x20 = 0x03
Input, Read: 0x6E[6]
0x20 = 0x01
Output, L
0x20 = 0x09
Output, H
0x20 = 0x03
Input, Read: 0x6E[5]
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Table 3. GPIO_REG and GPIO Local Enable and Configuration (continued)
DESCRIPTION
REGISTER CONFIGURATION
FUNCTION
GPIO3
0x1F = 0x01
Output, L
GPIO2
GPIO1
GPIO0
0x1F = 0x09
Output, H
0x1F = 0x03
Input, Read: 0x6E[3]
0x1E = 0x01
Output, L
0x1E = 0x09
Output, H
0x1E = 0x03
Input, Read: 0x6E[2]
0x1E = 0x01
Output, L
0x1E = 0x09
Output, H
0x1E = 0x03
Input, Read: 0x6E[1]
0x1D = 0x01
Output, L
0x1D = 0x09
Output, H
0x1D = 0x03
Input, Read: 0x6E[0]
7.3.15 I2S Audio Interface
The DS90UB924-Q1 deserializer features six I2S output pins that, when paired with a DS90UB927Q-Q1
serializer, supports surround-sound audio applications. The bit clock (I2S_CLK) supports frequencies between 1
MHz and the smaller of < PCLK/4 or < 13 MHz. Four I2S data outputs carry two channels of I2S-formatted digital
audio each, with each channel delineated by the word select (I2C_WC) input. The I2S audio interface is not
available in Backwards Compatibility Mode (BKWD = 1).
Deserializer
MCLK
I2S_CLK
I2S_WC
I2S_Dx
System Clock
Bit Clock
Word Select 4
Data
I2S Receiver
Figure 22. I2S Connection Diagram
I2S_WC
I2S_CLK
I2S_Dx
MSB
LSB
MSB
LSB
Figure 23. I2S Frame Timing Diagram
When paired with a DS90UB921-Q1 or DS90UB925Q-Q1, the DS90UB924-Q1 I2S interface supports a single
I2S data output through I2S_DA (24-bit video mode), or two I2S data outputs through I2S_DA and I2S_DB (18bit video mode).
7.3.15.1 I2S Transport Modes
By default, packetized audio is received during video blanking periods in dedicated data island transport frames.
The transport mode is set in the serializer and auto-loaded into the deserializer by default. The audio
configuration may be disabled from control registers if Forward Channel Frame Transport of I2S data is desired.
In frame transport, only I2S_DA is received to the DS90UB924-Q1 deserializer. Surround Sound Mode, which
transmits all four I2S data inputs (I2S_D[D:A]), may only be operated in Data Island Transport mode. This mode
is only available when connected to a DS90UB927Q-Q1 serializer. If connected to a DS90UB921-Q1 or
DS90UB925Q-Q1 serializer, only I2S_DA and I2S_DB may be received.
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7.3.15.2 I2S Repeater
I2S audio may be fanned-out and propagated in the repeater application. By default, data is propagated via data
island transport on the FPD-Link (OpenLDI) interface during the video blanking periods. If frame transport is
desired, connect the I2S pins from the deserializer to all serializers. Activating surround sound at the top-level
serializer automatically configures downstream serializers and deserializers for surround-sound transport utilizing
Data Island Transport. If 4-channel operation utilizing I2S_DA and I2S_DB only is desired, this mode must be
explicitly set in each serializer and deserializer control register throughout the repeater tree (Table 8).
A DS90UB924-Q1 deserializer configured in repeater mode may also regenerate I2S audio from its I2S input
pins in lieu of Data Island frames. See Figure 31 and the I2C control registers (Table 8) for additional details.
7.3.15.3 I2S Jitter Cleaning
The DS90UB924-Q1 features a standalone PLL to clean the I2S data jitter, supporting high-end car audio
systems. If I2S_CLK frequency is less than 1 MHz, this feature must be disabled through register 0x2B[7]. See
Table 8.
7.3.15.4 MCLK
The deserializer has an I2S Master Clock Output (MCLK). It supports ×1, ×2, or ×4 of I2S CLK Frequency. When
the I2S PLL is disabled, the MCLK output is off. Table 4 covers the range of I2S sample rates and MCLK
frequencies. By default, all the MCLK output frequencies are ×2 of the I2S CLK frequencies. The MCLK
frequencies can also be enabled through the register bits 0x3A[6:4] (I2S DIVSEL), shown in Table 8. To select
desired MCLK frequency, write 0x3A[7], then write to bit [6:4] accordingly.
Table 4. Audio Interface Frequencies
SAMPLE RATE
(kHz)
I2S DATA WORD SIZE (BITS)
32
1.024
44.1
48
I2S_CLK (MHz)
1.4112
16
96
192
1.536
3.072
6.144
MCLK OUTPUT (MHz)
REGISTER 0x3A[6:4]'b
I2S_CLK x1
000
I2S_CLK x2
001
I2S_CLK x4
010
I2S_CLK x1
000
I2S_CLK x2
001
I2S_CLK x4
010
I2S_CLK x1
000
I2S_CLK x2
001
I2S_CLK x4
010
I2S_CLK x1
001
I2S_CLK x2
010
I2S_CLK x4
011
I2S_CLK x1
010
I2S_CLK x2
011
I2S_CLK x4
100
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Table 4. Audio Interface Frequencies (continued)
SAMPLE RATE
(kHz)
I2S DATA WORD SIZE (BITS)
32
1.536
44.1
48
2.117
24
96
2.304
4.608
192
9.216
32
2.048
44.1
48
I2S_CLK (MHz)
2.8224
32
96
192
3.072
6.144
12.288
MCLK OUTPUT (MHz)
REGISTER 0x3A[6:4]'b
I2S_CLK x1
000
I2S_CLK x2
001
I2S_CLK x4
010
I2S_CLK x1
001
I2S_CLK x2
010
I2S_CLK x4
011
I2S_CLK x1
001
I2S_CLK x2
010
I2S_CLK x4
011
I2S_CLK x1
010
I2S_CLK x2
011
I2S_CLK x4
100
I2S_CLK x1
011
I2S_CLK x2
100
I2S_CLK x4
101
I2S_CLK x1
001
I2S_CLK x2
010
I2S_CLK x4
011
I2S_CLK x1
001
I2S_CLK x2
010
I2S_CLK x4
011
I2S_CLK x1
001
I2S_CLK x2
010
I2S_CLK x4
011
I2S_CLK x1
010
I2S_CLK x2
011
I2S_CLK x4
100
I2S_CLK x1
011
I2S_CLK x2
100
I2S_CLK x4
110
7.3.16 AV Mute Prevention
The DS90UB924-Q1 may inadvertently enter the AV MUTE state if the serializer sends video data during
blanking period (DE = L) with a specific data pattern (24’h666666). Once the device enters the AV MUTE
state, the device mutes both audio and video outputs resulting in a black display screen. Setting the gate DE
Register 0x04[4] on the serializer will prevent video signals from being sent during the blanking interval. This
will ensure AV MUTE mode is not entered during normal operation
If unexpected AV MUTE state is seen, it is recommended to verify checking the data path control setting of
the paired Serializer. This setting is not accessible from DS90UB924-Q1.
7.3.17 OEN Toggling Limitation
OEN must be enabled LVDS outputs after PDB turns to high state and the internal circuit is stabled. Since OEN
function is asynchronous signal to internal digital blocks, repeatedly OEN toggling may result in horizontal pixel
shift at the LVDS output. To avoid this, recommend to reset by programming Register 0x01[0] for digital blocks
after OEN turns to ON state.
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7.4 Device Functional Modes
7.4.1 Clock and Output Status
When PDB is driven HIGH, the CDR PLL begins locking to the serial input, and LOCK is TRI-STATE or LOW
(depending on the value of the OEN setting). After the deserializer completes its lock sequence to the input serial
data, the LOCK output is driven HIGH, indicating valid data and clock recovered from the serial input is available
on the LVCMOS and LVDS outputs. The state of the outputs is based on the OEN and OSS_SEL setting
(Table 5) or register bit (Table 8).
Table 5. Output State Table
INPUTS
SERIAL
INPUT
OUTPUTS
LOCK
PASS
DATA/GPIO/I2S
TxCLKOUT/Tx
OUT[3:0]
X
Z
Z
Z
Z
L
L or H
L
L
L
H
L or H
Z
Z
Z
PDB
OEN
OSS_SEL
X
L
X
X
H
L
X
H
L
Static
H
H
L
L
L
L
L/OSC (Register
EN)
L
Static
H
H
H
L
Previous Status
L
Active
H
H
L
L
L
L
L
Active
H
H
H
H
Valid
Valid
Valid
7.4.2 FPD-Link (OpenLDI) Input Frame and Color Bit Mapping Select
The DS90UB924-Q1 can be configured to output 24-bit color (RGB888) or 18-bit color (RGB666) with 2 different
mapping schemes, shown in Figure 24, or MSBs on TxOUT[3], shown in Figure 25. Each frame corresponds to a
single pixel clock (PCLK) cycle. The LVDS clock output from TxCLKOUT± follows a 4:3 duty cycle scheme, with
each 28-bit pixel frame starting with two LVDS bit clock periods high, three low, and ending with two high. The
mapping scheme is controlled by MAPSEL pin or by Register (Table 8).
TxCLKOUT
Previous cycle
Current cycle
TxOUT3
B[1]
(bit 26)
B[0]
(bit 25)
G[1]
(bit 24)
G[0]
(bit 23)
R[1]
(bit 22)
R[0]
(bit 21)
TxOUT2
DE
(bit 20)
VS
(bit 19)
HS
(bit 18)
B[7]
(bit 17)
B[6]
(bit 16)
B[5]
(bit 15)
B[4]
(bit 14)
TxOUT1
B[3]
(bit 13)
B[2]
(bit 12)
G[7]
(bit 11)
G[6]
(bit 10)
G[5]
(bit 9)
G[4]
(bit 8)
G[3]
(bit 7)
TxOUT0
G[2]
(bit 6)
R[7]
(bit 5)
R[6]
(bit 4)
R[5]
(bit 3)
R[4]
(bit 2)
R[3]
(bit 1)
R[2]
(bit 0)
Figure 24. 24-bit Color FPD-Link (OpenLDI) Mapping: LSBs on TxOUT3 (MAPSEL=L)
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TxCLKOUT
Previous cycle
Current cycle
TxOUT3
B[7]
(bit 26)
B[6]
(bit 25)
G[7]
(bit 24)
G[6]
(bit 23)
R[7]
(bit 22)
R[6]
(bit 21)
TxOUT2
DE
(bit 20)
VS
(bit 19)
HS
(bit 18)
B[5]
(bit 17)
B[4]
(bit 16)
B[3]
(bit 15)
B[2]
(bit 14)
TxOUT1
B[1]
(bit 13)
B[0]
(bit 12)
G[5]
(bit 11)
G[4]
(bit 10)
G[3]
(bit 9)
G[2]
(bit 8)
G[1]
(bit 7)
TxOUT0
G[0]
(bit 6)
R[5]
(bit 5)
R[4]
(bit 4)
R[3]
(bit 3)
R[2]
(bit 2)
R[1]
(bit 1)
R[0]
(bit 0)
Figure 25. 24-bit Color FPD-Link (OpenLDI) Mapping: MSBs on TxOUT3 (MAPSEL=H)
TxCLKOUT
Previous cycle
Current cycle
TxOUT3
TxOUT2
DE
(bit 20)
VS
(bit 19)
HS
(bit 18)
B[5]
(bit 17)
B[4]
(bit 16)
B[3]
(bit 15)
B[2]
(bit 14)
TxOUT1
B[1]
(bit 13)
B[0]
(bit 12)
G[5]
(bit 11)
G[4]
(bit 10)
G[3]
(bit 9)
G[2]
(bit 8)
G[1]
(bit 7)
TxOUT0
G[0]
(bit 6)
R[5]
(bit 5)
R[4]
(bit 4)
R[3]
(bit 3)
R[2]
(bit 2)
R[1]
(bit 1)
R[0]
(bit 0)
Figure 26. 18-bit Color FPD-Link (OpenLDI) Mapping (MAPSEL = L)
TxCLKOUT
Previous cycle
Current cycle
TxOUT3
DE
(bit 20)
TxOUT2
B[5]
(bit 26)
B[4]
(bit 25)
G[5]
(bit 24)
G[4]
(bit 23)
R[5]
(bit 22)
R[4]
(bit 21)
VS
(bit 19)
HS
(bit 18)
B[3]
(bit 17)
B[2]
(bit 16)
B[1]
(bit 15)
B[0]
(bit 14)
G[3]
(bit 11)
G[2]
(bit 10)
G[1]
(bit 9)
G[0]
(bit 8)
R[2]
(bit 4)
R[1]
(bit 3)
R[0]
(bit 2)
TxOUT1
R[3]
(bit 5)
TxOUT0
Figure 27. 18-bit Color FPD-Link (OpenLDI) Mapping (MAPSEL = H)
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DS90UB924-Q1
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SNLS512 – APRIL 2016
7.4.3 Low Frequency Optimization (LFMODE)
The LFMODE is set via register (Table 8) or by the LFMODE Pin. This mode optimizes device operation for
lower input data clock ranges supported by the serializer. If LFMODE is Low (LFMODE=0, default), the
TxCLKOUT± PCLK frequency is between 15 MHz and 96 MHz. If LFMODE is High (LFMODE=1), the
TxCLKOUT± frequency is between 5 MHz and
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