LM27222
www.ti.com
SNVS306B – SEPTEMBER 2004 – REVISED MARCH 2013
LM27222 High-Speed 4.5A Synchronous MOSFET Driver
Check for Samples: LM27222
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
•
•
The LM27222 is a dual N-channel MOSFET driver
designed to drive MOSFETs in push-pull
configurations as typically used in synchronous buck
regulators. The LM27222 takes the PWM output from
a controller and provides the proper timing and drive
levels to the power stage MOSFETs. Adaptive shootthrough protection prevents damaging and efficiency
reducing shoot-through currents, thus ensuring a
robust design capable of being used with nearly any
MOSFET. The adaptive shoot-through protection
circuitry also reduces the dead time down to as low
as 10ns, ensuring the highest operating efficiency.
The peak sourcing and sinking current for each driver
of the LM27222 is about 3A and 4.5Amps
respectively with a Vgs of 5V. System performance is
also enhanced by keeping propagation delays down
to 8ns. Efficiency is once again improved at all load
currents
by
supporting
synchronous,
nonsynchronous, and diode emulation modes through the
LEN pin. The minimum output pulse width realized at
the output of the MOSFETs is as low as 30ns. This
enables high operating frequencies at very high
conversion ratios in buck regulator designs. To
support low power states in notebook systems, the
LM27222 draws only 5µA from the 5V rail when the
IN and LEN inputs are low or floating.
1
2
•
•
Adaptive Shoot-through Protection
10ns Dead Time
8ns Propagation Delay
30ns Minimum On-time
0.4Ω Pull-down and 0.9Ω Pull-up Drivers
4.5A Peak Driving Current
MOSFET Tolerant Design
5µA Quiescent Current
30V Maximum Input Voltage in Buck
Configuration
4V to 6.85V Operating Voltage
SOIC-8 and WSON Packages
APPLICATIONS
•
•
•
•
High Current Buck And Boost Voltage
Converters
Fast Transient DC/DC Power Supplies
Single Ended Forward Output Rectification
CPU And GPU Core Voltage Regulators
Typical Application
VCC
4V to 6.85V
D1
R1
C1
C2
0.33 PF
U1
6
VCC
(to controller) 5
(to controller) 4
8
GND
+
C3
CB
LEN
HG
LM27222
IN
VIN
Q1
SW
LG
up to 30V
3
L1
2
1
Q2
VOUT
C4
+
0.5V to
Vin - 0.5V
7
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2013, Texas Instruments Incorporated
LM27222
SNVS306B – SEPTEMBER 2004 – REVISED MARCH 2013
www.ti.com
Connection Diagram
SW
1
8
GND
HG
2
7
LG
CB
3
6
VCC
IN
4
5
LEN
Figure 1. Top View
SOIC-8 (Package # D0008A) θJA = 172°C/W
or
WSON-8 (Package # NGT0008A) θJA = 39°C/W
PIN DESCRIPTIONS
Pin #
Pin Name
Pin Function
1
SW
High-side driver return. Should be connected to the common node of high and low-side MOSFETs.
2
HG
High-side gate drive output. Should be connected to the high-side MOSFET gate. Pulled down internally to
SW with a 10K resistor to prevent spurious turn on of the high-side MOSFET when the driver is off.
3
CB
Bootstrap. Accepts a bootstrap voltage for powering the high-side driver.
4
IN
Accepts a PWM signal from a controller. Active High. Pulled down internally to GND with a 150K resistor to
prevent spurious turn on of the high-side MOSFET when the controller is inactive.
5
LEN
Low-side gate enable. Active High. Pulled down internally to GND with a 150K resistor to prevent spurious
turn-on of the low-side MOSFET when the controller is inactive.
6
VCC
Connect to +5V supply.
7
LG
Low-side gate drive output. Should be connected to low-side MOSFET gate. Pulled down internally to GND
with a 10K resistor to prevent spurious turn on of the low-side MOSFET when the driver is off.
8
GND
Ground.
Block Diagram
CB
VCC
Level
Shifter
HG
10k
SW
LEN
+
150k
Logic
IN
150k
LG
10k
Shoot-through
Protection
GND
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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SNVS306B – SEPTEMBER 2004 – REVISED MARCH 2013
Absolute Maximum Ratings
(1)
VCC to GND
-0.3V to 7V
CB to GND
-0.3V to 36V
CB to SW
SW to GND
-0.3V to 7V
(2)
-2V to 36V
-0.3V to VCC + 0.3V ≤ 7V
LEN, IN, LG to GND
HG to GND
-0.3V to 36V
Junction Temperature
+150°C
(3)
720mW
Storage Temperature
−65° to 150°C
ESD Susceptibility
Human Body Model
2kV
Power Dissipation
(1)
(2)
(3)
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating ratings are conditions under which
the device operates correctly. Operating Ratings do not imply ensured performance limits.
The SW pin can have -2V to -0.5 volts applied for a maximum duty cycle of 10% with a maximum period of 1 second. There is no duty
cycle or maximum period limitation for a SW pin voltage range of -0.5V to 30 Volts.
Maximum allowable power dissipation is a function of the maximum junction temperature, TJMAX, the junction-to-ambient thermal
resistance, θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated
using: PMAX = (TJMAX-TA) / θJA. The junction-to-ambient thermal resistance, θJA, for the LM27222M, it is 165°C/W. For a TJMAX of 150°C
and TA of 25°C, the maximum allowable power dissipation is 0.76W. The θJA for the LM27222SD is 42°C/W. For a TJMAX of 150°C and
TA of 25°C, the maximum allowable power dissipation is 3W.
Operating Ratings
(1)
VCC
4V to 6.85V
−40° to 125°C
Junction Temperature Range
CB (max)
(1)
33V
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating ratings are conditions under which
the device operates correctly. Operating Ratings do not imply ensured performance limits.
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LM27222
SNVS306B – SEPTEMBER 2004 – REVISED MARCH 2013
Electrical Characteristics
www.ti.com
(1)
VCC = CB = 5V, SW = GND = 0V, unless otherwise specified. Typicals and limits appearing in plain type apply for TA = TJ =
+25°C. Limits appearing in boldface type apply over the entire operating temperature range (-40°C ≤ TJ ≤ 125°C).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
5
15
µA
POWER SUPPLY
Iq_op
Operating Quiescent Current
IN = 0V, LEN = 0V
30
IN = 0V, LEN = 5V
500
540
650
µA
825
HIGH-SIDE DRIVER
Peak Pull-up Current
RH-pu
Pull-up Rds_on
3
ICB = IHG = 0.3A
0.9
Peak Pull-down Current
RH-pd
A
2.5
Ω
1.5
Ω
4.5
A
Pull-down Rds_on
ISW = IHG = 0.3A
0.4
t4
Rise Time
Timing Diagram, CLOAD = 3.3nF
17
ns
t6
Fall Time
Timing Diagram, CLOAD = 3.3nF
12
ns
t3
Pull-up Dead Time
Timing Diagram
9.5
ns
t5
Pull-down Delay
Timing Diagram
16.5
ns
30
ns
3.2
A
ton_min
Minimum Positive Output
Pulse Width
LOW-SIDE DRIVER
Peak Pull-up Current
RL-pu
Pull-up Rds_on
IVCC = ILG = 0.3A
0.9
Peak Pull-down Current
RL-pd
2.5
Ω
1.5
Ω
4.5
A
Pull-down Rds_on
IGND = ILG = 0.3A
0.4
t8
Rise Time
Timing Diagram, CLOAD = 3.3nF
17
ns
t2
Fall Time
Timing Diagram, CLOAD = 3.3nF
14
ns
t7
Pull-up Dead Time
Timing Diagram
11.5
ns
t1
Pull-down Delay
Timing Diagram
7.7
ns
HG-SW Pull-down Resistance
10k
Ω
LG-GND Pull-down
Resistance
10k
Ω
LEN-GND Pull-down
Resistance
150K
Ω
IN-GND Pull-down Resistance
150K
Ω
PULL-DOWN RESISTANCES
LEAKAGE CURRENTS
Ileak_IN
Ileak_LEN
IN pin Leakage Current
LEN pin Leakage Current
IN = 0V, Source Current
50
nA
IN = 5V, Sink Current
33
µA
LEN = 0V, Source Current
200
nA
LEN = 5V, Sink Current
33
µA
LOGIC
VIH_LEN
LEN Low to High Threshold
Low to High Transition
VIL_LEN
LEN High to Low Threshold
High to Low Transition
VIH_IN
IN Low to High Threshold
Low to High Transition
VIL_IN
IN High to Low Threshold
High to Low Transition
Threshold Hysteresis
(1)
4
65
30
% of VCC
% of VCC
65
30
% of VCC
% of VCC
0.7
V
Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation
using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).
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SNVS306B – SEPTEMBER 2004 – REVISED MARCH 2013
Timing Diagram
IN
t2
t5
t1
t7
t8
0.9V
LG
t3
t6
t4
HG-SW
0.9V
Typical Waveforms
IN
IN
HG-SW
HG-SW
LG
LG
40 ns/DIV
40 ns/DIV
Figure 2. PWM Low-to-High Transition at IN Input
Figure 3. PWM High-to-Low Transition at IN Input
IN
LEN
HG
LG
400 ns/DIV
Figure 4. LEN Operation
The typical waveforms are from a circuit similar to Typical Application with:
Q1: 2 x Si7390DP
Q2: 2 x Si7356DP
L1: 0.4 µH
VIN: 12V
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LM27222
SNVS306B – SEPTEMBER 2004 – REVISED MARCH 2013
www.ti.com
APPLICATION INFORMATION
GENERAL
The LM27222 is designed for high speed and high operating reliability. The driver can handle very narrow, down
to zero, PWM pulses in a specified, deterministic way. Therefore, the HG and LG outputs are always in
predictable states. No latches are used in the HG and LG control logic so the drivers cannot get "stuck" in the
wrong state. The driver design allows for powering up with a pre-biasing voltage being present at the regulator
output. To reduce conduction losses in DC-DC converters with low duty factors the LM27222 driver can be
powered from a 6.5V ±5% power rail.
It is recommended to use the same power rail for both the controller and driver. If two different power rails are
used, never allow the PWM pulse magnitude at the IN input or the control voltage at the LEN input to be above
the driver VCC voltage or unpredictable HG and LG outputs pulse widths may result.
MINIMUM PULSE WIDTH
As the input pulse width to the IN pin is decreased, the pulse width of the high-side gate drive (HG-SW) also
decreases. However, for input pulse widths 60ns and smaller, the HG-SW remains constant at 30ns. Thus the
minimum pulse width of the driver output is 30ns. Figure 5 shows an input pulse at the IN pin 20ns wide, and the
output of the driver, as measured between the nodes HG and SW is a 30ns wide pulse. Figure 6 shows the
variation of the SW node pulse width vs IN pulse width. At the IN pin, if a falling edge is followed by a rising edge
within 5ns, the HG may ignore the rising edge and remain low until the IN pin toggles again. If a rising edge is
followed by a falling edge within 5ns, the pulse may be completely ignored.
120
100
80
tON_SW (ns)
IN
60
40
HG-SW
20
0
20 ns/DIV
20
40
60
80
100
120
140
tON (ns)
Figure 5. Min On Time
Figure 6.
ADAPTIVE SHOOT-THROUGH PROTECTION
The LM27222 prevents shoot-through power loss by ensuring that both the high- and low-side MOSFETs are not
conducting at the same time. When the IN signal rises, LG is first pulled down. The adaptive shoot-through
protection circuit waits for LG to reach 0.9V before turning on HG. Similarly, when IN goes low, HG is pulled
down first, and the circuit turns LG on only after the voltage difference between the high-side gate and the switch
node, i.e., HG-SW, has fallen to 0.9V.
It is possible in some applications that at power-up the driver's SW pin is above 3V in either buck or boost
comverter applications. For instance, in a buck configuration a pre-biasing voltage can be either a voltage from
anothert power rail connected to the load, or a leakage voltage through the load, or it can be an output capacitor
pre-charged above 3V while no significant load is present. In a boost application it can be an input voltage rail
above 3V.
6
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In the case of insufficient initial CB-SW voltage (less than 2V) such as when the output rail is pre-biased, the
shoot-through protection circuit holds LG low for about 170ns, beginning from the instant when IN goes high.
After the 170ns delay, the status of LG is dictated by LEN and IN. Once LG goes high and SW goes low, the
bootstrap capacitor will be charged up (assuming SW is grounded for long enough time). As a result, CB-SW will
be close to 5V and the LM27222 will now fully support synchronous operation.
The dead-time between the high- and low-side pulses is kept as small as possible to minimize conduction
through the body diode of the low-side MOSFET(s).
POWER DISSIPATION
The power dissipated in the driver IC when switching synchronously can be calculated as follows:
fSW x VCC
P=
2
^Q
G-H
RH-pd
RH-pu
RH-pu + RG-H
+
RH-pd + RG-H
RL-pd
RL-pu
+
+ QG-L R + R
RL-pd + RG-L
L-pu
G-L
^
where
•
•
•
•
•
•
•
•
•
•
where fSW = switching frequency
VCC = voltage at the VCC pin
QG_H = total gate charge of the (parallel combination of the) high-side MOSFET(s)
QG_L = total gate charge of the (parallel combination of the) low-side MOSFET(s)
RG_H = gate resistance of the (parallel combination of the) high-side MOSFET(s)
RG_L = gate resistance of the (parallel combination of the) low-side MOSFET(S)
RH_pu = pull-up RDS_ON of the high-side driver
RH_pd = pull-down RDS_ON of the high-side driver
RL_pu = pull-up RDS_ON of the low-side driver
RL_pd = pull-down RDS_ON of the low-side driver
(1)
PC BOARD LAYOUT GUIDELINES
1. Place the driver as close to the MOSFETs as possible.
2. HG, SW, LG, GND: Run short, thick traces between the driver and the MOSFETs. To minimize parasitics,
the traces for HG and SW should run parallel and close to each other. The same is true for LG and GND.
3. Driver VCC: Place the decoupling capacitor close to the VCC and GND pins.
4. The high-current loop between the high-side and low-side MOSFETs and the input capacitors should be as
small as possible.
5. There should be enough copper area near the MOSFETs and the inductor for heat dissipation. Vias may
also be added to carry the heat to other layers.
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LM27222
SNVS306B – SEPTEMBER 2004 – REVISED MARCH 2013
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TYPICAL APPLICATION CIRCUIT DESCRIPITON
The Application Example on the following page shows the LM27222 being used with the LM27212, a 2-phase
hysteretic current mode controller. Although this circuit is capable of operating from 5V to 28V, the components
are optimized for an input voltage range of 9V to 28V. The high-side FET is selected for low gate charge to
reduce switching losses. For low duty cycles, the average current through the high-side FET is relatively small
and thus we trade off higher conduction losses for lower switching losses. The low-side FET is selected solely on
RDS_ON to minimize conduction losses. If the input voltage range were 4V to 6V, the MOSFET selection should
be changed. First, much lower voltage FETs can be used, and secondly, high-side FET RDS_ON becomes a larger
loss factor than the switching losses. Of course with a lower input voltage, the input capacitor voltage rating can
be reduced and the inductor value can be reduced as well. For a 4V to 6V application, the inductor can be
reduced to 200nH to 300nH. The switching frequency of the LM27212 is determined by the allowed ripple current
in the inductor. This circuit is set for approximately 300kHz. At lower input voltages, higher frequencies are
possible without suffering a significant efficiency loss. Although the LM27222 can support operating frequencies
up to 2MHz in many applications, the LM27212 should be limited to about 1MHz. The control architecture of the
LM27212 and the low propagation times of the LM27222 potentially gives this solution the fastest transient
response in the industry.
Application Example
VCC5
R1
R6
10:
C1
0.1 PF
1.5:
R7
1.5:
LM27212
U1
VDD
OUT1
SYNC1
OUT2
SYNC2
VREF
CMP1
CMP2
CMPREF
GND
VIN
D1
+
C2
1 PF,
6.3V
U2
LM27222
VCC
LEN
IN
GND
C4 0.33 PF
CB
HG
SW
LG
C6
10 PF x 6
Q1 *
L1
0.6 PH
30A
R8
1 m:
Q2
**
R2
121:
D2
R3
VIN
121:
C3 1 PF,
6.3V
U3
LM27222
VCC
LEN
IN
GND
C5
0.33 PF
Q3
*
VOUT
+
CB
HG
SW
LG
L2
R9
0.6 PH
30A
1 m:
C7
270 PF x 3
ESR = 9 m:
/cap
Q4
**
R4
60.4:
R5
60.4:
* Q1, Q3: 2 x Si7390DP
** Q2, Q4: 2 x Si7356DP
8
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SNVS306B – SEPTEMBER 2004 – REVISED MARCH 2013
REVISION HISTORY
Changes from Revision A (March 2013) to Revision B
•
Page
Changed layout of National Data Sheet to TI format ............................................................................................................ 8
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PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LM27222M
NRND
SOIC
D
8
95
TBD
Call TI
Call TI
-40 to 125
27222
M
LM27222M/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
27222
M
LM27222MX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
27222
M
LM27222SD
NRND
WSON
NGT
8
TBD
Call TI
Call TI
-40 to 125
L27222S
LM27222SD/NOPB
ACTIVE
WSON
NGT
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L27222S
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2015
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LM27222MX/NOPB
SOIC
D
8
2500
330.0
12.4
6.5
5.4
2.0
8.0
12.0
Q1
LM27222SD/NOPB
WSON
NGT
8
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Sep-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM27222MX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
LM27222SD/NOPB
WSON
NGT
8
1000
210.0
185.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
NGT0008A
SDC08A (Rev A)
www.ti.com
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