Order
Now
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
Reference
Design
LM27402
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
LM27402 High-Performance Synchronous Buck Controller With DCR Current Sensing
1 Features
3 Description
•
•
The LM27402 is a voltage-mode, synchronous,
DC/DC step-down controller with lossless inductor
DCR current sensing capability. Sensing the inductor
current eliminates the need to add resistive
powertrain elements, which increases overall
efficiency and facilitates accurate, continuous current
sensing. A 0.6-V ±1% voltage reference enables high
accuracy and low voltage capability at the output. An
input operating voltage range of 3 V to 20 V makes
the LM27402 suitable for a large variety of input rails.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Wide Input-Voltage Range of 3 V to 20 V
Inductor DCR or Shunt Resistor Based
Overcurrent Protection
0.6-V Reference With ±1% FB Accuracy Across
Full –40°C to 125°C Junction Temperature Range
Switching Frequency from 200 kHz to 1.2 MHz
Output Voltage as High as 95% of Input Voltage
Integrated High-Current MOSFET Drivers
Internal VDD Bias Supply LDO Subregulator
External Clock Synchronization
Adjustable Soft Start With External Capacitor
Prebiased Start-up Capability
Power Supply Tracking
Voltage-Mode Control With Line Feedforward
Open-Drain Power-Good Indicator
Precision Enable With Hysteresis
16-Pin HTSSOP and WQFN Packages
Create a Custom Design Using the LM27402 With
the WEBENCH® Power Designer
The LM27402 voltage-mode control loop incorporates
input voltage feed forward to maintain stability
throughout the entire input-voltage range. The
switching frequency is adjustable from 200 kHz to
1.2 MHz. Dual, high-current, integrated MOSFET
drivers support large QG, low RDS(on) power
MOSFETs. A power-good indicator provides powerrail-sequencing capability and output fault detection.
An adjustable external soft start limits inrush current
and provides monotonic output control during startup. Other features include external tracking of other
power supplies, integrated LDO bias supply, and
synchronization capability.
Device Information(1)
2 Applications
•
•
•
•
•
PART NUMBER
High-Current, Low-Voltage Supply for FPGA and
ASIC
General-Purpose, High-Current Buck Converters
DC/DC Converters and POL Modules
Telecom, Datacom, Networking, Distributed Power
Architectures
Cryptocurrency Miners (Bitcoin, Ethereum,
Litecoin)
LM27402
PACKAGE
BODY SIZE (NOM)
WQFN (16)
4.00 mm × 4.00 mm
HTSSOP (16)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Circuit
VOUT+
VDD
CS+
SS/TRACK
CS±
VIN
CBOOT
FB
HG
VOUT+
COMP
SW
LM27402
LG
VIN
VDD
EN
SYNC
PGOOD
FADJ
GND
VOUT±
GND
VIN
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM27402
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
5
5
5
7
7
8
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Typical Performance Characteristics ........................
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 16
8
Application and Implementation ........................ 18
8.1 Application Information............................................ 18
8.2 Typical Applications ............................................... 32
9 Power Supply Recommendations...................... 37
10 Layout................................................................... 37
10.1 Layout Guidelines ................................................. 37
10.2 Layout Example .................................................... 40
11 Device and Documentation Support ................. 41
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
41
41
41
42
42
42
42
12 Mechanical, Packaging, and Orderable
Information ........................................................... 42
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision J (July 2015) to Revision K
•
Added "Cryptocurrency Miners (Bitcoin, Ethereum, Litecoin" to Applications; add links for WEBENCH .............................. 1
Changes from Revision I (March 2013) to Revision J
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
Changes from Revision H (March 2013) to Revision I
•
Page
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 36
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
LM27402
www.ti.com
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
5 Pin Configuration and Functions
PWP Package
16-Pin HTSSOP
Top View
15 HG
SS/TRACK 3
14 SW
FB 4
13 LG
EP
COMP 5
CBOOT
CS- 2
HG
16 CBOOT
CS-
CS+ 1
CS+
RUM Package
16-Pin WQFN
Top View
16
15
14
13
SS/TRACK
1
12
SW
FB
2
11
LG
12 VDD
FADJ 6
11 GND
SYNC 7
10 VIN
EP
PGOOD
3
10
VDD
FADJ
4
9
GND
EN
5
6
7
8
PGOOD
COMP
VIN
9
SYNC
EN 8
Pin Functions
PIN
I/O (1)
DESCRIPTION
13
P
High-side gate driver supply rail. Connect a 100-nF ceramic capacitor from CBOOT to
SW and a Schottky diode from VDD to CBOOT.
5
3
O
Output of the internal error amplifier. The COMP voltage is compared to an internally
generated ramp at the PWM comparator to establish the duty cycle command.
CS+
1
16
I
Current sense positive input. This pin is the noninverting input to the current-sense
comparator.
CS–
2
15
I
Current sense negative input. This pin is the inverting input to the current-sense
comparator. 10-µA of nominal offset current is provided for adjustable current limit
setpoint.
NAME
HTSSOP
WQFN
CBOOT
16
COMP
EN
8
5
I
LM27402 enable pin. Apply a voltage typically higher than 1.17 V to EN and the
LM27402 will begin to switch if VIN and VDD have exceeded their UVLO thresholds.
A hysteresis of 100 mV on EN provides noise immunity. EN is internally tied to VDD
through a 2-µA pullup current source. EN must not exceed the voltage on VDD.
FADJ
6
4
I
Frequency adjust input. The switching frequency is programmable between 200 kHz
and 1.2 MHz by connecting a resistor between FADJ and GND.
FB
4
2
I
Feedback input. Inverting input to the error amplifier to set the output voltage and
compensate the voltage-mode control loop.
GND
11
9
G
Common ground connection. This pin provides the power and signal return
connections for analog functions, including low-side MOSFET gate return, soft-start
capacitor, and frequency adjust resistor.
HG
15
14
O
High-side MOSFET gate drive output.
LG
13
11
O
Low-side MOSFET gate drive output.
O
Power Good monitor output. This open-drain output goes low during overcurrent,
short-circuit, UVLO, output overvoltage and undervoltage, overtemperature, or when
the output is not regulated (such as an output prebias). An external pullup resistor to
VDD or to an external rail is required. Included is a 20-μs deglitch filter. The PGOOD
voltage should not exceed 5.5 V.
PGOOD
(1)
9
8
P= Power, G = Ground, I = Input, O = Output
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
3
LM27402
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
www.ti.com
Pin Functions (continued)
PIN
NAME
HTSSOP
WQFN
I/O (1)
DESCRIPTION
Soft-start or tracking input. A start-up rate is defined with the use of an external softstart capacitor from SS/TRACK to GND. A +3-µA current source charges the soft-start
capacitor to set the output voltage rise time during start-up. SS/TRACK can also be
controlled with an external voltage source for tracking applications. SS/TRACK
voltage must not exceed the voltage on VDD.
SS/TRACK
3
1
I/O
SW
14
12
P
Power stage switch-node connection and return path for the high-side gate driver.
I
Frequency synchronization input. Apply an external clock signal to SYNC to set the
switching frequency. The SYNC frequency must be greater than the frequency set by
the FADJ pin. If the signal is not present, the switching frequency will decrease to the
frequency set by the FADJ resistor. SYNC must not exceed the voltage on VDD and
must be tied to GND if not used.
P
Internal sub-regulated 4.5-V bias supply. VDD is used to supply the voltage on
CBOOT to facilitate high-side MOSFET switching. Connect a 1-µF ceramic capacitor
from VDD to GND as close as possible to the LM27402. VDD cannot be connected to
a separate voltage rail. However, VDD can be connected to VIN to provide increased
gate drive only if VIN ≤ 5.5 V. Use A 1-Ω, 1-µF input filter for increased noise rejection.
SYNC
7
VDD
12
6
10
VIN
10
7
P
Input voltage supply rail with an operating range is 3 V to 20 V. This input is used to
provide the feedforward modulation for output voltage control and for generating the
internal bias supply voltage. Decouple VIN to GND locally with a 1-μF ceramic
capacitor. For better noise rejection, connect to the power stage input rail with an RC
filter.
EP
–
–
P
Exposed pad. Connect this pad to the PCB GND plane using multiple thermal vias.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
VIN, CS+, CS–, SW to GND
SW to GND less than 20ns Transients
MIN
MAX
UNIT
–0.3
22
V
–3
22
V
VDD, PGOOD to GND
–0.3
6
V
EN, SYNC, SS/TRACK, FADJ, COMP, FB, LG to GND
–0.3
VVDD
V
CBOOT to GND
–0.3
24
V
CBOOT to SW
V
–0.3
6
CS+ to CS–
–2
2
V
Operating Junction Temperature
–40
150
°C
260
°C
150
°C
Lead Temperature (Soldering, 10 sec)
Storage Temperature
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Unless otherwise specified, voltages are from the indicated pins to GND.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
(3)
4
Electrostatic discharge
(1) (2)
Charged-device model (CDM), per JEDEC specification JESD22C101 (3)
UNIT
±2000
±1000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor to each pin.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
LM27402
www.ti.com
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
6.3 Recommended Operating Conditions
MIN
MAX UNIT
VDD powered by internal LDO
3.0
20
VDD tied to VIN
3.0
5.5
2.2
5.5
V
SS/TRACK, SYNC, EN
0
VVDD
V
PGOOD
0
5.5
V
–40
125
°C
VIN (1)
VDD
Junction Temperature
(1)
V
VDD is the output of an internal linear regulator. Under normal operating conditions where VIN is greater than 5.5 V, VDD must not be
connected to any external voltage source. In an application where VIN is between 3.0 V and 5.5 V, connecting VIN to VDD maximizes
the bias supply rail voltage. In order to have better noise rejection under these conditions, a 1-Ω and 1-µF RC input filter to VDD may be
used.
6.4 Thermal Information
LM27402
THERMAL METRIC
(1)
RUM (WQFN)
PWP (HTSSOP)
16 PINS
16 PINS
UNIT
35.3 (2)
39.8 (2)
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
32.7
25.6
°C/W
RθJB
Junction-to-board thermal resistance
12.9
18.8
°C/W
ψJT
Junction-to-top characterization parameter
0.3
0.7
°C/W
ψJB
Junction-to-board characterization parameter
13.0
18.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.3
2.5
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Tested on a four layer JEDEC board. Four vias are provided under the WQFN exposed pad and nine vias are provided under the
HTSSOP exposed pad.
6.5 Electrical Characteristics
Unless otherwise stated, the following conditions apply: VVIN = 12 V. Limits in standard type are for TJ = 25°C only. Minimum
and maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C and are provided for reference purposes only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATIONAL SPECIFICATIONS
VFB = 0.6 V (not switching), TJ = 25°C
IQ
Quiescent Current
IQSD
Quiescent Current In Shutdown
4.5
VFB = 0.6 V (not switching), TJ = –40°C
to +125°C
6
VEN = 0 V, TJ = 25°C
25
VEN = 0 V, TJ = –40°C to +125°C
45
mA
µA
UVLO
VVIN Rising, VVDD Rising, TJ = 25°C
UVLO
Input Under Voltage Lockout
VVIN Rising, VVDD Rising, TJ = –40°C to
+125°C
UVLOHYS
UVLO Hysteresis
VVIN Falling, VVDD Falling
2.9
2.7
2.99
300
V
mV
REFERENCE
VFB
Feedback Voltage
IFB
Feedback Pin Bias Current
TJ = 25°C
TJ = –40°C to +125°C
VFB = 0.65 V
0.600
0.594
–50
0.606
0
50
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
V
nA
5
LM27402
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
www.ti.com
Electrical Characteristics (continued)
Unless otherwise stated, the following conditions apply: VVIN = 12 V. Limits in standard type are for TJ = 25°C only. Minimum
and maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C and are provided for reference purposes only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SWITCHING
RFADJ = 4.12 kΩ, TJ = 25°C
1150
RFADJ = 4.12 kΩ, TJ = –40°C to +125°C
FSW
Switching Frequency
950
RFADJ = 20 kΩ, TJ = 25°C
500
RFADJ = 4.12 kΩ, TJ = –40°C to +125°C
400
RFADJ = 95.3 kΩ, TJ = 25°C
Maximum Duty Cycle
0
600
214
RFADJ = 4.12 kΩ, TJ = –40°C to +125°C
DMAX
1350
175
FSW = 300 kHz, TJ = 25°C
265
kHz
kHz
kHz
95%
FSW = 300 kHz, TJ = –40°C to +125°C
93%
VDD SUB-REGULATOR
VDD
Sub-Regulator Output Voltage
IDD = 25 mA, TJ = 25°C
4.5
IDD = 25 mA, TJ = –40°C to +125°C
4
5
V
ERROR AMPLIFIER
BW–3dB
Open Loop Bandwidth
AVOL
Error Amp DC Gain
2
MHz
50
dB
VSLEW_RISE
Error Amplifier Rising Slew Rate
VSLEW_FALL
Error Amplifier Falling Slew Rate
VFB = 0.5 V
5
V/µs
VFB = 0.7 V
3
ISOURCE
COMP Source Current
VFB = 0.5 V
8
V/µs
12
mA
ISINK
COMP Sink Current
VFB = 0.7 V
4
VCOMP_MAX
Max COMP Voltage
VFB = 0.5 V
12
mA
3.1
VCOMP_MIN
Min COMP Voltage
VFB = 0.7 V
0.5
V
V
OVER CURRENT
VOFFSET
Comparator Voltage Offset
ICS–
Current Limit Offset Current
TJ = 25°C
0
TJ = –40°C to +125°C
–5
VCS– = 5 V, TJ = 25°C
5
10
VCS– = 5 V, TJ = –40°C to +125°C
9.5
10.5
mV
µA
GATE DRIVE
RDSON1
High-Side FET Driver pullup On
Resistance
VCBOOT – VSW = 4.7 V, IHG = +100 mA
RDSON2
High-Side FET Driver pulldown On
Resistance
VCBOOT – VSW = 4.7 V, IHG = –100 mA
RDSON3
Low-Side FET Driver pullup On
Resistance
VVDD = 4.7 V, ILG = +100 mA
RDSON4
Low-Side FET Driver pulldown On
Resistance
VVDD = 4.7 V, ILG = –100 mA
1.7
Ω
1.2
Ω
1.7
Ω
1
Ω
SOFT-START
ISS
Soft-Start Source Current
RSS_PD
Soft-Start pulldown Resistance
6
VSS/TRACK = 0 V, TJ = 25°C
3
VSS/TRACK = 0 V, TJ = –40°C to +125°C
VSS/TRACK = 0.6 V
Submit Documentation Feedback
2
4
288
µA
Ω
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
LM27402
www.ti.com
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
Electrical Characteristics (continued)
Unless otherwise stated, the following conditions apply: VVIN = 12 V. Limits in standard type are for TJ = 25°C only. Minimum
and maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely
parametric norm at TJ = 25°C and are provided for reference purposes only.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWERGOOD
VPGOOD = 0.2 V, VFB = 0.75 V, TJ = 25°C
IPGS
PGOOD Low Sink Current
VPGOOD = 0.2 V, VFB = 0.75 V, TJ =
–40°C to +125°C
IPGL
PGOOD Leakage Current
VPGOOD = 5 V
OVT
Overvoltage Threshold
OVT_HYS
OVT Hysteresis
UVT
Undervoltage Threshold
UVT_HYS
UVT Hysteresis
60
0
1
VFB Rising, TJ = 25°C
VFB Rising, TJ = –40°C to +125°C
µA
100
10
µA
117%
114%
120%
VFB Falling
2%
VFB Rising , TJ = 25°C
94%
VFB Rising, TJ = –40°C to +125°C
91%
97%
VFB Falling
3%
ENABLE
VEN Rising, TJ = 25°C
VEN
Enable Logic High Threshold
VEN_HYS
Enable Hysteresis
VEN Falling
IEN
Enable Pin pullup Current
VEN = 0 V
1.17
VEN Rising, TJ = –40°C to +125°C
1.10
V
1.24
100
mV
2
µA
FREQUENCY SYNCHRONIZATION
VLH_SYNC
SYNC Pin Logic High
VVDD = 4.7 V, TJ = –40°C to +125°C
VLL_SYNC
SYNC Pin Logic Low
VVDD = 4.7 V, TJ = –40°C to +125°C
SYNCFSW_L Minimum Clock Sync Frequency
TJ = –40°C to +125°C
SYNCFSW_H Maximum Clock Sync Frequency
TJ = –40°C to +125°C
2.0
V
0.8
V
200
kHz
1200
kHz
THERMAL SHUTDOWN
TSHD
Thermal Shutdown
Temperature Rising
165
°C
TSHD_HYS
Thermal Shutdown Hysteresis
Temperature Falling
15
°C
6.6 Timing Requirements
MIN
NOM
MAX
UNIT
SOFT-START
TSS_INT
Internal Soft-Start Time
1.28
ms
20
µs
POWERGOOD
TDEGLITCH
Deglitch Time
VPGOOD Rising and Falling
6.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SWITCHING
TOFF_MIN
Minimum Off Time
VFB = 0.5 V, TJ = 25°C
VFB = 0.5 V, TJ = –40°C to +125°C
165
125
5
205
ns
GATE DRIVE
TDT
Deadtime Timeout
FSW = 500 kHz
40
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
ns
7
LM27402
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
www.ti.com
6.8 Typical Performance Characteristics
Unless otherwise stated, all data sheet curves were recorded using Example Circuit 1. VIN = 12 V.
8
Figure 1. Efficiency (Vout = 1.5 V)
Figure 2. Efficiency (Vout = 5 V, Example Circuit 2)
Figure 3. Efficiency (Vout = 3.3 V, Example Circuit 2)
Figure 4. Load Regulation (Vout = 1.5 V)
Figure 5. Line Regulation (Vout = 1.5 V)
Figure 6. VDD Voltage vs Temperature (IVDD = 25 mA)
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
LM27402
www.ti.com
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
Typical Performance Characteristics (continued)
Unless otherwise stated, all data sheet curves were recorded using Example Circuit 1. VIN = 12 V.
Figure 7. Frequency vs Temperature (RFADJ = 20 kΩ)
Figure 8. Frequency vs RFADJ
Figure 9. CS– Current Source vs Temperature
Figure 10. Deadtime vs Temperature
Horizontal Scale: 100 µs/DIV
Figure 11. CS– Current Source Compliance Voltage
Figure 12. Load Transient
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
9
LM27402
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
www.ti.com
Typical Performance Characteristics (continued)
Unless otherwise stated, all data sheet curves were recorded using Example Circuit 1. VIN = 12 V.
Horizontal Scale: 2 ms/DIV
Figure 13. Start-up Waveforms
Horizontal Scale: 2 ms/DIV
Figure 14. Pre-Bias Start-up
Horizontal Scale: 2 ms/DIV
Figure 15. OCP Hiccup
Horizontal Scale: 400 ns/DIV
Figure 16. Frequency Synchronization
Horizontal Scale: 2 ms/DIV
Figure 17. Tracking
10
Figure 18. Shutdown Quiescent Current vs Temperature
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
LM27402
www.ti.com
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
Typical Performance Characteristics (continued)
Unless otherwise stated, all data sheet curves were recorded using Example Circuit 1. VIN = 12 V.
Figure 19. Quiescent Current vs Temperature
Figure 20. Feedback Voltage vs Temperature
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
11
LM27402
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
www.ti.com
7 Detailed Description
7.1 Overview
The LM27402 is a feature-rich, easy-to-use, single-phase, synchronous PWM DC/Dc step-down controller
capable of providing an ultrahigh current output for demanding POL applications. An input voltage range of 3 V to
20 V is compatible with a wide range of intermediate bus system rails and battery chemistries, especially 3.3-V,
5-V, and 12-V inputs. The output voltage is adjustable from 0.6 V to as high as 95% of the input voltage, with
better than ±1% feedback system regulation accuracy over the full junction temperature range. With an
adjustable inductor DCR based current limit setpoint, ferrite and composite cored inductors with low DCR and
small footprint can be specified to maximize efficiency and reduce power loss. High-current gate drivers with
adaptive deadtime are used for the high-side and low-side power MOSFETs to provide further efficiency gains.
The LM27402 employs a voltage-mode control loop with input voltage feedforward to accurately regulate the
output voltage over substantial load, line, and temperature ranges. The switching frequency is programmable
between 200 kHz and 1.2 MHz through a resistor or an external synchronization signal. The LM27402 is
available in thermally-enhanced WQFN-16 and HTSSOP-16 packages with 0.65-mm lead pitch. The device
offers high levels of integration by including MOSFET gate drivers, a low dropout (LDO) bias supply regulator,
and comprehensive fault protection features to enable highly flexible, reliable, energy-efficient, and high density
regulator solutions. Multiple fault conditions are accommodated, including overvoltage, undervoltage, overcurrent,
and overtemperature.
7.2 Functional Block Diagram
VIN
CBOOT
VIN
2.90 V
+
VIN UVLO
HG
2 μA
DRIVER, LEVEL SHIFTER
AND FAULT LOGIC
THERMAL
SHUTDOWN
EN
1.17 V
+
SW
ENABLE
-
VDD
VIN
4.5 V
VDD
LG
VDD
UVLO
+
+
SYNC
PLL AND VCO
GND
-
2.90 V
HICCUP LOGIC
CLOCK
PGOOD
VIN
FADJ
DIGITAL SOFTSTART
COUNTER
KFF = 0.143
RESET
PWM
SS
-
546 mV
+
-
RAMP
VDD
+
VIN
3 μA
SS/TRACK
0.6 V
REFERENCE
AND LOGIC
702 mV
+
-
OVP
OCP
-
+
-
10 μA
+
EA
UVP
546 mV
GND
12
FB
+
COMP
Submit Documentation Feedback
CS+
CS-
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
LM27402
www.ti.com
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
7.3 Feature Description
7.3.1 Wide Input Voltage Range
The LM27402 operating input voltage range is from 3 V to 20 V. The device is intended for POL conversions
from 3.3-V, 5-V, and 12-V unregulated, semiregulated and fully regulated supply rails. It is also suitable for
connection to intermediate bus converters with output rails centered at 12 V and 9.6 V (derived from 4:1 and 5:1
primary-secondary transformer step-downs in nonregulated full-bridge converter topologies) and voltage levels
intrinsic to a wide variety of battery chemistries.
The LM27402 uses an internal LDO subregulator to provide a 4.5-V bias rail for the gate drive and control circuits
(assuming the input voltage is higher than 4.5 V plus the necessary subregulator dropout specification).
Naturally, it can be more favorable to connect VDD directly to the input during low input voltage operation
(VVIN < 5.5 V). In summary, connecting VDD to VIN during low input voltage operation provides a greater gate
drive voltage level and thus an inherent efficiency benefit. However, by virtue of the low subregulator dropout
voltage, this VDD to VIN connection is not mandatory, thus enabling input ranges from 3 V up to 20 V.
In general, the subregulator is rated to drive the two internal gate driver stages in addition to the quiescent
current associated with the operation of the LM27402. VDD and VIN pins of the LM27402 can be tied together if
the input voltage is ensured not to exceed 5.5 V (absolute maximum 6 V). This connection bypasses the internal
LDO bias regulator and eliminates the LDO dropout voltage and power dissipation. An RC filter from the input rail
to the VIN pin, for example 2.2 Ω and 1 µF, presents supplementary filtering at the VIN pin. Low gate threshold
voltage MOSFETs are recommended for this configuration.
7.3.2 UVLO
An undervoltage lockout is built into the LM27402 that allows the device to only switch if the input voltage (VIN)
and the internal sub-regulated voltage (VDD) both exceed 2.9 V. A UVLO hysteresis of 300 mV on both VDD and
VIN prevents power-on and -off anomalies related to input voltage deviations.
7.3.3 Precision Enable
The EN pin of the LM27402 allows the output to be toggled on and off and is a precision analog input. When the
EN voltage exceeds 1.17 V, the controller initiates the soft-start sequence as long as the input voltage and subregulated voltage have exceeded their UVLO thresholds of 2.9 V. The EN pin has an absolute maximum voltage
rating of 6.0 V and should not exceed the voltage on VDD. There is an internal 2 µA pullup current source
connected to the EN pin. If EN is open, the LM27402 turns on automatically if VIN and VDD exceed 2.9 V. If the
EN voltage is held below 0.8 V, the LM27402 enters a deep shutdown state where the internal bias circuitry is
off. The quiescent current is approximately 35 µA in deep shutdown. The EN pin has 100 mV of hysteresis to
reject noise and allow the pin to be resistively coupled to the input voltage or sequenced with other rails.
7.3.4 Soft-Start and Voltage Tracking
When the EN pin exceeds 1.17 V and both VIN and VDD exceed their UVLO thresholds, the LM27402 begins
charging the output linearly to the voltage level dictated by the feedback resistor network. The soft-start time is
set by connecting a capacitor from SS/TRACK to GND. After EN exceeds 1.17 V, an internal 3-µA current source
begins to linearly charge the soft-start capacitor. Soft-start allows the user to limit inrush currents related to high
output capacitance and output slew rate. If a soft-start capacitor is not used, the LM27402 defaults to a digitallycontrolled star-tup time of 1.28 ms. The SS/TRACK pin can also be used to ratiometrically or coincidentally track
an external voltage source. See the Setting the Soft-Start Time and Tracking sections for more information.
7.3.5 Output Voltage Setpoint and Accuracy
The reference voltage seen at the FB pin is set at 0.6 V, and a feedback system accuracy of ±1% over the full
junction temperature range is met. Junction temperature range for the LM27402 is –40°C to +125°C. While
somewhat dependent on frequency and load current levels, the LM27402 is generally capable of providing output
voltages in the range of 0.6 V to a maximum of greater than 90% VIN. The dc output voltage during normal
operation is set by the feedback resistor network connected to VOUT.
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
13
LM27402
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
www.ti.com
Feature Description (continued)
7.3.6 Voltage-Mode Control
The LM27402 incorporates a voltage-mode control loop implementation with input voltage feedforward to
eliminate the input voltage dependence of the PWM modulator gain. This configuration allows the controller to
maintain stability throughout the entire input voltage operating range and provides for optimal response to input
voltage transient disturbances. The constant gain provided by the controller greatly simplifies feedback loop
design because loop characteristics remain constant as the input voltage changes, unlike a buck converter
without voltage feedforward. An increase in input voltage is matched by a concomitant increase in ramp voltage
amplitude to maintain constant modulator gain. The input voltage feedforward gain, kFF, is 1/7, equivalent to the
ramp amplitude divided by the input voltage, VRAMP/VIN. See the Control Loop Compensation section for more
detail.
7.3.7 Power Good
CURRENT LIMIT LEVEL (ILIMIT)
IL
Soft-Start Time
VSS/TRACK
0.6 V
VOVT
VOVTHYS
VFB (0.6 V)
VUVTHYS
VUVT
0.0 V
VENABLE
TPGOOD (20 Ps)
VPGOOD
HIGH GATE
CUTOFF
VSW
OVP
UVP
DISABLE
PRE-BIASED
STARTUP CONDITION
CURRENT LIMIT
HICCUP
(1.28 ms)
Figure 21. Power Good Behavior
The PGOOD flag of the LM27402 is used to signal when the output is out of regulation or during nonregulated
pre-biased conditions. This means that current limit, UVLO, overvoltage threshold, undervoltage threshold, or a
non-regulated output will cause the PGOOD pin to pull low. To prevent glitches to PGOOD, a 20-μs deglitch filter
is built into the LM27402. Figure 21 illustrates when the PGOOD flag is asserted low.
7.3.8 Inductor-DCR-Based Overcurrent Protection
The LM27402 exploits the filter inductor DCR (DC resistance) to detect overcurrent events. This technique
enables lossless and continuous monitoring of the output current using an RC sense network in parallel with the
inductor. DCR current sensing allows the system designer to use inductors specified with tight tolerance DCRs to
improve the current limit setpoint accuracy. A DC current limit setpoint accuracy within the range of 10% to 20%
is achieved using inductors with low DCR tolerances.
14
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
LM27402
www.ti.com
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
Feature Description (continued)
7.3.9 Current Sensing
As mentioned, the LM27402 implements a lossless inductor DCR lossless current sense scheme designed to
provide both accurate overload (current limit) and short-circuit protection. Figure 22 shows the popular inductor
DCR current sense method. Figure 23 shows an implementation with current shunt resistor, RISNS.
Components RS and CS in Figure 22 create a low-pass filter across the inductor to enable differential sensing of
the inductor DCR voltage drop. When RSCS is equal to L/RDCR, the voltage developed across the sense
capacitor, CS, is a replica of the voltage waveform of the inductor DCR. Choose the capacitance of CS greater
than 0.1 µF to maintain low impedance of the sense network, thus reducing the susceptibility of noise pickup
from the switch node.
VIN
VIN
&6Å
CS+
CS
RS
L
RDCR
&6Å
CS+
L
VOUT
RISNS
VOUT
To Load
To Load
GND
GND
Figure 22. Current Sensing Using Inductor DCR
Figure 23. Current Sensing Using Shunt Resistor
Note that the inductor DCR is shown schematically as a discrete element in Figure 22. With power inductors
selected to provide lowest possible DCR to minimize power losses, the typical DCR ranges from 0.4 mΩ to
4 mΩ. Then, given a load current of 25 A, the voltage presented across the CS+ and CS– pins ranges between
10 mV and 100 mV.
A current sense (or current shunt) resistor in series with the inductor can also be implemented at lower output
current levels to provide accurate overcurrent protection, see Figure 23. Burdened by the unavoidable efficiency
penalty and/or additional cost implications, this configuration is not usually implemented in high-current
applications (except where OCP setpoint accuracy and stability over the operating temperature range are critical
specifications).
7.3.10 Power MOSFET Gate Drivers
The LM27402 gate driver impedances are low enough to perform effectively in high output current applications
where large die-size or paralleled MOSFETs with correspondingly large gate charge, QG, are used. Measured at
VVDD = 4.7 V, the LM27402's low-side driver has a low impedance pulldown path of 1 Ω to minimize the effect of
dv/dt induced turn-on, particularly with low gate-threshold voltage MOSFETs. Similarly, the high-side driver has
1.7-Ω and 1.2-Ω pull-up and pulldown impedances, respectively, for faster switching transition times, lower
switching loss, and greater efficiency.
Furthermore, there is a proprietary adaptive deadtime control on both switching edges to prevent shoot-through
and cross-conduction, minimize body diode conduction time, and reduce body diode reverse recovery related
losses. The LM27402 is fully compatible with discrete NexFET™ Power Block MOSFETs from TI.
7.3.11 Pre-Bias Start-up
In certain applications, the output may acquire a pre-bias voltage before the LM27402 is powered on or enabled.
Pre-biased conditions are managed by preventing switching until the soft-start (SS/TRACK) voltage exceeds the
feedback (FB) voltage. When VSS/TRACK exceeds VFB, the LM27402 begins to switch synchronously and regulate
the output voltage.
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
15
LM27402
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
www.ti.com
No Switching
Switching
Voltage
94% VOUT
VOUT
Pre-bias Level
VSS/TRK
0V
Enable Delay
Soft-Start exceeds
feedback voltage
VEN
VPGOOD
Time
Soft-Start Time (tss)
Figure 24. Pre-Bias Start-up
Prohibiting switching during a pre-biased start-up condition prevents the output from forcing parasitic paths in the
system application to conduct excessive current. The LM27402 does not switch if the output is pre-biased to a
voltage higher than the nominally-set output voltage.
7.4 Device Functional Modes
7.4.1 Fault Conditions
Overcurrent, overtemperature, output undervoltage, and overvoltage protection features are included in the
LM27402.
7.4.1.1 Thermal Protection
Internal thermal shutdown is provided to protect the controller in the event that the maximum junction
temperature of approximately 165°C has been exceeded. Both the high-side and low-side power MOSFETs are
turned off during this condition. During a thermal fault condition, PGOOD is held at logic zero.
7.4.1.2 Current Limit
The LM27402 may enter two states when a current limit event is detected. If a current limit condition has
occurred, the high-side power MOSFET is immediately turned off until the next switching cycle. This is
considered the first current limit state and provides an immediate response to any current limit event. During the
first state, an internal counter begins to record the number of overcurrent events. The counter is reset if 32
consecutive switching cycles occur with no current limit events detected. If five overcurrent events are detected
within 32 switching cycles, the LM27402 then enters into a hiccup mode state. During hiccup mode, the LM27402
enters shutdown for 1.28 ms and then attempt to restart again. When transitioning into hiccup mode, the highside MOSFET is turned off and the low-side MOSFET is turned on. As the inductor current reaches zero
subsequent to the overcurrent event, the low-side MOSFET is turned off and the switch-node becomes high
impedance to prepare for the next start-up sequence. The soft-start capacitor is discharged through an internal
pulldown FET to reinitialize the start-up sequence. To illustrate how the LM27402 behaves during current limit
faults, an overcurrent scenario is illustrated in Figure 25.
16
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
LM27402
www.ti.com
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
Device Functional Modes (continued)
Soft-Start
High Gate
Off
1
2
High Gate
Off
Controller
begins to
count to 32
3
Low
5
Gate On
4
...
OCP Level
High Gate
and Low
Gate Off
L Current
1
Switch
Node
Voltage
2
...
22
23
Soft-Start
Discharge
0V
24
0A
No Over-Current Events
Detected
HICCUP (1.28 ms)
Figure 25. Current Limit Timing Diagram
In the example shown in Figure 25, the LM27402 immediately turns off the high-side MOSFET when an
overcurrent event is detected. After the third overcurrent event is detected, 24 switching cycles occur before the
fourth overcurrent pulse is detected. Because the current limit logic does not count 32 switching cycles between
two overcurrent events, the internal current limit counter is not reset and continues counting until the LM27402
enters hiccup mode. The soft-start capacitor is then discharged to initialize start-up and a wait period of 1.28 ms
occurs.
7.4.1.3 Negative Current Limit
To prevent excess negative current, the LM27402 implements a negative current limit through the low-side
MOSFET. Negative current limit is only enabled when an output overvoltage event is detected. Should such an
overvoltage fault occur, the low-side MOSFET turns off if the SW voltage exceeds a positive 100 mV during the
low-side MOSFET conduction time, thereby protecting the power stage from excessive negative current.
7.4.1.4 Undervoltage Threshold (UVT)
The FB pin is also monitored for an output voltage excursion below the nominal level. However, if the UVT
comparator is tripped, no action occurs on the normal switching cycles. The UVT signal is used solely as a valid
condition for the Power Good flag to transition low. When the FB voltage exceeds 94% of the reference voltage,
the Power Good flag transitions high. Conversely, the Power Good flag transitions low when the FB voltage is
less than 91% of the reference.
7.4.1.5 Overvoltage Threshold (OVT)
When the FB voltage exceeds 117% of the reference voltage, the Power Good flag transitions low after a 20-µs
deglitch. The control loop attempts to bring the output voltage back to the nominal setpoint. Conversely, when the
FB voltage goes below 115% of the reference, the Power Good flag is allowed to transition high. Negative
current-limit detection is activated when the regulator is in an OV condition. See the Negative Current Limit
section for more details.
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
17
LM27402
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
www.ti.com
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers must
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Converter Design
As with any DC/Dc converter, numerous tradeoffs are required to optimize the design for efficiency, size, or
performance. Such tradeoffs are highlighted throughout the following discussion. To facilitate component
selection, the circuit shown in Figure 26 may be used as a reference. Unless otherwise indicated, all formulae
assume units of Amps (A) for current, Farads (F) for capacitance, Henries (H) for inductance and Volts (V) for
voltage.
Figure 26 shows RF and CF acting as an RC filter to the VIN pin of the LM27402. The filter is used to attenuate
voltage ripple that may exist on the input rail particularly during high output currents. The recommended values of
RF and CF are 2.2 Ω and 1 µF, respectively. There is a practical limit to the size of RF as it can cause a large
voltage drop if large operating bias currents are present. The VIN pin of the LM27402 must not exceed 150 mV
difference from the input voltage rail (VIN).
Equation 1 is used to calculate for any buck converter is duty ratio:
D=
VOUT 1
x
VIN
(1)
Due to the resistive powertrain losses, the duty ratio will increase based on the overall efficiency, η. Calculation
of η can be found in the Power Loss and Efficiency Calculations section of this data sheet.
VIN
CBOOT
CF
CIN
RF
QH
VIN
CBOOT
HG
VDD
SW
L
DBOOT
RPGOOD
LM27402
CVDD
QL
RS
VOUT
CS
COUT
LG
PGOOD
CS+
EN
CSBY
SYNC
SS/TRACK
CSS
CC3
RFB1
FB
FADJ
GND COMP
RFADJ
RSET
CSCC1
RC2
RC1
CC2
RFB2
Figure 26. Typical Application Circuit
18
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
LM27402
www.ti.com
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
Application Information (continued)
8.1.2 Inductor Selection (L)
The inductor value is determined based on the operating frequency, load current, ripple current, and duty ratio.
The selected inductor must have a saturation current rating greater than the peak current limit of the LM27402.
To optimize the performance, the inductance is typically selected such that the ripple current, ΔIL, is between
20% and 40% of the rated output current. Figure 27 illustrates the switch voltage and inductor ripple current
waveforms. Once the nominal input voltage, output voltage, operating frequency, and desired ripple current are
known, the minimum inductance value can be calculated by Equation 2:
LMIN =
(VIN - VOUT) x D
'IL x fSW
(2)
VSW
VIN
Time
IL
IL (AVG) = IOUT
∆IL
Time
Figure 27. Switch Voltage and Inductor Current Waveforms
The peak inductor current at maximum load, IOUT + ΔIL / 2, should be kept adequately below the peak current
limit setpoint of the device.
8.1.3 Output Capacitor Selection (COUT)
The output capacitor, COUT, filters the inductor ripple current and provides a source of charge for transient load
events. A wide range of output capacitors may be used with the LM27402 that provide excellent performance,
including ceramic, tantalum, or electrolytic type chemistries. Typically, ceramic capacitors provide extremely low
ESR to reduce the output ripple voltage and noise spikes, while tantalum and electrolytic capacitors provide a
large bulk capacitance in a small size for transient loading events. When selecting the output capacitance, the
two performance characteristics to consider are output voltage ripple and transient response. The output voltage
ripple is approximated by Equation 3:
'VOUT = 'IL x RESR2 +
1
2
8 x fSW x COUT
(3)
where ΔVOUT is the amount of peak-to-peak voltage ripple at the power supply output, RESR is the equivalent
series resistance of the output capacitor, fSW is the switching frequency, and COUT is the output capacitance used
in the design. The tolerable output ripple amplitude is application specific; however a general recommendation is
to keep the output ripple less than 1% of the rated output voltage. Note that ceramic capacitors are sometimes
preferred because they have very low ESR; however, depending on package and voltage rating of the capacitor,
the effective in-circuit capacitance can drop significantly with applied voltage and operating temperature.
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
19
LM27402
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
www.ti.com
Application Information (continued)
The output capacitor also affects the output voltage deviation during a load current transient. The peak output
voltage deviation is dependent on many factors such as output capacitance, output capacitor ESR, filter
inductance, control loop bandwidth, powertrain parasitics, and so on. Given sufficient control loop bandwidth, a
good approximation of the output voltage deviation is seen in Equation 4:
2
'VTR =
2
L x 'IO
RESR x COUT x VL
+
2 x COUT x VL
2xL
(4)
ΔVTR is the transient output voltage deviation, ΔIOUT is the load current step change and L is the filter inductance.
VL is the minimum inductor voltage, which is duty ratio dependent.
VL = VOUT , if D ≤ 0.5,
VL = VIN - VOUT , if D > 0.5
For a desired ΔVTR, a minimum output capacitance is found by Equation 5:
2
COUT t
L x 'IOUT
'VTR x VL
1
x
1+ 1-
RESR x 'IOUT
'VTR
2
(5)
8.1.4 Input Capacitor Selection (CIN)
Input capacitors are necessary to limit the input ripple voltage while supplying much of the switch current during
the high-side MOSFET on-time. It is generally recommended to use ceramic capacitors at the input as they
provide both a low impedance and a high RMS current rating. It is important to choose a stable dielectric for the
ceramic capacitor such as X5R or X7R. A quality dielectric provides better temperature performance and also
avoids the DC voltage derating inherent with Y5V capacitors. Place the input capacitor as close as possible to
the drain of the high-side MOSFET and the source of the low-side MOSFET. Non-ceramic input capacitors must
be selected for RMS current rating, minimum ripple voltage, and to provide damping. A good approximation for
the required ripple current rating is given by the relationship of Equation 6:
ICIN_RMS | IOUT x D x 1- D
(6)
The highest requirement for RMS current rating occurs for D = 0.5. When D = 0.5, the RMS ripple current rating
of the input capacitor must be greater than half the output current. Low ESR ceramic capacitors can be placed in
parallel with higher valued bulk capacitors to provide optimized input filtering for the regulator. The input voltage
ripple is calculated using Equation 7:
'VIN =
IOUT x D x (1 ± D)
+
CIN x fSW
IOUT +
'IL
x RESR_CIN
2
(7)
The minimum amount of input capacitance as a function of desired input voltage ripple is estimated using
Equation 8:
CIN t
IOUT x D x (1 ± D)
'IL
'VIN ± IOUT +
x RESR_CIN x fSW
2
(8)
8.1.5 Using Precision Enable
If enable (EN) is not controlled directly, the LM27402 can be pre-programmed to turn on at an input voltage
higher than the UVLO voltage. This is done with an external resistor divider from VIN to EN and EN to GND as
shown in Figure 28.
20
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
LM27402
www.ti.com
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
Application Information (continued)
Input Power
Supply
RA
VIN
LM27402
EN
RB
GND
Figure 28. Enable Sequencing
The resistor values of RA and RB are relatively sized to allow the EN pin to reach the precision enable threshold
voltage at the appropriate input supply voltage. With the enable current source considered, the equation to solve
for RA is Equation 9:
RB VIN - 1.17V
RA =
1.17V - IEN x RB
(9)
where RA is the resistor from VIN to EN, RB is the resistor from EN to GND, IEN is the internal enable pull-up
current (2 µA) and 1.17 V is the fixed precision enable threshold voltage. Typical values for RB range from 10 kΩ
to 100 kΩ.
8.1.6 Setting the Soft-Start Time
Adding a soft-start capacitor reduces inrush currents and provides a monotonic start-up. The soft-start
capacitance is calculated by Equation 10:
tSS X ISS
CSS =
0.6V
(10)
As shown, the CSS capacitance is set by the desired soft-start time tss, the soft-start current Iss (3 µA) and the
nominal feedback (FB) voltage level of 0.6 V. If VVIN and VVDD are above their UVLO voltage levels (2.9 V) and
EN is above the precision enable threshold (1.17 V), the soft-start sequence begins. The LM27402 defaults to a
minimum start-up time of 1.28 ms when a soft-start capacitor is not connected. In other words, the LM27402 will
not start-up faster than 1.28 ms. The soft-start capacitor is discharged when enable is cycled, during UVLO,
OTP, or when the LM27402 enters hiccup mode from an overcurrent event.
There is a delay between EN transitioning above 1.17 V and the beginning of the soft-start sequence. The delay
allows the LM27402 to initialize its internal circuitry. Once the output has charged to 94% of the nominal output
voltage and SS/TRACK has exceeded 564 mV, the PGOOD indicator transitions high as illustrated in Figure 29.
Voltage
94% VOUT
VOUT
Enable
Delay
0V
VEN
VPGOOD
Soft-Start Time (tss)
Time
Figure 29. Soft-Start Timing
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
21
LM27402
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
www.ti.com
Application Information (continued)
8.1.7 Tracking
The SS/TRACK pin also functions as a tracking pin when external power supply tracking is needed. Tracking is
achieved by simply dividing down the external supply voltage with a simple resistor network shown in Figure 30.
With the correct resistor divider configuration, the LM27402 can track an external voltage source to obtain a
coincident or ratiometric start-up behavior.
External
Power Supply
VOUT1
LM27402
R1
VOUT2
SS/TRACK
R2
Figure 30. Tracking an External Power Supply
Because the soft-start charging current ISS is sourced from the SS/TRACK pin, the size of R2 must be less than
10 kΩ to minimize errors in the tracking output. Once a value for R2 is selected, calculate the value for R1 using
the appropriate equation in Figure 31 to give the desired start-up sequence. Figure 31 shows two common startup sequences; the upper waveform shows a coincidental start-up while the lower waveform illustrates a
ratiometric start-up. A coincidental configuration provides a robust start-up sequence for certain applications
because it avoids turning on any parasitic conduction paths that may exist between loads. A ratiometric
configuration is preferred in applications where both supplies need to be at the final steady-state voltage at the
same time.
COINCIDENTAL STARTUP
VOLTAGE
VOUT1
VOUT2
æV
ö
R1 = ç OUT2 - 1÷ ´ R2
è 0.6V
ø
VEN
VOUT2 < 0.6 x VOUT1
TIME
RATIOMETRIC STARTUP
VOUT1
VOLTAGE
VOUT2
R1 = (VOUT1 - 0.8) x R 2
VEN
TIME
Figure 31. Tracking Start-up Sequences
Similar to the soft-start function, the fastest possible startup time is 1.28 ms regardless of the rise time of the
tracking voltage. When using the track feature, the final voltage seen by the SS/TRACK pin should exceed 0.8 V
to provide sufficient overdrive and transient immunity.
22
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
LM27402
www.ti.com
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
Application Information (continued)
8.1.8 Setting the Switching Frequency
There are two options for setting the switching frequency of the LM27402. The frequency is adjusted by an
external resistor from FADJ to GND, or the user can synchronize the LM27402 to an external clock signal using
SYNC. The LM27402 only synchronizes to frequencies above the frequency set by the RFADJ resistor. The clock
signal must range from less than 0.8 V to greater than 2.0 V to ensure proper operation. If the clock signal
ceases, the switching frequency reduces to the free-running frequency set by the FADJ resistor. The frequency
range is 200 kHz to 1.2 MHz. The sync-in clock can synchronize at a maximum of 400 kHz above the frequency
set by the resistor. To find the resistance needed for a given frequency, use the following equation: (fSW (kHz),
RFADJ (kΩ))
100 5
RFADJ =
fSW
-1
100
(11)
8.1.9 Setting the Current Limit Threshold
As mentioned in the Current Sensing section, the LM27402 exploits the filter inductor DCR to detect overcurrent
events. If desired, the user can employ inductors with low tolerance DCR to increase the accuracy of the current
limit threshold. The most common circuit arrangement for sensing the inductor DCR voltage is shown in
Figure 32.
L
Rs
IL
Cs
-
+
VDCR
Figure 32. Inductor DCR Current Sensing Circuit
The most accurate sensing of the differential voltage across the inductor DCR is achieved by matching the time
constant of the RSCS sense filter with the inductor's L/RDCR time constant. If the time constants are matched, the
voltage across the capacitor follows the voltage across the DCR. A typical range of capacitance used in the
RSCS network is 100 nF to 1µF. The equation to match the time constants is:
L
RSCS =
RDCR
(12)
Adjust the current limit threshold to any level with a single resistor from the current limit comparator to the output
voltage pin. Use the circuit in Figure 33 to set the current limit.
L
LM27402
SW
Rs
IL
Cs
+ VDCR CS+
CSBY
RSET
CS-
+ VSET -
Figure 33. Adjusting the Current Limit Setpoint
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
23
LM27402
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
www.ti.com
Application Information (continued)
Because the voltage across the inductor DCR follows the current through the inductor, the device trips at the
peak of the inductor current. Capacitor CSBY shown in Figure 33 filters the input to the current sense comparator.
A working range for this capacitance is 47 pF to 100 pF. The equation to set the resistor value of RSET is:
RSET =
ILIMIT RDCR
Ics-
(13)
ILIMIT is the desired current limit level, RDCR is the rated DC resistance of the inductor and Ics- is the 10 µA current
source flowing out of the CS– pin. To aid in high frequency common-mode rejection, a series resistor, RCS, of
same resistance as RSET, is optionally added to the CS+ signal path.
The internal current source ICS- is powered from the input voltage rail, VIN. The minimum voltage required to drive
that current source is 1 V from VIN to VOUT. If a low-dropout condition occurs where VIN – VOUT < 1 V, the
LM27402 may prematurely initiate hiccup mode. There are multiple options to avoid this situation. The first option
is to enable the LM27402 after the input voltage has risen 1 V above the nominal output voltage as seen in
Figure 28. The second option is to lower the comparator common-mode voltage shown in Figure 34 such that the
ICS- current source has enough headroom voltage.
L
LM27402
SW
RS
IL
CS
RS1
RSET
RS2
RS3
CS+
CS-
Figure 34. Common Mode Voltage Resistor Divider Network
Refer to AN-2060 LM27402 Current Limit Application Circuits (SNVA441) for design guidelines to adjust the
common-mode voltage of the current sense comparator.
8.1.10 Control Loop Compensation
The LM27402 voltage mode control system incorporates input voltage feedforward to eliminate the input voltage
dependence of the PWM modulator gain. Input voltage feedforward is essential for stability across the entire
input voltage range and makes it easier for the designer to select the compensation and power train components.
The following describes how to set the output voltage and obtain the open-loop transfer function.
During steady state operation, the DC output voltage is set by the feedback resistor network between VOUT, FB
and GND. The FB voltage is nominally 0.6 V ±1%. The equation describing the output voltage is:
RFB1 + RFB2
0.6V
VOUT =
RFB2
(14)
A good starting value for RFB1 is 20 kΩ. If an output voltage of 0.6 V is required, RFB2 must not be used.
There are three main blocks of a voltage-mode buck switcher that the power supply designer needs to consider
when designing the control system: power train, PWM modulator, and compensator. A diagram representing the
control loop is shown in Figure 35.
24
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
LM27402
www.ti.com
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
Application Information (continued)
Powertrain
PWM Modulator
VIN
L
RDCR
DRIVER
VOUT
SW
RESR
RO
COUT
+
PWM
Compensator
+
-
COMP
EA
CC1
0.6 V
FB
RFB1
RC1
RC2
RFB2
CC3
CC2
Figure 35. Control Loop Schematic Diagram
The power train consists of the filter inductor (L) with DCR (RDCR), output capacitor (COUT) with ESR (effective
series resistance RESR), and effective load resistance (RO). The error amplifier (EA) regulates the feedback (FB)
voltage to 0.6V. The passive compensation components around the error amplifier establish system stability.
Type-III compensation is shown in Figure 35. The PWM modulator establishes the duty cycle command by
comparing the error amplifier output (COMP) with an internally generated ramp set at the switching frequency.
The modulator gain, power train and compensator transfer functions must be taken into consideration when
obtaining the total open-loop transfer function. The PWM modulator adds a DC gain component to the open-loop
transfer function. In a basic voltage-mode system, the PWM gain varies with input voltage. However the
LM27402 internal voltage feedforward circuitry maintains a constant PWM gain of 7:
1
=7
GPWM =
kFF
(15)
The power train transfer function includes the filter inductor and its DCR, output capacitor with ESR, and load
resistance. The inductor and capacitor create two complex poles at a frequency described by:
fLC =
RO + RDCR
1
2S LCOUT(RO + RESR)
(16)
A left half plane zero is created by the output capacitor ESR located at a frequency described by:
fESR =
1
2SCOUTRESR
(17)
The complete power train transfer function is:
s
1+
2SfESR
GP(s) =
s
s 2
1+
+
QO2SfLC
2SfLC
(18)
Figure 36 shows the bode plot of the above transfer function.
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
25
LM27402
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
www.ti.com
Application Information (continued)
Figure 36. Powertrain Bode Plot
The complex poles (fLC) created by the filter inductor and output capacitor cause a 180° phase shift as seen in
Figure 36. The phase is boosted back up to -90° by virtue of the output capacitor ESR zero. The phase shift
caused by the complex poles must be compensated to stabilize the loop response. The compensation network
shown around the error amplifier in Figure 35 creates two poles, two zeros and a pole at the origin. Placing these
poles and zeros at the correct frequencies optimizes the loop response. The compensator transfer function is:
2SfZ1
s
+1
2SfZ2 +1
s
GEA(s) = Km
s
s
+1
+1
2SfP1
2SfP2
(19)
The pole located at the origin provides high DC gain to maximize DC load regulation performance. The other two
poles and two zeros are strategically located to stabilize the voltage-mode loop depending on the power stage
complex poles and damping characteristic, Q. Figure 37 illustrates a typical compensation transfer function.
40
20
30
0
-20
fP2
X
X
10
-40
PHASE (°)
GAIN (dB)
fP1
20
OO
fZ1
0
100
1,000
fZ2
10,000
-60
100,000 1,000,000
FREQUENCY (Hz)
Figure 37. Type-lll Compensation Network Bode Plot
Km is the mid-band gain of the compensator and is estimated by:
Km =
26
fC kFF
fLC
(20)
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
LM27402
www.ti.com
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
Application Information (continued)
fC is the desired crossover frequency and is normally selected between one tenth and one fifth of the switching
frequency, fSW. The next set of equations show pole and zero locations expressed in terms of the components in
the compensator feedback loop.
1
1
fZ2 =
fZ1 =
2SRC1CC1
2S(RC2 + RFB1 )CC3
1
fP1 = 2SR C
C2 C3
fP2 =
RC1
CC1 + CC2
K =
2SRC1 CC1CC2 m RFB1
(21)
Depending on Q, the complex double pole causes an increase in gain at the LC resonant frequency and a
precipitous drop in phase. To compensate for the phase drop, it is common practice to place both compensator
zeros created by the Type-III compensation network at or slightly below the LC double pole frequency. The other
two poles are located beyond this point. One pole is located at the zero caused by the output capacitor ESR and
the other pole is placed at half the switching frequency to roll off the higher frequency response.
fZ1 = fZ2 = fLC
fP1 = fESR
fSW
fP2 =
2
(22)
Conservative values for the compensation components are found by using the following equations.
RC1 = RFB1Km
CC1 =
1
2SfLCRC1
RC2 =
RFB1 fLC
fESR-fLC
CC3 =
1
2SfESRRC2
CC2 =
CC1
SfSWRC1 CC1-1
(23)
100
140
75
100
50
60
25
20
fC
0
-25
100
-20
1,000
10,000
PHASE MARGIN (°)
GAIN (dB)
Once the compensation components are fixed, create a Bode plot of the loop response using all three transfer
functions. Figure 38 provides an illustration of the loop response.
-60
100,000 1,000,000
FREQUENCY (Hz)
Figure 38. Loop Response
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
27
LM27402
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
www.ti.com
Application Information (continued)
It is important to always verify the stability by either observing the load transient response or by using a network
analyzer. A phase margin between 45° and 70° is usually desired for voltage-mode controlled systems.
Excessive phase margin causes slow system response to load transients whereas low phase margin is indicated
by an oscillatory load transient response. If the peak voltage deviation is larger than desired, increase fC and
recalculate the compensation components. If this amounts to a reduction in phase margin, the remaining option
is to increase output capacitance.
8.1.11 MOSFET Gate Drivers
To drive large power MOSFETs with high gate charge, the LM27402 includes low impedance high-side and lowside gate drivers that source and sink high current for fast transition times and increased efficiency. The highside gate driver is powered from a bootstrap circuit, whereas the low-side driver is powered by the VDD rail as
shown in Figure 39.
LM27402
VDD
CBOOT
DBOOT
CBOOT
VIN
HG
+
SW
VOUT
LOGIC
VDD
+
LG
Figure 39. High-Side and Low-Side MOSFET Gate Drivers
The circuit in Figure 39 effectively supplies close to the VDD voltage (4.5 V) between the gate and the source of
the high-side MOSFET during the on time. Use a Schottky diode for DBOOT with sufficient reverse voltage rating
and continuous current rating. The average current through the boot diode depends on the gate charge of the
high-side MOSFET and the switching frequency. It is calculated using Equation 24.
IDBOOT = fSWQGHS
(24)
IDBOOT is the average current through the DBOOT diode, fSW is the switching frequency and QGHS is the gate
charge of the high-side MOSFET. If the input voltage is below 5.5 V, it is recommended to connect VDD to the
input supply of the LM27402 through a 1-Ω resistor as shown in Figure 40. This increases the gate voltage
amplitude of both the low-side and high-side MOSFETs, thus reducing RDS(on).
28
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
LM27402
www.ti.com
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
Application Information (continued)
1Ω
DBOOT
VIN
CBOOT
CIN
CBOOT
HG
QH
L
VDD
LM27402
CVDD
SW
VOUT
COUT
LG
QL
Figure 40. Tie VDD to VIN when VIN ≤ 5.5V
8.1.12 Power Loss and Efficiency Calculations
The overall efficiency of a buck regulator is simply the ratio of output power to input power. Although power
losses are found in almost every component of a buck regulator, the following sections present equations
detailing components with the highest relative power loss.
8.1.12.1 Power MOSFETs
Selecting the correct power MOSFET for a design is important to the overall operation of the circuit. If
inappropriate MOSFETs are selected for the application, it may result in poor efficiency, high temperature issues,
shoot-through and other impairments. It is important to calculate the power dissipation for each MOSFET at the
maximum output current and ensure that the maximum allowable power dissipation is not exceeded. MOSFET
data sheets must also specify a junction-to-ambient thermal resistance (θJA), and the temperature rise is
estimated from this specification.
Both high-side and low-side MOSFETs contribute significant loss to the system relative to the other components.
The high-side MOSFET contributes transition switching loss, conduction loss and gate charge loss. The low-side
MOSFET also contributes conduction and gate charge loss, and the body diode of the MOSFET causes
deadtime conduction loss and reverse recovery loss that must also be considered. The transition losses for the
low-side MOSFET are insignificant and usually ignored.
8.1.12.2 High-Side Power MOSFET
The next set of equations are used to calculate the losses associated with the high-side MOSFET.
2
PCND_HS IOUT x RDS(ON)_HS x D x 1.3
PSW_HS =
VIN x IOUT x fSW x (tr+tf)
2
PTOT_HS = PCND_HS + PSW_HS
(25)
PCND_HS is the conduction loss of the high-side MOSFET during the D interval. this equation includes a self
heating coefficient of 1.3 to approximate the effects of the RDS(on) temperature coefficient. RDS(ON)_HS is the drain
to source resistance, IOUT is the output current and D is the duty ratio. PSW_HS is the switching power loss during
the high-side MOSFET transition time. VIN is the input voltage, fSW is the switching frequency, and tr and tf are
the rise and fall times of the switch-node voltage, respectively. PTOT_HS is the total power dissipation of the highside MOSFET.
The gate charge of the high-side MOSFET greatly affects the turn-on transition time, and therefore efficiency.
Furthermore, consider the ratio of switching loss to conduction loss associated with the high-side MOSFET. If the
duty ratio is small and the input voltage is high, it is beneficial to tradeoff QG for higher RDS(on) to avoid high
switching losses relative to conduction losses. If the duty ratio is large and the input voltage is low, then a lower
RDS(on) MOSFET in tandem with a higher QG may result in less power dissipation.
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
29
LM27402
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
www.ti.com
Application Information (continued)
8.1.12.3 Low-Side Power MOSFET
The next set of equations are used to calculate the losses due to the low-side MOSFET.
PCND_LS
IOUT2 x RDS(ON)_LS x (1-D) x 1.3
PD = Tdeadtime x fSW x IOUT x VFD
PRR = QRR x fSW x VIN
PTOT_LS = PCND_LS + PD + PRR
(26)
PCND_LS is the conduction loss of the low-side MOSFET during the 1-D cycle and RDS(ON)_LS is its on-state
resistance. PD is the deadtime power loss due to the body diode drop of the low-side MOSFET. Tdeadtime is the
total deadtime. PRR is the reverse recovery charge power loss. QRR is the total reverse recovery charge typically
specified in the MOSFET datasheet. PTOT_LS is the total power dissipation of the low-side MOSFET.
8.1.12.4 Gate-Charge Loss
A finite amount of gate charge is required in order to switch the high-side and low-side power MOSFETs. This
gate charge is continually charging the MOSFET gates during every switching cycle and appears as a constant
current flowing to the controller from the input supply. The next equation describes the power loss due to the
gate charge.
PQG = VIN x (QGHS + QGLS) x fSW
(27)
PQG is the total gate charge power loss, QGHS and QGLS are the respective high-side and low-side MOSFET gate
charges found in the MOSFET datasheets, VIN is the input voltage, and fSW is the switching frequency.
8.1.12.5 Input and Output Capacitor ESR Losses
Both the input and output capacitors are subject to steady state AC current and must be taken into consideration
when calculating power losses. The next equation shown is the input capacitor ESR power loss.
2
PIN_CAP = ICIN_RMS x RESR_CIN
(28)
The input capacitor power loss equation includes the effective series resistance or RESR_IN of the input capacitor.
The power loss due to the ESR of the output capacitor is:
POUT_CAP =
üIL2
x RESR
12
(29)
The output capacitor power loss equation includes the peak-to-peak inductor current, ΔIL, and the effective series
resistance or RESR of the output capacitor.
8.1.12.6 Inductor Losses
The losses due to the inductor are caused primarily by its DCR. The next equation calculates the inductor DCR
power loss.
2
PDCR = IRMS x RDCR x 1.2
(30)
PDCR is the total power loss of the Inductor. A self-heating coefficient of 1.2 is included in this equation to
approximate the effects of the copper temperature coefficient approximately equal to 3900ppm/°C. RDCR is the
inductor DC resistance.
30
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
LM27402
www.ti.com
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
Application Information (continued)
8.1.12.7 Controller Losses
The controller loss remains constant and typically contributes a very small loss of power. The quiescent current is
the main factor in terms of power loss attributed to the controller and it remains constant at 4 mA. The quiescent
current power loss equation is:
PIQ = VIN x IQ
(31)
The controller IQ power loss equation includes the IQ current (4 mA) and the input voltage VIN.
It is also important to calculate the power dissipated in the controller itself due to the gate charge component of
current flowing from VIN to VDD. This can cause the controller to operate at an elevated temperature given the
power dissipation of the LDO pass device. The next equation calculates the power dissipated by the internal
LDO.
PLDO = (VVIN - 4.5) x (QGLS+QGHS) x fSW
(32)
PLDO is the power dissipated in the LDO, QGHS and QGLS are the high-side and low-side MOSFET gate charges,
respectively.
8.1.12.8 Overall Efficiency
After calculating the losses, the efficiency is thus calculated using:
POUT
x 100
(%) = P + P
OUT
LOSS
PLOSS = PTOT_HS + PTOT_LS + PQG + PDCR + PIN_CAP + POUT_CAP + PIQ
POUT = VOUT x IOUT
(33)
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
31
LM27402
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
www.ti.com
8.2 Typical Applications
8.2.1 Example Circuit 1
VIN
5 V-12 V
CBOOT
CF
CIN
RF
QH
CBOOT
DBOOT
VIN
VDD
RPGD
HG
VOUT
1.5 V
LOUT
LM27402
SW
CVDD
QL
LG
CS
RS
COUT
DSW
PGOOD
CS+
EN
CSBY
SYNC
SS/TRACK
CC3
RFB1
FB
FADJ
CSS
RSET
CS-
GND COMP
CC1
CC2
RFADJ
RC2
RC1
RFB2
Figure 41. 4.5-V to 20-V Input, 1.5-V Output at 20 A, 300-kHz Switching Frequency
8.2.1.1 Design Requirements
The schematic diagram of a 20-A buck regulator is given in Figure 41 and its BOM is listed in Table 1. In this
example, the target full-load efficiency is 88% at 12-V input voltage. Output voltage is adjusted simply by
changing RFB2. The free-running switching frequency is set to 300 kHz by resistor RFADJ. The output voltage softstart time is 10 ms.
8.2.1.2 Detailed Design Procedure
The design procedure for an LM27402-based converter for a given application is streamlined by using the
LM27402 Quick-Start Design Tool available as a free download, or by availing of TI's WEBENCH® Designer
online software. Such tools are complemented by the availability of the LM27402 evaluation module (EVM)
design as well as numerous LM27402 reference designs populated in TI Designs™ reference design library.
8.2.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM27402 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
32
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
LM27402
www.ti.com
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
Typical Applications (continued)
The current limit setpoint in this design is set at 25 A at 25°C, based on resistor RSET and the inductor DCR of
2.34 mΩ. Of course, the current limit setpoint must always be selected such that the operating current level does
not exceed the saturation current specification of the chosen inductor. The component values for the DCR sense
network (RS and CS in Figure 41) are chosen based on setting the RSCS product approximately equal to L/RDCR,
as recommended in the Setting the Current Limit Threshold section. The MOSFETs are chosen for both lowest
conduction and switching power loss, as discussed in detail in the Power MOSFETs section.
Table 1. Bill of Materials
DESIGNATOR
TYPE
PARAMETERS
PART NUMBER
QTY
U1
IC
Synchronous Buck Voltage-Mode PWM Controller
LM27402
1
MANUFACTURER
TI
CBOOT
Capacitor
0.22 µF, Ceramic, X7R, 25 V, 10%
GRM188R71E224KA88D
1
Murata
CC1
Capacitor
3.9 nF, Ceramic, X7R, 50 V, 10%
GRM188R71H392KA01D
1
Murata
CC2
Capacitor
150 pF, Ceramic, C0G, 50 V, 5%
GRM1885C1H151JA01D
1
Murata
CC3
Capacitor
820 pF, Ceramic, C0G, 50 V, 5%
GRM1885C1H821JA01D
1
Murata
CVDD
Capacitor
1 µF, Ceramic, X5R, 25 V, 10%
GRM188R61E105KA12D
1
Murata
CF
Capacitor
1 µF, Ceramic, X5R, 25 V, 10%
GRM188R61E105KA12D
1
Murata
CIN
Capacitor
22 µF, Ceramic, X5R, 25 V, 10%
GRM32ER61E226KE15L
5
Murata
COUT
Capacitor
100 µF, Ceramic, X5R, 6.3 V, 20%
C1210C107M9PACTU
4
Kemet
CS
Capacitor
0.22 µF, Ceramic, X7R, 25 V, 10%
GRM188R71E224KA88D
1
Murata
CSS
Capacitor
47 nF, Ceramic, X7R, 16 V, 10%
GRM188R71C473KA01D
1
Murata
CSBY
Capacitor
100 pF, Ceramic, C0G, 50 V, 5%
GRM1885C1H101JA01D
1
Murata
Diode
Schottky Diode, Average I = 100 mA, Max Surge I =
750 mA
CMOSH-3
1
Central Semi
DBOOT
DSW
Diode
Schottky Diode, Average I = 3A, Max Surge I = 80A
CMSH3-40M
1
Central Semi
LOUT
Inductor
0.68 µH, 2.34 mΩ
IHLP5050CEERR68M06
1
Vishay
QL
N-CH MOSFET
30 V, 60 A, 43.5 nC, RDS(on) at 4.5 V = 1.85 mΩ
Si7192DP
1
Vishay
QH
N-CH MOSFET
25 V, 40 A, 13 nC, RDS(on) at 4.5 V = 6.2 mΩ
SiR436DP
1
Vishay
RC1
Resistor
8.06 kΩ, 1%, 0.1 W
CRCW06038k06FKEA
1
Vishay
RC2
Resistor
261 Ω, 1%, 0.1 W
CRCW0603261RFKEA
1
Vishay
RFADJ
Resistor
45.3 kΩ, 1%, 0.1 W
CRCW060345K3FKEA
1
Vishay
RFB1
Resistor
20.0 kΩ, 1%, 0.1 W
CRCW060320K0FKEA
1
Vishay
RFB2
Resistor
13.3 kΩ, 1%, 0.1 W
CRCW060320K0FKEA
1
Vishay
RF
Resistor
2.2 Ω, 5%, 0.1 W
CRCW06032R20JNEA
1
Vishay
RPGD
Resistor
51.1 kΩ, 5%, 0.1 W
CRCW060351K1JNEA
1
Vishay
RS
Resistor
1.3 kΩ, 1%, 0.1 W
CRCW06031K30FKEA
1
Vishay
RSET
Resistor
6.34 kΩ, 1%, 0.1 W
CRCW06036K34FKEA
1
Vishay
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
33
LM27402
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
www.ti.com
8.2.1.3 Application Curves
100
VIN = 5V
EFFICIENCY (%)
95
90
VIN = 12V
85
80
75
70
0
5
10
15
20
OUTPUT CURRENT (A)
34
Figure 42. Converter Efficiency vs Output Current
Figure 43. Start-up Characteristic with EN Stepped High,
15-A Electronic Load (2 ms/div)
Figure 44. 10-A to 20-A Load Transient (100 µs/div)
Figure 45. 0-A to 20-A Load Transient (100 µs/div)
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
LM27402
www.ti.com
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
8.2.2 Example Circuit 2
VIN
5 V ± 12 V
CBOOT
CIN
RF
CF
QH1
QH2
VIN
HG
CBOOT
DBOOT
SW
VDD
VIN
RPGD
REN1
CVDD
VOUT
3.3 V
L
LM27402
QL
+
CS
RS
DSW
LG
COUT1
COUT2
PGOOD
CS+
EN
CSBY
REN2
SYNC
SS/TRACK
CSS
RSET
CC3
CSRFB1
FB
FADJ
GND COMP
CC1
RC2
RC1
RFB2
CC2
RFADJ
Figure 46. 5-V to 12-V Input Voltage Range, 3.3-V Output, 25-A Output Current, 300-kHz Switching
Frequency
Table 2. Bill Of Materials
DESIGNATOR
TYPE
PARAMETERS
PART NUMBER
QTY
U1
IC
Synchronous Buck Voltage-Mode PWM Controller
LM27402
1
TI
CBOOT
Capacitor
0.22 µF, Ceramic, X7R, 25 V, 10%
GRM188R71E224KA88D
1
Murata
CC1
Capacitor
1200 pF, Ceramic, COG, 50 V, 5%
GRM1885C1H122JA01D
1
Murata
CC2
Capacitor
56 pF, Ceramic, COG, 50 V, 5%
GRM1885C1H560JA01D
1
Murata
CC3
Capacitor
820 pF, Ceramic, COG, 50 V, 5%
GRM1885C1H821JA01D
1
Murata
CVDD
Capacitor
1 µF, Ceramic, X5R, 25 V, 10%
GRM188R61E105KA12D
1
Murata
CF
Capacitor
1 µF, Ceramic, X5R, 25 V, 10%
GRM188R61E105KA12D
1
Murata
CIN
Capacitor
22 µF, Ceramic, X5R, 25 V, 10%
GRM32ER61E226KE15L
5
Murata
COUT 1
Capacitor
100 µF, Ceramic, X5R, 6.3 V, 20%
C1210C107M9PACTU
1
Kemet
COUT2
Capacitor
330 µF, POSCAP, 6.3 V, 20%
6TPE1330MIL
1
Sanyo
CS
Capacitor
0.22 µF, Ceramic, X7R, 25 V, 10%
GRM188R71E224KA88D
1
Murata
CSS
Capacitor
47000 pF, Ceramic, X7R, 16 V, 10%
GRM188R71E473KA01D
1
Murata
CSBY
Capacitor
100 pF, Ceramic, C0G, 50 V, 5%
GRM1885C1H101JA01D
1
Murata
Diode
Schottky Diode, Average I = 100 mA, Max Surge I =
750 mA
CMOSH-3
1
Central Semi
DBOOT
MANUFACTURER
DSW
Diode
Schottky Diode, Average I = 3 A, Max Surge I = 80A
CMSH3-40M
1
Central Semi
LOUT
Inductor
1 µH, 0.9 mΩ
SER2010-102ML
1
Coilcraft
QL
N-CH MOSFET
30 V, 60 A, 43.5 nC, RDS(on) at 4.5V = 1.85 mΩ
Si7192DP
1
Vishay
QH(1,2)
N-CH MOSFET
25 V, 50 A, 20 nC, RDS(on) at 4.5V = 3.4 mΩ
SiR892DP
1
Vishay
RC1
Resistor
18.7 kΩ, 1%, 0.1 W
CRCW060318K7FKEA
1
Vishay
RC2
Resistor
4.75 kΩ, 1%, 0.1 W
CRCW06034K75FKEA
1
Vishay
RFADJ
Resistor
45.3 kΩ, 1%, 0.1 W
CRCW060345K3FKEA
1
Vishay
RFB1
Resistor
20.0 kΩ, 1%, 0.1 W
CRCW060320K0FKEA
1
Vishay
RFB2
Resistor
4.42 kΩ, 1%, 0.1 W
CRCW06034K42FKEA
1
Vishay
RF
Resistor
2.2Ω, 5%, 0.1 W
CRCW06032R20JNEA
1
Vishay
RPGD
Resistor
51.1 kΩ, 5%, 0.1 W
CRCW060351K1JNEA
1
Vishay
RS
Resistor
4.12 kΩ, 1%, 0.1 W
CRCW06034K12FKEA
1
Vishay
RSET
Resistor
4.53 kΩ, 1%, 0.1 W
CRCW06034K53FKEA
1
Vishay
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
35
LM27402
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
www.ti.com
8.2.3 Example Circuit 3
VIN
3.3 V
CBOOT
QH
VIN
CBOOT
DBOOT
HG
SW
CVDD
VOUT
0.9 V
LOUT
LM27402
VDD
RPGD
CIN
RF
CF
RDD
QL
CS
RS
LG
COUT
DSW
PGOOD
CS+
EN
CSBY
SYNC
SS/TRACK
CC3
RFB1
FB
FADJ
CSS
RSET
CS-
GND COMP
CC1
RC2
RC1
RFB2
CC2
RFADJ
Figure 47. 3.3-V Input voltage, 0.9-V Output Voltage, 20-A Output Current, 500-kHz Switching Frequency
Table 3. Bill Of Materials
DESIGNATOR
PARAMETERS
PART NUMBER
QTY
MANUFACTURER
U1
IC
Synchronous Buck Voltage-Mode PWM Controller
LM27402
1
TI
CBOOT
Capacitor
0.22 µF, Ceramic, X7R, 25 V, 10%
GRM188R71E224KA88D
1
Murata
CC1
Capacitor
820 pF, Ceramic, COG, 50 V, 5%
GRM1885C1H821JA01D
1
Murata
CC2
Capacitor
68 pF, Ceramic, COG, 50 V, 5%
GRM1885C1H680JA01D
1
Murata
CC3
Capacitor
390 pF, Ceramic, COG, 50 V, 5%
GRM1885C1H391JA01D
1
Murata
CVDD
Capacitor
1 µF, Ceramic, X5R, 25 V, 10%
GRM188R61E105KA12D
1
Murata
CF
Capacitor
1 µF, Ceramic, X5R, 25 V, 10%
GRM188R61E105KA12D
1
Murata
CIN
Capacitor
22 µF, Ceramic, X5R, 25 V, 10%
C2012X5R0J226M
5
TDK
COUT
Capacitor
100 µF, Ceramic, X5R, 6.3 V, 20%
JMK316BJ107ML
3
Taiyo Yuden
CS
Capacitor
0.22 µF, Ceramic, X7R, 25 V, 10%
GRM188R71E224KA88D
1
Murata
CSS
Capacitor
22000 pF, Ceramic, X7R, 16 V, 10%
GRM188R71E223KA01D
1
Murata
CSBY
Capacitor
68 pF, Ceramic, C0G, 50 V, 5%
GRM1885C1H680JA01D
1
Murata
Diode
Schottky Diode, Average I = 100 mA, Max Surge I =
750 mA
CMOSH-3
1
Central Semi
Central Semi
DBOOT
36
TYPE
DSW
Diode
Schottky Diode, Average I = 3A, Max Surge I = 80 A
CMSH3-40M
1
LOUT
Inductor
0.33 µH, 1.4 mΩ
RL-8250-1.4-R33M
1
Renco
QL
N-Ch MOSFET
20 V, 100 A, 64 nC, RDS(on) at 4.5 V = 1.6 mΩ
BSC019N02KS
1
Infineon
QH
N-Ch MOSFET
20 V, 100 A, 40 nC, RDS(on) at 4.5 V = 2.1 mΩ
BSC026N02KS
1
Infineon
RC1
Resistor
10.0 kΩ, 1%, 0.1 W
CRCW060310K0FKEA
1
Vishay
RC2
Resistor
150Ω, 1%, 0.1 W
CRCW0603150RFKEA
1
Vishay
RDD
Resistor
1Ω, 5%, 0.1 W
CRCW06031R00JNEA
1
Vishay
RFADJ
Resistor
20.0 kΩ, 1%, 0.1 W
CRCW060320K0FKEA
1
Vishay
RFB1
Resistor
20.0 kΩ, 1%, 0.1 W
CRCW060320K0FKEA
1
Vishay
RFB2
Resistor
40.2 kΩ, 1%, 0.1 W
CRCW060340K2FKEA
1
Vishay
RF
Resistor
2.2 Ω, 5%, 0.1 W
CRCW06032R20JNEA
1
Vishay
RPGD
Resistor
51.1 kΩ, 5%, 0.1 W
CRCW060351K1JNEA
1
Vishay
RS
Resistor
1.07 kΩ, 1%, 0.1 W
CRCW06031K07FKEA
1
Vishay
RSET
Resistor
5.11 kΩ, 1%, 0. W
CRCW06035K11FKEA
1
Vishay
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
LM27402
www.ti.com
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
9 Power Supply Recommendations
The LM27402 PWM controller is designed to operate from an input voltage supply range between 3 V and 20 V.
If the input supply is located more than a few inches from the LM27402-based converter, additional bulk
capacitance may be required in addition to ceramic bypass capacitance. Given the negative incremental input
impedance of a buck converter, a bulk electrolytic component provides damping to reduce effects of input line
parasitic inductance resonating with high-Q ceramic capacitors.
10 Layout
10.1 Layout Guidelines
Careful PCB design and layout are important in a high current, fast switching circuit (with high current and
voltage slew rates) to assure appropriate device operation and design robustness. As expected, certain issues
must be considered before designing a PCB layout using the LM27402. The main switching loop of the power
stage is denoted by 1 in Figure 48. The buck converter topology means that particularly high di/dt current will
flow in loop 1, and it becomes mandatory to reduce the parasitic inductance of this loop by minimizing its
effective loop area. For loop 2 however, the di/dt through inductor LF and capacitor COUT is naturally limited by
the inductor. Keeping the area of loop 2 small is not nearly as important as that of loop 1. Also important are the
gate drive loops of the low-side and high-side MOSFETs, denoted by 3 and 4, respectively, in Figure 48.
VIN
VDD
LM27402
CBOOT
CIN
CBOOT
High-side
gate
driver
Q1
HG
LF
(3)
VOUT
SW
(1)
VDD
CVDD
Low-side
gate
driver
LG
GND
(2)
Q2
COUT
(4)
GND
Figure 48. DC/Dc Converter Ground System With Power Stage and Gate Drive Circuit Switching Loops
10.1.1 Power Stage Layout
1. Input capacitor(s), output capacitor(s) and MOSFETs are the constituent components in the power stage of a
buck regulator and are typically placed on the top side of the PCB (solder side). Leveraging any system-level
airflow, the benefits of convective heat transfer are thus maximized. In a two-sided PCB layout, small-signal
components are typically placed on the bottom side (component side). At least one inner plane must be
inserted, connected to ground, in order to shield and isolate the small-signal traces from noisy power traces
and lines.
2. The DC/Dc converter has several high-current loops. Minimize the area of these loops in order to suppress
generated switching noise and parasitic loop inductance and optimize switching performance.
– Loop 1: The most important loop to minimize the area of is the path from the input capacitor(s) through
the high- and low-side MOSFETs, and back to the capacitor(s) through the ground connection. Connect
the input capacitor(s) negative terminal close to the source of the low-side MOSFET (at ground).
Similarly, connect the input capacitor(s) positive terminal close to the drain of the high-side MOSFET (at
VIN). Refer to loop 1 of Figure 48.
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
37
LM27402
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
www.ti.com
Layout Guidelines (continued)
– Loop 2. The second important loop is the path from the low-side MOSFET through inductor and output
capacitor(s), and back to source of the low-side MOSFET through ground. Connect source of the low-side
MOSFET and negative terminal of the output capacitor(s) at ground as close as possible. Refer to loop 2
of Figure 48.
3. The PCB trace defined as SW node, which connects to the source of the high-side (control) MOSFET, the
drain of the low-side (synchronous) MOSFET and the high-voltage side of the inductor, must be short and
wide. However, the SW connection is a source of injected EMI and thus must not be too large.
4. Follow any layout considerations of the MOSFETs as recommended by the MOSFET manufacturer, including
pad geometry and solder paste stencil design.
5. The SW pin connects to the switch node of the power conversion stage, and it acts as the return path for the
high-side gate driver. The parasitic inductance inherent to loop 1 in Figure 48 and the output capacitance
(COSS) of both power MOSFETs form a resonant circuit that induces high frequency (>100 MHz) ringing on
the SW node. The voltage peak of this ringing, if not controlled, can be significantly higher than the input
voltage. Ensure that the peak ringing amplitude does not exceed the absolute maximum rating limit for the
SW pin. In many cases, a series resistor and capacitor snubber network connected from the SW node to
GND damps the ringing and decreases the peak amplitude. Provide provisions for snubber network
components in the printed circuit board layout. If testing reveals that the ringing amplitude at the SW pin is
excessive, then include snubber components.
10.1.2 Gate Drive Layout
The LM27402 high- and low-side gate drivers incorporate short propagation delays, adaptive deadtime control
and low-impedance output stages capable of delivering large peak currents with very fast rise and fall times to
facilitate rapid turn-on and turn-off transitions of the power MOSFETs. Very high di/dt can cause unacceptable
ringing if the trace lengths and impedances are not well controlled.
Minimization of stray/parasitic loop inductance is key to optimizing gate drive switching performance, whether it
be series gate inductance that resonates with MOSFET gate capacitance or common source inductance
(common to gate and power loops) that provides a negative feedback component opposing the gate drive
command, thereby increasing MOSFET switching times. The following loops are important:
• Loop 3: high-side MOSFET, Q1. During the high-side MOSFET turn on, high current flows from the boot
capacitor through the gate driver and high-side MOSFET, and back to negative terminal of the boot capacitor
through the SW connection. Conversely, to turn off the high-side MOSFET, high current flows from gate of the
high-side MOSFET through the gate driver and SW, and back to source of the high-side MOSFET through
the SW trace. Refer to loop 3 of Figure 48.
• Loop 4: low-side MOSFET, Q2. During the low-side MOSFET turn on, high current flows from VDD
decoupling capacitor through the gate driver and low-side MOSFET, and back to negative terminal of the
capacitor through ground. Conversely, to turn off the low-side MOSFET, high current flows from gate of the
low-side MOSFET through the gate driver and GND, and back to source of the low-side MOSFET through
ground. Refer to loop 4 of Figure 48.
The following circuit layout guidelines are strongly recommended when designing with high-speed MOSFET gate
drive circuits.
1. Connections from gate driver outputs, HG and LG, to the respective gate of the high-side or low-side
MOSFET should be as short as possible to reduce series parasitic inductance. Use 0.65 mm (25 mils) or
wider traces. Use via(s), if necessary, of at least 0.5 mm (20 mils) diameter along these traces. Route HG
and SW gate traces as a differential pair from the LM27403 to the high-side MOSFET, taking advantage of
flux cancellation.
2. Minimize the current loop path from the VDD and CBOOT pins through their respective capacitors as these
provide the high instantaneous current to charge the MOSFET gate capacitances. Specifically, locate the
bootstrap capacitor, CBOOT, close to the LM27402's CBOOT and SW pins to minimize the area of loop 3
associated with the high-side driver. Similarly, locate the VDD capacitor, CVDD, close to the LM27402's VDD
and GND pins to minimize the area of loop 4 associated with the low-side driver.
3. Placing a 2-Ω to 10-Ω BOOT resistor in series with the BOOT capacitor slows down the high-side MOSFET
turn-on transition, serving to reduce the voltage ringing and peak amplitude at the SW node at the expense
of increased MOSFET turn-on power loss.
38
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
LM27402
www.ti.com
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
Layout Guidelines (continued)
10.1.3 Controller Layout
Components related to the analog and feedback signals, current limit setting and temperature sense are
considered in the following:
1. In general, separate power and signal traces, and use a ground plane to provide noise shielding.
2. Place all sensitive analog traces and components such as COMP, FB, FADJ, and SS/TRACK away from
high-voltage switching nodes such as SW, HG, LG or CBOOT. Use internal layer(s) as ground plane(s). Pay
particular attention to shielding the feedback (FB) trace from power traces and components.
3. The upper feedback resistor can be connected directly to the output voltage sense point at the load device or
the bulk capacitor at the converter side. This connections can be used for the purpose of remote sensing at
the downstream load; however, care must be taken to route the trace to prevent noise coupling from noisy
nets.
4. Connect the OCP setpoint resistor from CS– pin to VOUT and make the connections as close as possible to
the LM27402. The trace from the CS– pin to the resistor must avoid coupling to a high-voltage switching
node. Similar precautions apply if a resistor is tied to the CS+ pin.
5. Minimize the current loop from the VDD and VIN pins through their respective decoupling capacitors to the
GND pin. In other words, locate these capacitors as close as possible to the LM27402.
10.1.4 Thermal Design and Layout
The useful operating temperature range of a PWM controller with integrated gate drivers and bias supply LDO
regulator is greatly affected by:
• Average gate drive current requirements of the power MOSFETs
• Switching frequency
• Operating input voltage (affecting LDO voltage drop and hence its power dissipation)
• Thermal characteristics of the package and operating environment
In order for a PWM controller to be useful over a particular temperature range, the package must allow for the
efficient removal of the heat produced while keeping the junction temperature within rated limits. The LM27402
controller is available in small 4-mm × 4-mm WQFN-24 (RUM) and 4.4-mm × 5-mm HTSSOP-16 (PWP)
PowerPAD™ packages to cover a range of application requirements. The thermal metrics of these packages are
summarized in the Thermal Information section of this datasheet. For detailed information regarding the thermal
information table, please refer to IC Package Thermal Metrics, SPRA953, application report.
Both package offers a means of removing heat from the semiconductor die through the exposed thermal pad at
the base of the package. While the exposed pad of the LM27402's package is not directly connected to any
leads of the package, it is thermally connected to the substrate of the device (ground). This allows a significant
improvement in heat-sinking, and it becomes imperative that the PCB is designed with thermal lands, thermal
vias, and a ground plane to complete the heat removal subsystem. The LM27402's exposed pad is soldered to
the ground-connected copper land on the PCB directly underneath the device package, reducing the thermal
resistance to a very low value.
Numerous vias with a 0.3-mm diameter connected from the thermal land to the internal/solder-side ground
plane(s) are vital to help dissipation. In a multi-layer PCB design, a solid ground plane is typically placed on the
PCB layer below the power components. Not only does this provide a plane for the power stage currents to flow
but it also represents a thermally conductive path away from the heat generating devices.
The thermal characteristics of the MOSFETs also are significant. The high-side MOSFET's drain pad is normally
connected to a VIN plane for heat-sinking. The low-side MOSFET's drain pad is tied to the SW plane, but the SW
plane area is purposely kept relatively small to mitigate EMI concerns.
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
39
LM27402
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
www.ti.com
10.2 Layout Example
Figure 49 and Figure 50 show an example PCB layout based on the LM27402 20A EVM design. For more
details, please see the LM27402 Evaluation Board User's Guide, SNVA406.
Figure 49. LM27402 PCB Layout – Top Layer
Figure 50. LM27402 PCB Layout – Bottom Layer
40
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
LM27402
www.ti.com
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Development Support
11.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM27402 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
• WEBENCH http://www.ti.com/webench
• TI NexFET™ Power Block Module CSD87330Q3D
• LM27402 Design Tool
• TI Designs
11.2 Documentation Support
11.2.1 Related Documentation
• LM27402 EVM User's Guide, SNVA406
• LM27402 Current Limit Application Circuits, SNVA441
• 6/4-Bit VID Programmable Current DAC for Point of Load Regulators with Adjustable Start-Up Current,
SNVS822
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
41
LM27402
SNVS615K – JANUARY 2010 – REVISED FEBRUARY 2018
www.ti.com
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
NexFET, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
42
Submit Documentation Feedback
Copyright © 2010–2018, Texas Instruments Incorporated
Product Folder Links: LM27402
PACKAGE OPTION ADDENDUM
www.ti.com
2-Mar-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM27402MH/NOPB
ACTIVE
HTSSOP
PWP
16
92
RoHS & Green
SN
Level-1-260C-UNLIM
L27402
MH
LM27402MHX/NOPB
ACTIVE
HTSSOP
PWP
16
2500
RoHS & Green
SN
Level-1-260C-UNLIM
L27402
MH
LM27402SQ/NOPB
ACTIVE
WQFN
RUM
16
1000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
27402S
LM27402SQX/NOPB
ACTIVE
WQFN
RUM
16
4500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
27402S
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
