LM3046MX/NOPB

LM3046 www.ti.com SNLS372B – JULY 1999 – REVISED MARCH 2013 LM3046 Transistor Array Check for Samples: LM3046 FEATURES APPLICATIONS • • 1 2 • • • • Two Matched Pairs of Transistors – VBE Matched ±5 mV – Input Offset Current 2 μA Max at IC = 1 mA Five General Purpose Monolithic transistors Operation from DC to 120 MHz Wide Operating Current Range Low Noise Figure: 3.2 dB typ at 1 kHz • • General Use in All Types of Signal Processing Systems Operating Anywhere in the Frequency Range from DC to VHF Custom Designed Differential Amplifiers Temperature Compensated Amplifiers DESCRIPTION The LM3046 consists of five general purpose silicon NPN transistors on a common monolithic substrate. Two of the transistors are internally connected to form a differentially-connected pair. The transistors are well suited to a wide variety of applications in low power system in the DC through VHF range. They may be used as discrete transistors in conventional circuits however, in addition, they provide the very significant inherent integrated circuit advantages of close electrical and thermal matching. The LM3046 is supplied in a 14-lead SOIC package. Schematic and Connection Diagram Figure 1. SOIC Package Top View See Package Number D (R-PDSO-G14) These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999–2013, Texas Instruments Incorporated LM3046 SNLS372B – JULY 1999 – REVISED MARCH 2013 www.ti.com Absolute Maximum Ratings (1) (2) (3) Power Dissipation Each Transistor Total Package TA = 25°C 300 750 TA = 25°C to 55°C 300 750 TA > 55°C Derate at 6.67 TA = 25°C to 75°C 15 Collector to Base Voltage, VCBO 20 Collector to Substrate Voltage, VCIO (4) 20 Emitter to Base Voltage, VEBO 50 −65°C to +85°C Storage Temperature Range Dual-In-Line Package Soldering (10 Sec.) 2 mA −40°C to +85°C Operating Temperature Range (4) V 5 Collector Current, IC (2) (3) mW/°C mW/°C Collector to Emitter Voltage, VCEO (1) mW mW TA > 75°C Soldering Information Units 260°C SOIC Package Vapor Phase (60 Seconds) 215°C Infrared (15 Seconds) 220°C “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” for other methods of soldering surface mount devices. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. The collector of each transistor is isolated from the substrate by an integral diode. The substrate (terminal 13) must be connected to the most negative point in the external circuit to maintain isolation between transistors and to provide for normal transistor action. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LM3046 LM3046 www.ti.com SNLS372B – JULY 1999 – REVISED MARCH 2013 Electrical Characteristics (1) Min Typ Collector to Base Breakdown Voltage (V(BR)CBO) Parameter IC = 10 μA, IE = 0 Conditions 20 60 V Collector to Emitter Breakdown Voltage (V(BR)CEO) IC = 1 mA, IB = 0 15 24 V Collector to Substrate Breakdown Voltage (V(BR)CIO) IC = 10 μA, ICI = 0 20 60 V Emitter to Base Breakdown Voltage (V(BR)EBO) IE 10 μA, IC = 0 5 7 V Collector Cutoff Current (ICBO) VCB = 10V, IE = 0 Collector Cutoff Current (ICEO) VCE = 10V, IB = 0 VCE = 3V Static Forward Current Transfer Ratio (Static Beta) (hFE) 0.002 IC = 10 mA IC = 1 mA 40 Base to Emitter Voltage (VBE) 40 nA 0.5 μA 2 μA 100 54 VCE = 3V, IC = 1 mA VCE = 3V Units 100 IC = 10 μA Input Offset Current for Matched Pair Q1 and Q2 |IO1 − IIO2| Max 0.3 IE = 1 mA 0.715 IE = 10 mA 0.800 V Magnitude of Input Offset Voltage for Differential Pair |VBE1 − VBE2| VCE = 3V, IC = 1 mA 0.45 Magnitude of Input Offset Voltage for Isolated Transistors |VBE3 − VBE4|, |VBE4 − VBE5|, |VBE5 − VBE3| VCE = 3V, IC = 1 mA 0.45 VCE = 3V, IC = 1 mA −1.9 mV/°C IB = 1 mA, IC = 10 mA 0.23 V VCE = 3V, IC = 1 mA 1.1 μV/°C f = 1 kHz, VCE = 3V, IC = 100 μA, RS = 1 kΩ 3.25 dB 5 5 mV mV Temperature Coefficient of Base to Emitter Voltage (1) Collector to Emitter Saturation Voltage (VCE(SAT)) Temperature Coefficient of Input Offset Voltage (2) Low Frequency Noise Figure (NF) LOW FREQUENCY, SMALL SIGNAL EQUIVALENT CIRCUIT CHARACTERISTICS Forward Current Transfer Ratio (hfe) Short Circuit Input Impednace (hie) Open Circuit Output Impedance (hoe) 110 f = 1 kHz, VCE = 3V, IC = 1 mA 3.5 kΩ 15.6 μmho 1.8 x 10−4 Open Circuit Reverse Voltage Transfer Ratio (hre) ADMITTANCE CHARACTERISTICS 31 − j 1.5 Forward Transfer Admittance (Yfe) Input Admittance (Yie) Output Admittance (Yoe) 0.3+J 0.04 f = 1 MHz, VCE = 3V, IC = 1 mA 0.001+j 0.03 See Figure 16 Reverse Transfer Admittance (Yre) Gain Bandwidth Product (fT) VCE = 3V, IC = 3 mA Emitter to Base Capacitance (CEB) VEB = 3V, IE = 0 0.6 pF Collector to Base Capacitance (CCB) VCB = 3V, IC = 0 0.58 pF Collector to Substrate Capacitance (CCI) VCS = 3V, IC = 0 2.8 pF (1) 300 550 (TA = 25°C unless otherwise specified) Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LM3046 3 LM3046 SNLS372B – JULY 1999 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics 4 Typical Collector To Base Cutoff Current vs Ambient Temperature for Each Transistor Typical Collector To Emitter Cutoff Current vs Ambient Temperature for Each Transistor Figure 2. Figure 3. Typical Static Forward Current-Transfer Ratio and Beta Ratio for Transistors Q1 and Q2 vs Emitter Current Typical Input Offset Current for Matched Transistor Pair Q1 Q2 vs Collector Current Figure 4. Figure 5. Typical Static Base To Emitter Voltage Characteristic and Input Offset Voltage for Differential Pair and Paired Isolated Transistors vs Emitter Current Typical Base To Emitter Voltage Characteristic forEach Transistor vs Ambient Temperature Figure 6. Figure 7. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LM3046 LM3046 www.ti.com SNLS372B – JULY 1999 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Typical Input Offset Voltage Characteristics for Differential Pair and Paired Isolated Transistors vs Ambient Temperature Typical Noise Figure vs Collector Current Figure 8. Figure 9. Typical Noise Figure vs Collector Current Typical Noise Figure vs Collector Current Figure 10. Figure 11. Typical Normalized Forward Current Transfer Ratio, Short Circuit Input Impedance, Open Circuit Output Impedance, and Open Circuit Reverse Voltage Transfer Ratio vs Collector Current Typical Forward Transfer Admittance vs Frequency Figure 12. Figure 13. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LM3046 5 LM3046 SNLS372B – JULY 1999 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) 6 Typical Input Admittance vs Frequency Typical Output Admittance vs Frequency Figure 14. Figure 15. Typical Reverse Transfer Admittance vs Frequency Typical Gain-Bandwidth Product vs Collector Current Figure 16. Figure 17. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LM3046 LM3046 www.ti.com SNLS372B – JULY 1999 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision A (March 2013) to Revision B • Page Changed layout of National Data Sheet to TI format ............................................................................................................ 4 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: LM3046 7 PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LM3046M NRND SOIC D 14 55 TBD Call TI Call TI -40 to 85 LM3046M LM3046M/NOPB ACTIVE SOIC D 14 55 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LM3046M LM3046MX NRND SOIC D 14 2500 TBD Call TI Call TI -40 to 85 LM3046M LM3046MX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LM3046M (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM3046MX SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1 LM3046MX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM3046MX SOIC D 14 2500 367.0 367.0 35.0 LM3046MX/NOPB SOIC D 14 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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