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LM3409, LM3409-Q1, LM3409HV, LM3409HV-Q1
SNVS602L – MARCH 2009 – REVISED JUNE 2016
LM3409, -Q1, LM3409HV, -Q1 P-FET Buck Controller for High-Power LED Drivers
1 Features
3 Description
•
The LM3409, LM3409-Q1, LM3409HV, and
LM3409HV-Q1 are P-channel MOSFET (PFET)
controllers for step-down (buck) current regulators.
They offer wide input voltage range, high-side
differential current sense with low adjustable
threshold voltage and fast output enable/disable
function and a thermally enhanced 10-pin, HVSSOP
package. These features combine to make the
LM3409 family of devices ideal for use as constant
current sources for driving LEDs where forward
currents up to 5 A are easily achievable.
1
•
•
•
•
•
•
•
•
•
•
•
LM3409-Q1 and LM3409HV-Q1 are Automotive
Grade Products: AEC-Q100 Grade 1 Qualified
2-Ω, 1-A Peak MOSFET Gate Drive
VIN Range: 6 V to 42 V (LM3409, LM3409-Q1)
VIN Range: 6 V to 75 V (LM3409HV, LM3409HVQ1)
Differential, High-Side Current Sense
Cycle-by-Cycle Current Limit
No Control Loop Compensation Required
10,000:1 PWM Dimming Range
250:1 Analog Dimming Range
Supports All-Ceramic Output Capacitors and
Capacitor-less Outputs
Low-Power Shutdown and Thermal Shutdown
Thermally Enhanced 10-Pin, HVSSOP Package
The LM3409 devices use constant off-time (COFT)
control to regulate an accurate constant current
without the need for external control loop
compensation. Analog and PWM dimming are easy to
implement and result in a highly linear dimming range
with
excellent
achievable
contrast
ratios.
Programmable UVLO, low-power shutdown, and
thermal shutdown complete the feature set.
2 Applications
•
•
•
•
Device Information(1)
LED Driver
Constant Current Source
Automotive Lighting
General Illumination
PART NUMBER
LM3409
PACKAGE
BODY SIZE (NOM)
HVSSOP (10)
3.00 mm × 3.00 mm
PDIP (14)
19.177 mm × 6.35 mm
HVSSOP (10)
3.00 mm × 3.00 mm
LM3409-Q1
LM3409HV
LM3409HV-Q1
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
RUV2
RUV1
1
VIN
UVLO
10
VIN
CF
2
3
ROFF
VCC
IADJ
EN
LM3409/HV
CSP
CIN
9
8
RSNS
4
COFF
COFF
CSN
7
DAP
5
GND
PGATE
6
Q1
L1
VO
D1
ILED
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM3409, LM3409-Q1, LM3409HV, LM3409HV-Q1
SNVS602L – MARCH 2009 – REVISED JUNE 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
4
4
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
8.1 Overview ................................................................. 10
8.2 Functional Block Diagram ....................................... 10
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 18
9
Application and Implementation ........................ 19
9.1 Application Information............................................ 19
9.2 Typical Applications ................................................ 23
10 Power Supply Recommendations ..................... 37
11 Layout................................................................... 37
11.1 Layout Guidelines ................................................. 37
11.2 Layout Example .................................................... 37
12 Device and Documentation Support ................. 38
12.1
12.2
12.3
12.4
12.5
12.6
Device Support......................................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
38
38
38
38
38
38
13 Mechanical, Packaging, and Orderable
Information ........................................................... 38
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision K (July 2014) to Revision L
Page
•
Corrected package family reference in Features section ....................................................................................................... 1
•
Corrected package family reference in Device Information table........................................................................................... 1
•
Added Device Comparison table ............................................................................................................................................ 3
•
Corrected typographical error in package name reference in Pin Configuration and Functions section ............................... 3
•
Corrected typographical error in Absolute Maximum Ratings table ....................................................................................... 4
•
Corrected typographical error in package name reference in ESD Ratings table ................................................................. 4
•
Corrected package family reference in Thermal Information table......................................................................................... 5
Changes from Revision J (May 2013) to Revision K
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
Changes from Revision I (May 2013) to Revision J
•
2
Page
Changed layout of National Data Sheet to TI format ............................................................................................................ 1
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Copyright © 2009–2016, Texas Instruments Incorporated
Product Folder Links: LM3409 LM3409-Q1 LM3409HV LM3409HV-Q1
LM3409, LM3409-Q1, LM3409HV, LM3409HV-Q1
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SNVS602L – MARCH 2009 – REVISED JUNE 2016
5 Device Comparison Table
ORDERABLE
NUMBER
MAXIMUM INPUT
VOLTAGE (V)
LM3409
AEC-Q100 GRADE 1
QUALIFIED
N
42
LM3409-Q1
LM3409HV
Y
N
75
LM3409HV-Q1
Y
6 Pin Configuration and Functions
DGQ Package
10-Pin HVSSOP
Top View
1
2
3
UVLO
VIN
IADJ
VCC
EN
4
DAP
CSN
COFF
5
CSP
GND
PGATE
NFF Package
14-Pin PDIP
Top View
10
1
9
2
8
3
7
4
6
5
6
7
UVLO
VIN
NC
NC
IADJ
VCC
EN
CSP
COFF
CSN
GND
14
13
12
11
10
PGATE
NC
NC
9
8
Pin Functions
PIN
NAME
DESCRIPTION
PDIP
HVSSOP
UVLO
1
1
Input undervoltage lockout. Connect to a resistor divider from VIN and GND. Turn-on threshold is
1.24 V and hysteresis for turnoff is provided by a 22 µA current source.
IADJ
3
2
Analog LED current adjust. Apply a voltage from 0 to 1.24 V, connect a resistor to GND, or leave
open to set the current sense threshold voltage.
EN
4
3
Logic level enable and PWM dimming. Apply a voltage >1.74 V to enable device, a PWM signal to
dim, or a voltage < 0.5 V for low-power shutdown.
COFF
5
4
Off-time programming. Connect resistor from VO, capacitor to GND to set off-time.
GND
6
5
Connect to system ground.
PGATE
9
6
Gate drive. Connect to gate of external P-channel MOSFET.
CSN
10
7
Negative current sense. Connect to negative side of sense resistor.
CSP
11
8
Positive current sense. Connect to positive side of sense resistor (also to VIN).
VCC
12
9
VIN– referenced linear regulator output. Connect at least a 1-µF ceramic capacitor to VIN. The
regulator provides power for the P-channel MOSFET drive.
VIN
14
10
Input voltage. Connect to the input voltage.
Thermal pad
—
Connect to GND pin. Place 4 to 6 vias from thermal pad to GND plane.
Copyright © 2009–2016, Texas Instruments Incorporated
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SNVS602L – MARCH 2009 – REVISED JUNE 2016
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
VIN, EN, UVLO to GND
MIN
MAX
LM3409,
LM3409-Q1
–0.3
45
LM3409HV,
LM3409HV-Q1
–0.3
76
VIN to VCC, PGATE
UNIT
V
–0.3
7
V
–2.8
9.5
V
VIN to CSP, CSN
–0.3
0.3
V
COFF to GND
–0.3
4
V
VIN to PGATE
for 100 ns
COFF Current
continuous
±1
mA
IADJ Current
continuous
±5
mA
150
°C
Lead temperature (Soldering, 10 s)
260
°C
Infrared and convection reflow (15 s)
260
°C
125
°C
Junction temperature
Soldering information
Storage temperature, Tstg
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
7.2 ESD Ratings
VALUE
UNIT
LM3409 IN DGQ AND NFF PACKAGES
V(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
±1000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
±1000
V
LM3409-Q1 IN DGQ AND NFF PACKAGES
V(ESD)
(1)
(2)
(3)
(4)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002 (3) (4)
±2000
Charged device model (CDM), per AEC Q100-011
±1000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
The human body model is a 100 pF capacitor discharged through a 1.5-kΩ resistor into each pin.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VIN
MIN
MAX
LM3409,
LM3409-Q1
6
42
LM3409HV,
LM3409HV-Q1
6
75
−40
125
Junction temperature range, TJ
4
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UNIT
V
°C
Copyright © 2009–2016, Texas Instruments Incorporated
Product Folder Links: LM3409 LM3409-Q1 LM3409HV LM3409HV-Q1
LM3409, LM3409-Q1, LM3409HV, LM3409HV-Q1
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SNVS602L – MARCH 2009 – REVISED JUNE 2016
7.4 Thermal Information
THERMAL METRIC (1)
LM3409,
LM3409-Q1,
LM3409HV,
LM3409HV-Q1
LM3409
DGQ
(HVSSOP)
NFF
(PDIP)
UNIT
10 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance
54.4
49
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
53.7
36.3
°C/W
RθJB
Junction-to-board thermal resistance
33.8
28.9
°C/W
ψJT
Junction-to-top characterization parameter
3.9
21.1
°C/W
ψJB
Junction-to-board characterization parameter
33.5
28.7
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
3.5
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
Copyright © 2009–2016, Texas Instruments Incorporated
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SNVS602L – MARCH 2009 – REVISED JUNE 2016
www.ti.com
7.5 Electrical Characteristics
VIN = 24 V unless otherwise indicated. Typicals and limits appearing in plain type apply for TA = TJ = 25°C
minimum and maximum specification limits are specified by design, test, or statistical analysis.
PARAMETER
TEST CONDITIONS
(1)
. Data sheet
MIN (2)
TYP (1)
MAX (2)
UNIT
PEAK CURRENT COMPARATOR
VCST
VCSP – VCSN average peak
current threshold (3)
VADJ = 1 V
188
198
208
VADJ = VADJ-OC
231
246
261
AADJ
VADJ to VCSP – VCSN threshold
gain
0.1 < VADJ < 1.2 V
VADJ = VADJ-OC
VADJ-OC
IADJ pin open circuit voltage
IADJ
IADJ pin current
tDEL
CSN pin falling delay
0.2
mV
V/V
1.189
1.243
1.297
V
3.8
5
6.4
µA
CSN fall - PGATE rise
38
ns
2
mA
110
µA
SYSTEM CURRENTS
IIN
Operating input current
Not switching
ISD
Shutdown input current
EN = 0 V
Driver output resistance
Sourcing 50 mA
2
Sinking 50 mA
2
PFET DRIVER
RPGATE
Ω
VCC REGULATOR
VCC
VIN pin voltage - VCC pin voltage VIN > 9 V
0 < ICC < 20 mA
VCC-UVLO
VCC undervoltage lockout
threshold
VCC increasing
VCC-HYS
VCC UVLO hysteresis
VCC decreasing
ICC-LIM
VCC regulator current limit
5.5
6
6.5
V
3.73
V
283
mV
30
45
mA
1.122
1.243
OFF-TIMER AND ON-TIMER
VOFT
Off-time threshold
tD-OFF
COFF threshold to PGATE falling
delay
1.364
tON-MIN
Minimum ON-time
115
tOFF-MAX
Maximum OFF-time
300
µs
10
nA
25
V
ns
211
ns
UNDERVOLTAGE LOCKOUT
IUVLO
UVLO pin current
VUVLO-R
Rising UVLO threshold
IUVLO-HYS
UVLO hysteresis current
VUVLO = 1 V
1.175
1.243
1.311
22
V
µA
ENABLE
IEN
EN pin current
VEN-TH
EN pin threshold
10
VEN rising
VEN falling
nA
1.74
.5
V
VEN-HYS
EN pin hysteresis
420
mV
tEN-R
EN pin rising delay
EN rise - PGATE fall
42
ns
tEN-F
EN pin falling delay
EN fall - PGATE rise
21
ns
(1)
(2)
(3)
6
Typical values represent most likely parametric norms at the conditions specified and are not ensured.
Minimum and maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through
correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Texas Instrument's Average Outgoing Quality
Level (AOQL).
The current sense threshold limits are calculated by averaging the results from the two polarities of the high-side differential amplifier.
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SNVS602L – MARCH 2009 – REVISED JUNE 2016
7.6 Typical Characteristics
250
6.125
248
6.100
VCC (V)
VCST (mV)
TA = 25 °C, VIN = 24 V, and characteristics are identical for LM3409 and LM3409HV unless otherwise specified.
246
244
6.075
6.050
242
-50
-14
22
58
94
6.025
-50
130
-14
TEMPERATURE (°C)
1.255
-5.10
1.250
-5.15
IADJ (#A)
VADJ (V)
-5.05
1.245
-5.25
1.235
-5.30
58
94
130
-5.20
1.240
22
94
Figure 2. VCC vs Junction Temperature
1.260
-14
58
TEMPERATURE (°C)
Figure 1. VCST vs Junction Temperature
1.230
-50
22
-5.35
-50
130
-14
TEMPERATURE (°C)
22
58
94
130
TEMPERATURE (°C)
Figure 3. VADJ vs Junction Temperature
Figure 4. IADJ vs Junction Temperature
1.26
180
160
tON-MIN (ns)
VOFT (V)
1.25
1.24
140
120
100
1.23
80
1.22
-50
-14
22
58
94
130
TEMPERATURE (°C)
Figure 5. VOFT vs Junction Temperature
Copyright © 2009–2016, Texas Instruments Incorporated
60
-50
-14
22
58
94
130
TEMPERATURE (°C)
Figure 6. tON-MIN vs Junction Temperature
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SNVS602L – MARCH 2009 – REVISED JUNE 2016
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Typical Characteristics (continued)
TA = 25 °C, VIN = 24 V, and characteristics are identical for LM3409 and LM3409HV unless otherwise specified.
95
95
EFFICIENCY (%)
100
EFFICIENCY (%)
100
90
85
80
90
85
80
75
75
70
0
10
20
30
40
70
0
50
20
40
60
80
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 7. LM3409 Efficiency vs Input Voltage VO = 17 V (5
LEDs); ILED = 2 A
Figure 8. LM3409HV Efficiency vs Input Voltage VO = 17 V (5
LEDs); ILED = 2 A
2.40
2.5
2.35
2.4
ILED (A)
ILED (A)
2.30
2.25
2.3
2.2
2.20
2.1
2.15
2.10
20
24
28
32
36
40
2.0
20
44
32
INPUT VOLTAGE (V)
68
80
Figure 10. LM3409HV LED Current vs Input Voltage VO = 17
V (5 LEDs)
1.7
2.3
1.4
1.8
1 LED
1.0
ILED (A)
NORMALIZED SWITCHING FREQUENCY
56
INPUT VOLTAGE (V)
Figure 9. LM3409 LED Current vs Input Voltage VO = 17 V (5
LEDs)
0.7
1.4
0.9
3 LEDs
0.3
0.5
7 LEDs
0.0
0
5 LEDs
14
28
42
56
70
INPUT VOLTAGE (V)
Figure 11. Normalized Switching Frequency vs Input
Voltage
8
44
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0.0
0.0
0.3
0.5
0.8
1.0
1.3
VADJ (V)
Figure 12. Amplitude Dimming Using IADJ Pin VO = 17 V (5
LEDs); VIN = 24 V
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SNVS602L – MARCH 2009 – REVISED JUNE 2016
Typical Characteristics (continued)
TA = 25 °C, VIN = 24 V, and characteristics are identical for LM3409 and LM3409HV unless otherwise specified.
2.3
2.3
1.8
1.8
20kHz
100 kHz
1.4
ILED (A)
0.9
0.9
1kHz
50 kHz
0.5
20
40
60
80
0.0
0
100
20
DUTY CYCLE (%)
VEN
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
ILED (A)
ILED
14
12
10
8
6
4
2
0
-2
ILED
VPWM2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
-0.4
ILED (A)
VEN (V)
Figure 15. 20 kHz 50% EN Pin PWM Dimming VO = 42 V (12
LEDs); VIN = 48 V
ILED
100
2.0
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
NOTE: The waveforms were acquired using the standard evaluation
board from AN-1953 (SNVA390).
Figure 16. 100 kHz 50% External FET PWM Dimming VO = 42
V (12 LEDs); VIN = 48 V
VPWM2 (V)
NOTE: The waveforms were acquired using the standard evaluation
board from AN-1953 (SNVA390).
VEN
80
2 és/DIV
10 és/DIV
7
6
5
4
3
2
1
0
-1
60
Figure 14. External Parallel FET PWM Dimming VO = 17 V (5
LEDs); VIN = 24 V
VPWM2 (V)
VEN (V)
Figure 13. Internal EN Pin PWM Dimming VO = 17 V (5
LEDs); VIN = 24 V
14
12
10
8
6
4
2
0
-2
40
DUTY CYCLE (%)
ILED (A)
0.0
0
0.5
7
6
5
4
3
2
1
0
-1
VPWM2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
-0.4
ILED
ILED (A)
ILED (A)
1.4
3.5 és
2 és/DIV
NOTE: The waveforms were acquired using the standard evaluation
board from AN-1953 (SNVA390).
Figure 17. 20 kHz 50% EN Pin PWM Dimming (Rising Edge)
VO = 42 V (12 LEDs); VIN = 48 V
Copyright © 2009–2016, Texas Instruments Incorporated
200 ns/DIV
The waveforms were acquired using the standard evaluation board
from AN-1953 (SNVA390).
Figure 18. 100 kHz 50% External FET PWM Dimming (Rising
Edge) VO = 42 V (12 LEDs); VIN = 48 V
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8 Detailed Description
8.1 Overview
The LM3409/09HV are P-channel MOSFET (PFET) controllers for step-down (buck) current regulators which are
ideal for driving LED loads. They have wide input voltage range allowing for regulation of a variety of LED loads.
The high-side differential current sense, with low adjustable threshold voltage, provides an excellent method for
regulating output current while maintaining high system efficiency.
The LM3409/09HV uses a Controlled Off-Time (COFT) architecture that allows the converter to be operated in
both continuous conduction mode (CCM) and discontinuous conduction mode (DCM) with no external control
loop compensation, while providing an inherent cycle-by-cycle current limit. The adjustable current sense
threshold provides the capability to amplitude (analog) dim the LED current over the full range and the fast output
enable/disable function allows for high frequency PWM dimming using no external components.
When designing, the maximum attainable LED current is not internally limited because the LM3409/09HV is a
controller. Instead it is a function of the system operating point, component choices, and switching frequency
allowing the LM3409/09HV to easily provide constant currents up to 5A. This simple controller contains all the
features necessary to implement a high-efficiency versatile LED driver.
8.2 Functional Block Diagram
VCC
REGULATOR
VIN
VCC
VIN
OFF TIMER
COFF
Complete
COFF
VCC
UVLO
THERMAL
SHUTDOWN
PGATE
Start
VCC
EN
R
CSN
+
LOGIC
CSP
R
22 µA
5 µA
1.24 V
+
UVLO
+
-
IADJ
1.24 V
GND
5R
10
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SNVS602L – MARCH 2009 – REVISED JUNE 2016
8.3 Feature Description
8.3.1 Buck Current Regulators
The buck regulator is unique among non-isolated topologies due to the direct connection of the inductor to the
load during the entire switching cycle. An inductor will control the rate of change of current that flows through it,
therefore a direct connection to the load is excellent for current regulation. A buck current regulator, using the
LM3409/09HV, is shown in the Application and Implementation section. During the time that the PFET (Q1) is
turned on (tON), the input voltage charges up the inductor (L1). When Q1 is turned off (tOFF), the re-circulating
diode (D1) becomes forward biased and L1 discharges. During both intervals, the current is supplied to the load
keeping the LEDs forward biased. Figure 19 shows the inductor current (iL(t)) waveform for a buck converter
operating in CCM.
The average inductor current (IL) is equal to the average output LED current (ILED), therefore if IL is tightly
controlled, ILED will be well regulated. As the system changes input voltage or output voltage, duty cycle (D) is
varied to regulate IL and ultimately ILED. For any buck regulator, D is simply the conversion ratio divided by the
efficiency (η):
D=
VO
x VIN
(1)
iL (t)
IL-MAX
üiL-
IL
PP
IL-MIN
0
tON = DTS
tOFF = (1-D)TS
t
TS
Figure 19. Ideal CCM Buck Converter Inductor Current iL(t)
8.3.2 Controlled Off-Time (COFT) Architecture
The COFT architecture is used by the LM3409/09HV to control ILED. It is a combination of peak current detection
and a one-shot off-timer that varies with output voltage. D is indirectly controlled by changes in both tOFF and tON,
which vary depending on the operating point. This creates a variable switching frequency over the entire
operating range. This type of hysteretic control eliminates the need for control loop compensation necessary in
many switching regulators, simplifying the design process and providing fast transient response.
8.3.2.1 Adjustable Peak Current Control
At the beginning of a switching period, PFET Q1 is turned on and inductor current increases. Once peak current
is detected, Q1 is turned off, the diode D1 forward biases, and inductor current decreases. Figure 20 shows how
peak current detection is accomplished using the differential voltage signal created as current flows through the
current setting resistor (RSNS). The voltage across RSNS (VSNS) is compared to the adjustable current sense
threshold (VCST) and Q1 is turned off when VSNS exceeds VCST, providing that tON is greater than the minimum
possible tON (typically 115ns).
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Feature Description (continued)
V IN
LM3409/09HV
R
CSP
+
V CST
+
+
R SNS
-
t ON
ENDS
-
VSNS
CSN
R
IT
PGATE
5V
Q1
L1
IL
LED+
5 µA
IADJ
+
-
+
1.24 V
VADJ
-
R EXT
Optional
D1
LED-
GND
5R
Figure 20. Peak Current Control Circuit
There are three different methods to set the current sense threshold (VCST) using the multi-function IADJ pin:
1. IADJ pin left open: 5 µA internal current source biases the Zener diode and clamps the IADJ pin voltage
(VADJ) at 1.24 V causing the maximum threshold voltage:
V
V
VCST = ADJ x R = ADJ = 1.24V = 248 mV
5xR
5
5
(2)
2. External voltage (VADJ) of 0 V to 1.24 V: Apply to the IADJ pin to adjust VCST from 0V to 248mV. If the VADJ
voltage is adjustable, analog dimming can be achieved.
3. External resistor (REXT) placed from IADJ pin to ground: 5 µA current source sets the VADJ voltage and
corresponding threshold voltage:
V
5#A x REXT
VCST = ADJ =
= 1#A x REXT
5
5
(3)
8.3.2.2 Controlled Off-Time
Once Q1 is turned off, it remains off for a constant time (tOFF) which is preset by an external resistor (ROFF), an
external capacitor (COFF), and the output voltage (VO) as shown in Figure 21. Because ILED is tightly regulated,
VO will remain nearly constant over widely varying input voltage and temperature yielding a nearly constant tOFF.
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Feature Description (continued)
VO
LM3409/09HV
+
tOFF
Control
Logic
-
to
PGATE
Drive
ROFF
COFF
1.24 V
COFF
+
vCOFF
-
Figure 21. Off-Time Control Circuit
At the start of tOFF, the voltage across COFF (vCOFF(t)) is zero and the capacitor begins charging according to the
time constant provided by ROFF and COFF. When vCOFF(t) reaches the off-time threshold (VOFT = 1.24 V), then the
off-time is terminated and vCOFF(t) is reset to zero. tOFF is calculated as follows:
·
§
t OFF = - R OFF x (COFF + 20 pF) x ln ¨¨1 - 1.24V¸¸
VO ¹
©
(4)
In reality, there is typically 20 pF parasitic capacitance at the off-timer pin in parallel with COFF, which is
accounted for in the calculation of tOFF. Also, it should be noted that the tOFF equation has a preceding negative
sign because the result of the logarithm should be negative for a properly designed circuit. The resulting tOFF is a
positive value as long as VO > 1.24 V. If VO < 1.24 V, the off-timer cannot reach VOFT and an internally limited
maximum off-time (typically 300 µs) will occur.
vCOFF(t)
VO
dvCOFF
dt
1.24
t
0
tOFF
ROFF x COFF
Figure 22. Exponential Charging Function vCOFF(t)
Although the tOFF equation is non-linear, tOFF is actually very linear in most applications. Ignoring the 20-pF
parasitic capacitance at the COFF pin, vCOFF(t) is plotted in Figure 22. The time derivative of vCOFF(t) can be
calculated to find a linear approximation to the tOFF equation:
æ
ö
tOFF
-ç
÷
dv COFF (t)
VO
è ROFF ´COFF ø
dt
=
ROFF ´ COFF
e
(5)
When tOFF > 1.24V), the slope of the function is essentially linear and
tOFF can be approximated as a current source charging COFF:
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Feature Description (continued)
t OFF |
1. 24V x R OFF x COFF
VO
(6)
Using the actual tOFF equation, the inductor current ripple (ΔiL-PP) of a buck current regulator operating in CCM is:
§ 1. 24V ·
¸
- VO x R OFF x (COFF + 20 pF) x ln ¨¨1 VO ¸¹
©
' iL - PP =
L1
(7)
Using the tOFF approximation, the equation is reduced to:
'iL - PP |
1. 24 x ROFF x COFF
L1
(8)
NOTE
ΔiL-PP is independent of both VIN and VO when in CCM.
The ΔiL-PP approximation only depends on ROFF, COFF, and L1, therefore the ripple is essentially constant over
the operating range as long as VO >> 1.24V (when the tOFF approximation is valid). An exception to the tOFF
approximation occurs if the IADJ pin is used to analog dim. As the LED/inductor current decreases, the converter
will eventually enter DCM and the ripple will decrease with the peak current threshold. The approximation shows
how the LM3409/09HV achieves constant ripple over a wide operating range, however tOFF should be calculated
using the actual equation first presented.
8.3.3 Average LED Current
For a buck converter, the average LED current is simply the average inductor current.
vSNS (t)
VCST
0
tON
tOFF
t
Figure 23. Sense Voltage vSNS(t)
Using the COFT architecture, the peak transistor current (IT-MAX) is sensed as shown in Figure 23, which is equal
to the peak inductor current (IL-MAX) given by the following equation:
V
VADJ
IL- MAX = IT - MAX = CST =
RSNS 5 x RSNS
(9)
Because IL-MAX is set using peak current control and ΔiL-PP is set using the controlled off-timer, IL and
correspondingly ILED can be calculated as follows:
ILED = IL = IL - MAX -
14
V xt
VADJ
'iL - PP
- O OFF
=
5 x RSNS
2 x L1
2
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Feature Description (continued)
The threshold voltage VCST seen by the high-side sense comparator is affected by the comparator’s input offset
voltage, which causes an error in the calculation of IL-MAX and ultimately ILED. To mitigate this problem, the
polarity of the comparator inputs is swapped every cycle, which causes the actual IL-MAX to alternate between two
peak values (IL-MAXH and IL-MAXL), equidistant from the theoretical IL-MAX as shown in Figure 24. ILED remains
accurate through this averaging.
iL(t)
IL-MAX-H
IL-MAX
IL-MAX-L
0
0
tOFF
t
tOFF
Figure 24. Inductor Current iL(t) Showing IL-MAX Offset
8.3.4 Inductor Current Ripple
Because the LM3409/09HV swaps the polarity of the differential current sense comparator every cycle, a
minimum inductor current ripple (ΔiL-PP) is necessary to maintain accurate ILED regulation. Referring to Figure 24,
the first tON is terminated at the higher of the two polarity-swapped thresholds (corresponding to IL-MAXH). During
the following tOFF, iL decreases until the second tON begins. If tOFF is too short, then as the second tON begins, iL
will still be above the lower peak current threshold (corresponding to IL-MAXL) and a minimum tON pulse will follow.
This will result in degraded ILED regulation. The minimum inductor current ripple (ΔiL-PP-MIN) should adhere to the
following equation to ensure accurate ILED regulation:
24 mV
'iL - PP - MIN >
RSNS
(11)
8.3.5 Switching Frequency
The switching frequency is dependent upon the actual operating point (VIN and VO). VO will remain relatively
constant for a given application, therefore the switching frequency will vary with VIN (frequency increases as VIN
increases). The target switching frequency (fSW) at the nominal operating point is selected based on the tradeoffs
between efficiency (better at low frequency) and solution size/cost (smaller at high frequency). The off-time of the
LM3409/09HV can be programmed for switching frequencies up to 5 MHz (theoretical limit imposed by minimum
tON). In practice, switching frequencies higher than 1MHz may be difficult to obtain due to gate drive limitations,
high input voltage, and thermal considerations.
At CCM operating points, fSW is defined as:
§ V ·
1 - ¨¨ O ¸¸
©K x VIN ¹
1- D
fSW =
=
t OFF
t OFF
(12)
At DCM operating points, fSW is defined as:
fSW =
1
1
=
t ON + tOFF §IL - MAX x L1·
¸¸ + t OFF
¨
© VIN - VO ¹
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Feature Description (continued)
In the CCM equation, it is apparent that the efficiency (η) factors into the switching frequency calculation.
Efficiency is hard to estimate and, because switching frequency varies with input voltage, accuracy in setting the
nominal switching frequency is not critical. Therefore, a general rule of thumb for the LM3409/09HV is to assume
an efficiency between 85% and 100%. When approximating efficiency to target a nominal switching frequency,
the following condition must be met:
VO
>
VIN
(14)
iLED (t)
ILED-MAX
ILED
IDIM-LED
DDIM x TDIM
t
0
TDIM
tOFF
Figure 25. LED Current iLED(t) During EN Pin PWM Dimming
8.3.6 PWM Dimming Using the EN Pin
The enable pin (EN) is a TTL compatible input for PWM dimming of the LED. A logic low (below 0.5V) at EN will
disable the internal driver and shut off the current flow to the LED array. While the EN pin is in a logic low state
the support circuitry (driver, bandgap, VCC regulator) remains active to minimize the time needed to turn the LED
array back on when the EN pin sees a logic high (above 1.74 V).
Figure 25 shows the LED current (iLED(t)) during PWM dimming where duty cycle (DDIM) is the percentage of the
dimming period (TDIM) that the PFET is switching. For the remainder of TDIM, the PFET is disabled. The resulting
dimmed average LED current (IDIM-LED) is:
IDIM- LED = DDIM x ILED
(15)
The LED current rise and fall times (which are limited by the slew rate of the inductor as well as the delay from
activation of the EN pin to the response of the external PFET) limit the achievable TDIM and DDIM. In general,
dimming frequency should be at least one order of magnitude lower than the steady state switching frequency to
prevent aliasing. However, for good linear response across the entire dimming range, the dimming frequency
may need to be even lower.
8.3.7 High Voltage Negative BIAS Regulator
The LM3409/09HV contains an internal linear regulator where the steady state VCC pin voltage is typically 6.2 V
below the voltage at the VIN pin. The VCC pin should be bypassed to the VIN pin with at least 1µF of ceramic
capacitance connected as close as possible to the IC.
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Feature Description (continued)
8.3.8 External Parallel FET PWM Dimming
iLED (t)
ILED-MAX
ILED
IDIM-LED
DDIM x TDIM
t
0
tOFF
TDIM
Figure 26. Ideal LED Current iLED(t) During Parallel FET Dimming
Any buck topology LED driver is a good candidate for parallel FET dimming because high slew rates are
achievable, due to the fact that no output capacitance is required. This allows for much higher dimming
frequencies than are achievable using the EN pin. When using external parallel FET dimming, a situation can
arise where maximum off-time occurs due to a shorted output. To mitigate this situation, a secondary voltage
(VDD) should be used as shown in Figure 27.
VDD
LM3409/09HV
ROFF2
ROFF1
COFF
COFF
ILED
VDD
Dim
FET
PWM
Gate
Driver
Figure 27. External Parallel FET Dimming Circuit
A small diode is connected in series with the off time resistor calculated for nominal operation from the output,
ROFF1. Then connect a small diode from the secondary voltage along with another resistor, ROFF2. The secondary
voltage can be any voltage as long as it is greater than 2V. The value of ROFF2 can be calculated using
Equation 16.
ROFF2 =
ROFF1 × VDD
ILED × RDS (on )
(16)
The ideal LED current waveform iLED(t) during parallel FET PWM dimming is very similar to the EN pin PWM
dimming shown previously. The LED current does not rise and fall infinitely fast as shown in Figure 26 however
with this method, only the speed of the parallel Dim FET ultimately limits the dimming frequency and dimming
duty cycle. This allows for much faster PWM dimming than can be attained with the EN pin.
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8.4 Device Functional Modes
8.4.1 Low-Power Shutdown
The LM3409/09HV can be placed into a low-power shutdown (typically 110 µA) by grounding the EN terminal
(any voltage below 0.5 V) until VCC drops below the VCC UVLO threshold (typically 3.73 V). During normal
operation this terminal should be tied to a voltage above 1.74 V and below absolute maximum input voltage
rating.
8.4.2 Thermal Shutdown
Internal thermal shutdown circuitry is provided to protect the IC in the event that the maximum junction
temperature is exceeded. The threshold for thermal shutdown is 160°C with 15°C of hysteresis (both values
typical). During thermal shutdown the PFET and driver are disabled.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Input Undervoltage Lockout (UVLO)
Undervoltage lockout is set with a resistor divider from VIN to GND and is compared against a 1.24V threshold as
shown in Figure 28. Once the input voltage is above the preset UVLO rising threshold (and assuming the part is
enabled), the internal circuitry becomes active and a 22µA current source at the UVLO pin is turned on. This
extra current provides hysteresis to create a lower UVLO falling threshold. The resistor divider is chosen to set
both the UVLO rising and falling thresholds.
LM3409/09HV
VIN
22 µA
RUV2
+
-
ON/OFF
UVLO
1.24 V
RUV1
Figure 28. UVLO Circuit
The turn-on threshold (VTURN-ON) is defined as follows:
VTURN-ON =
1. 24V x (RUV1 + RUV2)
RUV1
(17)
The hysteresis (VHYS) is defined as follows:
VHYS = RUV2 x 22 PA
(18)
9.1.2 Operation Near Dropout
Because the power MOSFET is a PFET, the LM3409/09HV can be operated into dropout which occurs when the
input voltage is approximately equal to output voltage. Once the input voltage drops below the nominal output
voltage, the switch remains constantly on (D=1) causing the output voltage to decrease with the input voltage. In
normal operation, the average LED current is regulated to the peak current threshold minus half of the ripple. As
the converter goes into dropout, the LED current is exactly at the peak current threshold because it is no longer
switching. This causes the LED current to increase by half of the set ripple current as it makes the transition into
dropout. Therefore, the inductor current ripple should be kept as small as possible (while remaining above the
previously established minimum) and output capacitance should be added to help maintain good line regulation
when approaching dropout.
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Application Information (continued)
9.1.3 LED Ripple Current
Selection of the ripple current through the LED array is analogous to the selection of output ripple voltage in a
standard voltage regulator. Where the output voltage ripple in a voltage regulator is commonly ±1% to ±5% of the
DC output voltage, LED manufacturers generally recommend values for ΔiLED-PP ranging from ±5% to ±20% of
ILED. For a nominal system operating point, a larger ΔiLED-PP specification can reduce the necessary inductor size
and/or allow for smaller output capacitors (or no output capacitors at all) which helps to minimize the total
solution size and cost. On the other hand, a smaller ΔiLED-PP specification would require more output inductance,
a higher switching frequency, or additional output capacitance.
9.1.4 Buck Converters without Output Capacitors
Because current is being regulated, not voltage, a buck current regulator is free of load current transients,
therefore output capacitance is not needed to supply the load and maintain output voltage. This is very helpful
when high frequency PWM dimming the LED load. When no output capacitor is used, the same design equations
that govern ΔiL-PP also apply to ΔiLED-PP.
9.1.5 Buck Converters With Output Capacitors
A capacitor placed in parallel with the LED load can be used to reduce ΔiLED-PP while keeping the same average
current through both the inductor and the LED array. With an output capacitor, the inductance can be lowered,
making the magnetics smaller and less expensive. Alternatively, the circuit can be run at lower frequency with the
same inductor value, improving the efficiency and increasing the maximum allowable average output voltage. A
parallel output capacitor is also useful in applications where the inductor or input voltage tolerance is poor.
Adding a capacitor that reduces ΔiLED-PP to well below the target provides headroom for changes in inductance or
VIN that might otherwise push the maximum ΔiLED-PP too high.
Figure 29. Calculating Dynamic Resistance rD
Output capacitance (CO) is determined knowing the desired ΔiLED-PP and the LED dynamic resistance (rD). rD can
be calculated as the slope of the LED’s exponential DC characteristic at the nominal operating point as shown in
Figure 29. Simply dividing the forward voltage by the forward current at the nominal operating point will give an
incorrect value that is 5x to 10x too high. Total dynamic resistance for a string of n LEDs connected in series can
be calculated as the rD of one device multiplied by n. The following equations can then be used to estimate ΔiLEDPP when using a parallel capacitor:
'i
'iLED- PP = L - PP
rD
1+
ZC
(19)
1
ZC =
2 x S x fSW x CO
20
(20)
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Application Information (continued)
In general, ZC should be at least half of rD to effectively reduce the ripple. Ceramic capacitors are the best choice
for the output capacitors due to their high ripple current rating, low ESR, low cost, and small size compared to
other types. When selecting a ceramic capacitor, special attention must be paid to the operating conditions of the
application. Ceramic capacitors can lose one-half or more of their capacitance at their rated DC voltage bias and
also lose capacitance with extremes in temperature. Make sure to check any recommended de-ratings and also
verify if there is any significant change in capacitance at the operating voltage and temperature.
9.1.6 Output Overvoltage Protection
Because the LM3409/09HV controls a buck current regulator, there is no inherent need to provide output
overvoltage protection. If the LED load is opened, the output voltage will only rise as high as the input voltage
plus any ringing due to the parasitic inductance and capacitance present at the output node. If a ceramic output
capacitor is used in the application, it should have a minimum rating equal to the input voltage. Ringing seen at
the output node should not damage most ceramic capacitors, due to their high ripple current rating.
9.1.7 Input Capacitors
Input capacitors are selected using requirements for minimum capacitance and RMS ripple current. The PFET
current during tON is approximately ILED, therefore the input capacitors discharge the difference between ILED and
the average input current (IIN) during tON. During tOFF, the input voltage source charges up the input capacitors
with IIN. The minimum input capacitance (CIN-MIN) is selected using the maximum input voltage ripple (ΔvIN-MAX)
which can be tolerated. ΔvIN-MAX is equal to the change in voltage across CIN during tON when it supplies the load
current. A good starting point for selection of CIN is to use ΔvIN-MAX of 2% to 10% of VIN. CIN-MIN can be selected
as follows:
CIN - MIN =
ILED x t ON
'vIN - MAX
·
§1
- t OFF¸¸
ILED x ¨¨
¹
©fSW
=
'vIN - MAX
(21)
An input capacitance at least 75% greater than the calculated CIN-MIN value is recommended. To determine the
RMS input current rating (IIN-RMS) the following approximation can be used:
IIN - RMS = ILED x D x (1 - D) = ILED x fSW x t ON x t OFF
(22)
Because this approximation assumes there is no inductor ripple current, the value should be increased by 1030% depending on the amount of ripple that is expected. Ceramic capacitors are the best choice for input
capacitors for the same reasons mentioned in the Buck Converters With Output Capacitors section. Careful
selection of the capacitor requires checking capacitance ratings at the nominal operating voltage and
temperature.
9.1.8 P-Channel MOSFET (PFET)
The LM3409/09HV requires an external PFET (Q1) as the main power MOSFET for the switching regulator. Q1
should have a voltage rating at least 15% higher than the maximum input voltage to ensure safe operation during
the ringing of the switch node. In practice all switching converters have some ringing at the switch node due to
the diode parasitic capacitance and the lead inductance. The PFET should also have a current rating at least
10% higher than the average transistor current (IT):
IT = D x ILED
(23)
The power rating is verified by calculating the power loss (PT) using the RMS transistor current (IT-RMS) and the
PFET on-resistance (RDS-ON):
2·
§
1 § 'i ·
IT- RMS = ILED x D x ¨¨1+ x ¨¨ L-PP ¸¸ ¸¸
¨ 12 © ILED ¹ ¸
©
¹
(24)
2
PT = IT- RMS x R DSON
(25)
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Application Information (continued)
It is important to consider the gate charge of Q1. As the input voltage increases from a nominal voltage to its
maximum input voltage, the COFT architecture will naturally increase the switching frequency. The dominant
switching losses are determined by input voltage, switching frequency, and PFET total gate charge (Qg). The
LM3409/09HV must provide and remove charge Qg from the input capacitance of Q1 to turn it on and off. This
occurs more often at higher switching frequencies which requires more current from the internal regulator,
thereby increasing internal power dissipation and eventually causing the LM3409/09HV to thermally cycle. For a
given range of operating points the only effective way to reduce these switching losses is to minimize Qg.
A good rule of thumb is to limit Qg < 30nC (if the switching frequency remains below 300kHz for the entire
operating range then a larger Qg can be considered). If a PFET with small RDS-ON and a high voltage rating is
required, there may be no choice but to use a PFET with Qg > 30nC.
When using a PFET with Qg > 30nC, the bypass capacitor (CF) should not be connected to the VIN pin. This will
ensure that peak current detection through RSNS is not affected by the charging of the PFET input capacitance
during switching, which can cause false triggering of the peak detection comparator. Instead, CF should be
connected from the VCC pin to the CSN pin which will cause a small DC offset in VCST and ultimately ILED,
however it avoids the problematic false triggering.
In general, the PFET should be chosen to meet the Qg specification whenever possible, while minimizing RDS-ON.
This will minimize power losses while ensuring the part functions correctly over the full operating range.
9.1.9 Re-Circulating Diode
A re-circulating diode (D1) is required to carry the inductor current during tOFF. The most efficient choice for D1 is
a Schottky diode due to low forward voltage drop and near-zero reverse recovery time. Similar to Q1, D1 must
have a voltage rating at least 15% higher than the maximum input voltage to ensure safe operation during the
ringing of the switch node and a current rating at least 10% higher than the average diode current (ID):
ID = (1- D) x ILED
(26)
The power rating is verified by calculating the power loss through the diode. This is accomplished by checking
the typical diode forward voltage (VD) from the I-V curve on the product data sheet and calculating as follows:
PD = ID x VD
(27)
In general, higher current diodes have a lower VD and come in better performing packages minimizing both
power losses and temperature rise.
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SNVS602L – MARCH 2009 – REVISED JUNE 2016
9.2 Typical Applications
9.2.1 EN PIN PWM Dimming Application for 10 LEDs
RUV2
RUV1
1
VIN
UVLO
10
VIN = 48 V
CF
2
3
PWM
VCC
IADJ
EN
LM3409HV
CSP
CIN1
CIN2
9
VO = 35 V
8
RSNS
ROFF
4
COFF
COFF
CSN
7
ILED = 2 A
DAP
5
GND
PGATE
6
Q1
L1
D1
Figure 30. EN PIN PWM Dimming Application for 10 LEDs Schematic
9.2.1.1 Design Requirements
fSW = 525 kHz
VIN = 48 V; VIN-MAX = 75 V
VO = 35 V
ILED = 2 A
ΔiLED-PP = ΔiL-PP = 1 A
ΔvIN-PP = 1.44 V
VTURN-ON = 10 V; VHYS = 1.1 V
η = 0.95
9.2.1.2 Detailed Design Procedure
Table 1. Design 1 Bill of Materials
QTY
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
1
LM3409HV/LM3409QHV
Buck controller
TI
LM3409HVMY/LM3409QHVMY
2
CIN1, CIN2
2 µF X7R 10% 100 V
MURATA
GRM43ER72A225KA01L
1
CF
1 µF X7R 10% 16 V
TDK
C1608X7R1C105K
1
COFF
470 pF X7R 10% 50 V
TDK
C1608X7R1H471K
1
Q1
PMOS 100 V 3.8 A
ZETEX
ZXMP10A18KTC
1
D1
Schottky 100 V 3 A
VISHAY
SS3H10-E3/57T
1
L1
15 µH 20% 4.2 A
TDK
SLF12565T-150M4R2
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Typical Applications (continued)
Table 1. Design 1 Bill of Materials (continued)
QTY
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
1
ROFF
24.9 kΩ 1%
VISHAY
CRCW060324K9FKEA
1
RUV1
6.98 kΩ 1%
VISHAY
CRCW06036K98FKEA
1
RUV2
49.9 kΩ 1%
VISHAY
CRCW060349K9FKEA
1
RSNS
0.1 Ω 1% 1W
VISHAY
WSL2512R1000FEA
9.2.1.2.1 Nominal Switching Frequency
Assume COFF = 470 pF and η = 0.95. Solve for ROFF:
ROFF =
§
VO ·
¸
- ¨¨1K
x
VIN ¸¹
©
§ 1.24V·
¸
(COFF + 20 pF) x fSW x ln ¨¨1¸
© VO ¹
§
35V ·
- ¨1¸
0
.
95
x 48V¹
©
ROFF =
= 25.1 k:
§ 1.24V·
490 pF x 525 kHz x ln ¨1¸
© 35V ¹
(28)
The closest 1% tolerance resistor is 24.9 kΩ; therefore, the actual tOFF and target fSW are:
§ 1.24V·
¸
t OFF = - (COFF + 20 pF) x ROFF x ln ¨¨1VO ¸¹
©
§ 1.24V·
¸¸ = 440 ns
t OFF = - 490 pF x 24.9 k: x ln ¨¨1© 35V ¹
(29)
§ V ·
§
·
1 - ¨¨ O ¸¸ 1 - ¨ 35V ¸
K
x
V
IN ¹
©0.95 x 48V¹ 528 kHz
©
fSW = t
=
=
440 ns
OFF
(30)
The chosen components from step 1 are:
COFF = 470 pF
R OFF = 24.9 k:
(31)
9.2.1.2.2 Inductor Ripple Current
Solve for L1:
L1 =
VO x t OFF 35V x 440 ns
=
= 15.4 PH
'iL - PP
1A
(32)
The closest standard inductor value is 15 µH therefore the actual ΔiL-PP is:
V xt
35V x 440 ns
'iL- PP = O OFF =
= 1.027A
L1
15 PH
(33)
The chosen component from step 2 is:
L1 = 15 PH
24
(34)
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9.2.1.2.3 Average LED Current
Determine IL-MAX:
IL- MAX = ILED +
'iL - PP
1.027A
= 2A +
= 2.51A
2
2
(35)
Assume VADJ = 1.24 V and solve for RSNS:
VADJ
1.24V
RSNS =
=
= 0.099:
5 x IL- MAX 5 x 2.51A
(36)
The closest 1% tolerance resistor is 0.1 Ω therefore the ILED is:
ILED =
VADJ
'i
- L- PP
5 x RSNS
2
ILED =
1.027A
1.24V
= 1.97A
2
5 x 0.099:
(37)
The chosen component from step 3 is:
RSNS = 0.1:
(38)
9.2.1.2.4 Output Capacitance
No output capacitance is necessary.
9.2.1.2.5 Input Capacitance
Determine tON:
1
1
t ON =
- t OFF =
- 440 ns = 1.45 Ps
528 kHz
fSW
(39)
Solve for CIN-MIN:
I xt
1. 97A x 1.45 Ps
CIN - MIN = LED ON =
= 1.98 PF
'vIN - PP
1.44V
(40)
Choose CIN:
CIN = CIN - MIN x 2 = 3.96 PF
(41)
Determine IIN-RMS:
IIN - RMS = ILED x fSW x t ON x t OFF
IIN- RMS = 1.97A x 528 kHz x 1.45 Ps x 440 ns = 831 mA
(42)
The chosen components from step 5 are:
CIN1 = CIN2 = 2.2 PF
(43)
9.2.1.2.6 PFET
Determine minimum Q1 voltage rating and current rating:
VT- MAX = VIN - MAX = 75V
IT = D x ILED =
(44)
VO x ILED 35V x 1.97A
=
= 1.51A
48V x 0.95
VIN x K
(45)
A 100 V, 3.8 A PFET is chosen with RDS-ON = 19 0mΩ and Qg = 20 nC. Determine IT-RMS and PT:
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2·
§
1 § 'i ·
IT- RMS = ILED x D x ¨¨1+ x ¨¨ L-PP ¸¸ ¸¸
¨ 12 © ILED ¹ ¸
©
¹
2
§
1 §1.027A · ·¸
35V
¨
x 1+ x ¨
IT- RMS = 1.97A x
¸
48V x 0.95 ¨ 12 ¨© 1.97A ¸¹ ¸
¹
©
IT- RMS = 1.74A
(46)
2
2
PT = IT- RMS x R DSON = 1.74 A x 190 m: = 577 mW
(47)
The chosen component from step 6 is:
Q1o 3.8 A ,100V, DPAK
(48)
9.2.1.2.7 Diode
Determine minimum D1 voltage rating and current rating:
VD - MAX = VIN - MAX = 75V
(49)
§
VO ·
¸ x ILED
ID = (1- D) x ILED = ¨¨1¸
© VIN x K ¹
§
35V ·
ID = ¨¨1¸ x 1.97A = 457 mA
48
V
x 0.95¸¹
©
(50)
A 100-V, 3-A diode is chosen with VD = 750 mV. Determine PD:
PD = ID x VD = 457 mA x 750 mV = 343 mW
(51)
The chosen component from step 7 is:
D1 o 3 A,100V, SMC
(52)
9.2.1.2.8 Input UVLO
Solve for RUV2:
RUV2 =
VHYS
1.1V 50 k:
=
=
22 PA 22 PA
(53)
The closest 1% tolerance resistor is 49.9 kΩ therefore VHYS is:
VHYS = RUV2 x 22 PA = 49.9 k: x 22 PA = 1.1V
(54)
Solve for RUV1:
RUV1 =
1. 24V x RUV2
1.24V x 49.9 k:
=
= 7.06 k:
10V - 1.24V
VTURN - ON - 1.24V
(55)
The closest 1% tolerance resistor is 6.98 kΩ therefore VTURN-ON is:
VTURN-ON =
VTURN-ON =
26
1. 24V x (RUV1 + RUV2)
RUV1
1. 24V x (6.98 k: + 49.9 k:)
6.98 k:
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= 10.1V
(56)
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SNVS602L – MARCH 2009 – REVISED JUNE 2016
The chosen components from step 8 are:
RUV1 = 6.98 k:
RUV2 = 49.9 k:
(57)
9.2.1.2.9 IADJ Connection Method
The IADJ pin is left open forcing VADJ = 1.24 V.
9.2.1.2.10 PWM Dimming Method
PWM dimming signal pair is applied to the EN pin and GND at fDIM = 1 kHz.
9.2.1.3 Application Curve
Figure 31 shows the LED current versus EN pin PWM duty cycle for the application.
2
1.8
LED Current (A)
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
10
20
30
40
50
60
70
EN Pin Duty Cycle (%)
Black = 200 Hz
Red = 1 kHz
80
90
100
D001
Gray = 20 kHz
Figure 31. EN Pin PWM Dimming
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9.2.2 Analog Dimming Application for 4 LEDs
RUV2
RUV1
1
VIN
UVLO
10
VIN = 24 V
CF
RF2
2
VADJ
VCC
IADJ
CIN1
9
CF2
3
LM3409
EN
CSP
8
RSNS
ROFF
4
COFF
COFF
CSN
VO = 14 V
7
DAP
5
GND
PGATE
6
Q1
ILED = 1 A
L1
D1
CO
9.2.2.1 Design Requirements
fSW = 500 kHz
VIN = 24 V; VIN-MAX = 42 V
VO = 14 V
ILED = 1 A
ΔiL-PP = 450 mA; ΔiLED-PP = 50 mA
ΔvIN-PP = 1 V
VTURN-ON = 10 V; VHYS = 1.1 V
η = 0.90
9.2.2.2 Detailed Design Procedure
Table 2. Design 2 Bill of Materials
QTY
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
1
LM3409/LM3409Q
Buck controller
TI
LM3409MY/LM3409QMY
2
CIN1
4.7-µF X7R 10% 50 V
MURATA
GRM55ER71H475MA01L
28
1
CF
1-µF X7R 10% 16 V
TDK
C1608X7R1C105K
1
CF2
0.1-µF X7R 10% 16 V
TDK
C1608X7R1C104K
1
COFF
470-pF X7R 10% 50 V
TDK
C1608X7R1H471K
1
CO
2.2-µF X7R 10% 50 V
MURATA
GRM43ER71H225MA01L
1
Q1
PMOS 70 V 5.7 A
ZETEX
ZXMP7A17KTC
1
D1
Schottky 60 V 5 A
COMCHIP
CDBC560-G
1
L1
22 µH 20% 4.2 A
TDK
SLF12575T-220M4R0
1
RF2
1 kΩ 1%
VISHAY
CRCW06031K00FKEA
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SNVS602L – MARCH 2009 – REVISED JUNE 2016
Table 2. Design 2 Bill of Materials (continued)
QTY
PART ID
PART VALUE
MANUFACTURER
PART NUMBER
1
ROFF
15.4 kΩ 1%
VISHAY
CRCW060315K4FKEA
1
RUV1
6.98 kΩ 1%
VISHAY
CRCW06036K98FKEA
1
RUV2
49.9 kΩ 1%
VISHAY
CRCW060349K9FKEA
1
RSNS
0.2 Ω 1% 1W
VISHAY
WSL2512R2000FEA
9.2.2.2.1 Nominal Switching Frequency
Assume COFF = 470 pF and η = 0.90. Solve for ROFF:
§
VO ·
- ¨¨1 ¸¸
© K x VIN ¹
ROFF =
§ 1.24V·
¸
COFF + 20 pF x fSW x ln ¨¨1 VO ¸¹
©
§
14V ·
- ¨1 ¸
0
.
90
x 24V¹
©
ROFF =
= 15.5 k:
§ 1. 24V·
490 pF x 500 kHz x ln ¨1¸
© 14V ¹
(58)
The closest 1% tolerance resistor is 15.4 kΩ; therefore, the actual tOFF and target fSW are:
§ 1.24V·
¸
t OFF = - (COFF + 20 pF) x R OFF x ln ¨¨1VO ¸¹
©
§ 1.24V ·
t OFF = - 490 pF x 15.4 k: x ln ¨¨1¸¸ = 700 ns
© 14V ¹
(59)
§ VO ·
¸ 1- §¨ 14V ·¸
1- ¨¨
¸
K
x
V
IN ¹
©
©0. 90 x 24V¹
fSW =
= 503 kHz
=
700 ns
t OFF
(60)
The chosen components from step 1 are:
COFF = 470 pF
R OFF = 15.4 k:
(61)
9.2.2.2.2 Inductor Ripple Current
Solve for L1:
L1 =
VO x t OFF 14V x 700 ns
=
= 21.8 PH
'iL - PP
450 mA
(62)
The closest standard inductor value is 22 µH; therefore, the actual ΔiL-PP is:
'iL - PP =
VO x t OFF
L1
=
14V x 700 ns
= 445 mA
22 PH
(63)
The chosen component from step 2 is:
L1 = 22 PH
(64)
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9.2.2.2.3 Average LED Current
Determine IL-MAX:
IL - MAX = ILED +
'iL - PP
445 mA
= 1A +
= 1. 22 A
2
2
(65)
Assume VADJ = 1.24 V and solve for RSNS:
VADJ
1.24V
RSNS =
=
= 0.203:
5 x IL - MAX 5 x 1.22A
(66)
The closest 1% tolerance resistor is 0.2 Ω therefore ILED is:
'i
VADJ
1.24V
445 mA
ILED =
- L - PP =
= 1.02 A
2
5 x RSNS
2
5 x 0.2:
(67)
The chosen component from step 3 is:
RSNS = 0.2:
(68)
9.2.2.2.4 Output Capacitance
Assume rD = 2 Ω and determine ZC:
r x 'iLED- PP
2: x 50 mA
ZC = D
=
= 250 m:
'iL- PP - 'iLED- PP 450 mA - 50 mA
(69)
Solve for CO-MIN and :
1
2 x S x fSW x Z C
CO - MIN =
CO - MIN =
1
2 x S x 503 kHz x 250 m:
= 1.27 PF
(70)
Choose CO:
CO = CO- MIN x 1.75 = 2.2 PF
(71)
The chosen component from step 5 is:
CO = 2.2 PF
(72)
9.2.2.2.5 Input Capacitance
Determine tON:
t ON =
1
fSW
- t OFF =
1
- 700 ns = 1.29 Ps
503 kHz
(73)
Solve for CIN-MIN:
I xt
1.02A x 1.29 Ps
CIN - MIN = LED ON =
= 1.82 PF
'vIN- PP
720 mV
(74)
Choose CIN:
CIN = CIN - MIN x 2 = 3.64 PF
(75)
Determine IIN-RMS:
30
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IIN- RMS = ILED x fSW x t ON x t OFF
IIN- RMS = 1.02A x 503 kHz x 1. 29 Ps x 700 ns = 486 mA
(76)
The chosen component from step 5 is:
CIN = 4.7 PF
(77)
9.2.2.2.6 PFET
Determine minimum Q1 voltage rating and current rating:
VT- MAX = VIN - MAX = 42V
IT = D x ILED =
(78)
VO x ILED 14V x 1.02A
=
= 660 mA
VIN x K
24V x 0.90
(79)
A 70V, 5.7 A PFET is chosen with RDS-ON = 190 mΩ and Qg = 20 nC. Determine IT-RMS and PT:
2·
§
1 § 'i ·
IT- RMS = ILED x D x ¨¨1+ x ¨¨ L-PP ¸¸ ¸¸
¨ 12 © ILED ¹ ¸
©
¹
§ 1 §445 mA·2·
14V
x ¨1+ x ¨
¸¸
IT- RMS = 1.02A x
24V x 0.90 ¨ 12 ¨© 1.02A ¸¹ ¸
¹
©
IT- RMS = 830 mA
2
PT = IT- RMS
(80)
2
x RDSON = 830 mA x190 m: = 129 mW
(81)
The chosen component from step 6 is:
Q1o 5.7A, 70V, DPAK
(82)
9.2.2.2.7 Diode
Determine minimum D1 voltage rating and current rating:
VD- MAX = VIN - MAX = 42V
(83)
VO ·
§
¸ x ILED
ID = (1- D) x ILED = ¨¨1¸
© VIN xK ¹
14V ·
§
¸ x 1.02A = 358 mA
ID = ¨1© 24V x 0.90¹
(84)
A 60 V, 5 A diode is chosen with VD = 750 mV. Determine PD:
PD = ID x VD = 358 mA x 750 mV = 268 mW
(85)
The chosen component from step 7 is:
D1 o 5A, 60V, SMC
(86)
9.2.2.2.8 Input UVLO
Solve for RUV2:
RUV2 =
VHYS
1.1V 50 k:
=
=
22 PA 22 PA
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(87)
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The closest 1% tolerance resistor is 49.9 kΩ therefore VHYS is:
VHYS = RUV2 x 22 PA = 49.9 k: x 22 PA = 1.1V
(88)
Solve for RUV1:
RUV1 =
1. 24V x RUV2
1.24V x 49.9 k:
=
= 7.06 k:
10V - 1.24V
VTURN - ON - 1.24V
(89)
The closest 1% tolerance resistor is 6.98 kΩ therefore VTURN-ON is:
VTURN-ON =
VTURN-ON =
1. 24V x (RUV1 + RUV2)
RUV1
1. 24V x (6.98 k: + 49.9 k:)
6.98 k:
= 10.1V
(90)
The chosen components from step 8 are:
RUV1 = 6.98 k:
RUV2 = 49.9 k:
(91)
9.2.2.2.9 IADJ Connection Method
The IADJ pin is connected to an external voltage source and varied from 0 – 1.24 V to dim. An RC filter (RF2 = 1
kΩ and CF2 = 0.1 µF) is used as recommended.
9.2.2.2.10 PWM Dimming Method
No PWM dimming is necessary.
9.2.2.3 Application Curve
Figure 32 shows the LED current versus IADJ voltage for the application.
1
LED Current (A)
0.8
0.6
0.4
0.2
0
0
0.2
0.4
0.6
0.8
IADJ Voltage (V)
1
1.2
1.4
D001
Figure 32. Analog Dimming Profile
32
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9.2.3 LM3409 Buck Converter Application
RUV2
RUV1
1
VIN
UVLO
10
VIN
CF
2
3
ROFF
VCC
IADJ
EN
LM3409/HV
CSP
CIN
9
8
RSNS
4
COFF
COFF
CSN
7
DAP
5
GND
PGATE
6
Q1
L1
VO
ILED
D1
Figure 33. LM3409 Buck Converter Simplified Schematic
9.2.3.1 Design Requirements
Nominal input voltage: VIN
Maximum input voltage: VIN-MAX
Nominal output voltage (number of LEDs x forward voltage): VO
LED string dynamic resistance: rD
Switching frequency (at nominal VIN, VO): fSW
Average LED current: ILED
Inductor current ripple: ΔiL-PP
LED current ripple: ΔiLED-PP
Input voltage ripple: ΔvIN-PP
UVLO characteristics: VTURN-ON and VHYS
Expected efficiency: η
9.2.3.2 Detailed Design Procedure
9.2.3.2.1 Nominal Switching Frequency
Calculate switching frequency (fSW) at the nominal operating point (VIN and VO). Assume a COFF value (from 470
pF to 1 nF) and a system efficiency (η). Solve for ROFF:
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R OFF =
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§
VO ·
¸
- ¨¨1¸
© K x VIN ¹
·
§
(COFF + 20 pF) x fSW x ln ¨¨1 - 1.24V ¸¸
V
O ¹
©
(92)
9.2.3.2.2 Inductor Ripple Current
Set the inductor ripple current (ΔiL-PP) by solving for the appropriate inductor (L1):
V xt
L1 = O OFF
'iL- PP
(93)
9.2.3.2.3 Average LED Current
Set the average LED current (ILED) by first solving for the peak inductor current (IL-MAX):
'i
IL- MAX = ILED + L- PP
2
(94)
Peak inductor current is detected across the sense resistor (RSNS). In most cases, assume the maximum value
(VADJ = 1.24 V) at the IADJ pin and solve for RSNS:
VADJ
RSNS =
5 x IL - MAX
(95)
If the calculated RSNS is far from a standard value, the beginning of the process can be iterated to choose a new
ROFF, L1, and RSNS value that is a closer fit. The easiest way to approach the iterative process is to change the
nominal fSW target knowing that the switching frequency varies with operating conditions anyways.
Another method for finding a standard RSNS value is to change the VADJ value. However, this would require an
external voltage source or a resistor from the IADJ pin to GND as explained in the Adjustable Peak Current
Control section of this data sheet.
9.2.3.2.4 Output Capacitance
A minimum output capacitance (CO-MIN) may be necessary to reduce ΔiLED-PP below ΔiL-PP. With the specified
ΔiLED-PP and the known dynamic resistance (rD) of the LED string, solve for the required impedance (ZC) for COMIN:
r x 'iLED - PP
ZC = D
'iL - PP - 'iLED - PP
(96)
Solve for CO-MIN:
CO - MIN =
1
2 x S x fSW x Z C
(97)
9.2.3.2.5 Input Capacitance
Set the input voltage ripple (ΔvIN-PP) by solving for the required minimum capacitance (CIN-MIN):
·
§ 1
- t OFF¸¸
ILED x ¨¨
I xt
¹
© fSW
CIN- MIN = LED ON =
'vIN - PP
'vIN - PP
(98)
The necessary RMS input current rating (IIN-RMS) is:
IIN - RMS = ILED x fSW x t ON x t OFF
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(99)
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SNVS602L – MARCH 2009 – REVISED JUNE 2016
9.2.3.2.6 PFET
The PFET voltage rating should be at least 15% higher than the maximum input voltage (VIN-MAX) and current
rating should be at least 10% higher than the average PFET current (IT):
IT = D x ILED
(100)
Given a PFET with on-resistance (RDS-ON), solve for the RMS transistor current (IT-RMS) and power dissipation
(PT):
2·
§
1 § 'i ·
IT- RMS = ILED x D x ¨¨1+ x ¨¨ L-PP ¸¸ ¸¸
¨ 12 © ILED ¹ ¸
©
¹
(101)
2
PT = IT- RMS x R DSON
(102)
9.2.3.2.7 Diode
The Schottky diode needs a voltage rating similar to the PFET. Higher current diodes with a lower forward
voltage are suggested. Given a diode with forward voltage (VD), solve for the average diode current (ID) and
power dissipation (PD):
ID = (1- D) x ILED
(103)
PD = ID x VD
(104)
9.2.3.2.8 Input UVLO
Input UVLO is set with the turnon threshold voltage (VTURN-ON) and the desired hysteresis (VHYS). To set VHYS,
solve for RUV2:
V
RUV2 = HYS
22 PA
(105)
To set VTURN-ON, solve for RUV1:
RUV1 =
1.24V x RUV2
VTURN - ON - 1.24V
(106)
9.2.3.2.9 IADJ Connection Method
The IADJ pin controls the high-side current sense threshold in three ways outlined in the Adjustable Peak
Current Control section.
Method 1: Leave IADJ pin open and ILED is calculated as in the Average LED Current section of the Design
Guide.
Method 2: Apply an external voltage (VADJ) to the IADJ pin from 0 to 1.24 V to analog dim or to reduce ILED as
follows:
'i
VADJ
ILED =
- L - PP
5 x RSNS
2
(107)
Keep in mind that analog dimming will eventually push the converter in to DCM and the inductor current ripple
will no longer be constant causing a divergence from linear dimming at low levels.
A 0.1 µF capacitor connected from the IADJ pin to GND is recommended when using this method. It may also be
necessary to have a 1kΩ series resistor with the capacitor to create an RC filter. The filter will help remove high
frequency noise created by other connected circuitry.
Method 3: Connect an external resistor or potentiometer to GND (REXT) and the internal 5 µA current source will
set the voltage. Again, a 0.1 µF capacitor connected from the IADJ pin to GND is recommended. To set ILED,
solve for REXT:
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www.ti.com
'i ·
§
¨ILED + L-PP¸ x RSNS
2 ¹
REXT = ©
1 PA
(108)
9.2.3.2.10 PWM Dimming Method
There are two methods to PWM dim using the LM3409/09HV:
Method 1:Apply an external PWM signal to the EN terminal.
Method 2: Perform external parallel FET shunt dimming as detailed in the External Parallel FET PWM Dimming
section.
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LM3409, LM3409-Q1, LM3409HV, LM3409HV-Q1
www.ti.com
SNVS602L – MARCH 2009 – REVISED JUNE 2016
10 Power Supply Recommendations
Any DC output power supply may be used provided it has a high enough voltage and current range for the
particular application required.
11 Layout
11.1 Layout Guidelines
The performance of any switching converter depends as much upon the layout of the PCB as the component
selection. Following a few simple guidelines will maximimize noise rejection and minimize the generation of EMI
within the circuit.
Discontinuous currents are the most likely to generate EMI, therefore take care when routing these paths. The
main path for discontinuous current in the LM3409/09HV buck converter contains the input capacitor (CIN), the
recirculating diode (D1), the P-channel MOSFET (Q1), and the sense resistor (RSNS). This loop should be kept as
small as possible and the connections between all three components should be short and thick to minimize
parasitic inductance. In particular, the switch node (where L1, D1 and Q1 connect) should be just large enough
to connect the components without excessive heating from the current it carries.
The IADJ, COFF, CSN and CSP pins are all high-impedance control inputs which couple external noise easily,
therefore the loops containing these high impedance nodes should be minimized. The most sensitive loop
contains the sense resistor (RSNS) which should be placed as close as possible to the CSN and CSP pins to
maximize noise rejection. The off-time capacitor (COFF) should be placed close to the COFF and GND pins for
the same reason. Finally, if an external resistor (REXT) is used to bias the IADJ pin, it should be placed close to
the IADJ and GND pins, also.
In some applications the LED or LED array can be far away (several inches or more) from the LM3409/09HV, or
on a separate PCB connected by a wiring harness. When an output capacitor is used and the LED array is large
or separated from the rest of the converter, the output capacitor should be placed close to the LEDs to reduce
the effects of parasitic inductance on the AC impedance of the capacitor.
11.2 Layout Example
GND
CIN
RUV1
VIN
RUV2
UVLO
LED-
VIN
CF
COFF
IADJ
VCC
EN
CSP
COFF
CSN
GND
ROFF
RSNS
D1
PGATE
GND
L1
Q1
LED+
+
VIA
Figure 34. Layout Recommendation
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SNVS602L – MARCH 2009 – REVISED JUNE 2016
www.ti.com
12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
LM3409
Click here
Click here
Click here
Click here
Click here
LM3409-Q1
Click here
Click here
Click here
Click here
Click here
LM3409HV
Click here
Click here
Click here
Click here
Click here
LM3409HV-Q1
Click here
Click here
Click here
Click here
Click here
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: LM3409 LM3409-Q1 LM3409HV LM3409HV-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM3409HVMY/NOPB
ACTIVE
HVSSOP
DGQ
10
1000
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 125
SYHB
LM3409HVMYX/NOPB
ACTIVE
HVSSOP
DGQ
10
3500
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 125
SYHB
LM3409MY/NOPB
ACTIVE
HVSSOP
DGQ
10
1000
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 125
SXFB
LM3409MYX/NOPB
ACTIVE
HVSSOP
DGQ
10
3500
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 125
SXFB
LM3409QHVMY/NOPB
ACTIVE
HVSSOP
DGQ
10
1000
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 125
SZEB
LM3409QHVMYX/NOPB
ACTIVE
HVSSOP
DGQ
10
3500
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 125
SZEB
LM3409QMY/NOPB
ACTIVE
HVSSOP
DGQ
10
1000
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 125
SZDB
LM3409QMYX/NOPB
ACTIVE
HVSSOP
DGQ
10
3500
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 125
SZDB
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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