LM3409QMY

LM3409 / LM3409HV / LM3409Q / LM3409QHV PFET Buck Controller for High Power LED Drives LM3409 / LM3409HV LM3409Q / LM3409QHV PFET Buck Controller for High Power LED Drives General Description The LM3409/09HV are P-channel MosFET (PFET) controllers for step-down (buck) current regulators. They offer wide input voltage range, high-side differential current sense with low adjustable threshold voltage, fast output enable/disable function and a thermally enhanced eMSOP-10 package. These features combine to make the LM3409/09HV ideal for use as constant current sources for driving LEDs where forward currents up to 5A are easily achievable. The LM3409/09Q/09HV/09QHV uses Constant Off-Time (COFT) control to regulate an accurate constant current without the need for external control loop compensation. Analog and PWM dimming are easy to implement and result in a highly linear dimming range with excellent achievable contrast ratios. Programmable UVLO, low-power shutdown, and thermal shutdown complete the feature set. April 12, 2010 Features ■ LM3409Q/LM3409QHV is an Automotive Grade product that is AEC-Q100 grade 1 qualified 2Ω, 1A Peak MosFET Gate Drive VIN Range: 6V to 42V (LM3409/LM3409Q) VIN Range: 6V to 75V (LM3409HV/LM3409QHV) Differential, High-side Current Sense Cycle-by-Cycle Current Limit No Control Loop Compensation Required 10,000:1 PWM Dimming Range 250:1 Analog Dimming Range Supports All-Ceramic Output Capacitors and Capacitorless Outputs ■ Low Power Shutdown ■ Thermal Shutdown Protection ■ Thermally Enhanced eMSOP-10 Package ■ ■ ■ ■ ■ ■ ■ ■ ■ Applications ■ ■ ■ ■ ■ LED Driver Constant Current Source Automotive Lighting General Illumination Industrial Lighting Typical Application 30085601 © 2010 National Semiconductor Corporation 300856 www.national.com LM3409/LM3409HV/LM3409Q/LM3409QHV Connection Diagram LM3409/09Q/09HV/09QHV 30085602 10-Lead Exposed Pad eMSOP Package Ordering Information Order Number LM3409MY LM3409MYX LM3409HVMY LM3409HVMYX LM3409QMY LM3409QMYX LM3409QHVMY LM3409QHVMYX NSC Package Drawing MUC10A MUC10A MUC10A MUC10A MUC10A MUC10A MUC10A MUC10A Top Marking SXFB SXFB SYHB SYHB SZDB SZDB SZEB SZEB Supplied As 1000 Units on tape and reel 3500 Units on tape and reel 1000 Units on tape and reel 3500 Units on tape and reel 1000 Units on tape and reel 3500 Units on tape and reel 1000 Units on tape and reel 3500 Units on tape and reel AEC-Q100 Grade 1 qualified. Automotive Grade Production Flow* Feature *Automotive Grade (Q) product incorporates enhanced manufacturing and support processes for the automotive market, including defect detection methodologies. Reliability qualification is compliant with the requirements and temperature grades defined in the AEC-Q100 standard. Automotive grade products are identified with the letter Q. For more information go to http://www.national.com/automotive. Pin Descriptions Pin(s) 1 2 3 4 5 6 7 8 9 10 DAP Name UVLO IADJ EN COFF GND PGATE CSN CSP VCC VIN DAP Description Input under-voltage lockout Analog LED current adjust Logic level enable / PWM dimming Off-time programming Ground Gate drive Negative current sense Positive current sense VIN- referenced linear regulator output Input voltage Thermal pad on bottom of IC Application Information Connect to a resistor divider from VIN and GND. Turn-on threshold is 1.24V and hysteresis for turn-off is provided by a 22µA current source. Apply a voltage between 0 - 1.24V, connect a resistor to GND, or leave open to set the current sense threshold voltage. Apply a voltage >1.74V to enable device, a PWM signal to dim, or a voltage 9V 0 < ICC < 20 mA VCC increasing VCC decreasing 30 5.5 6 3.73 283 45 6.5 V V mV mA 1.243 5 38 2 110 2 2 1.297 6.4 208 261 V/V V µA ns mA µA Ω Units PEAK CURRENT COMPARATOR VCST VCSP – VCSN average peak current threshold (Note 6) VADJ to VCSP – VCSN threshold gain IADJ pin open circuit voltage IADJ pin current CSN pin falling delay Operating current Shutdown hysteresis current Driver output resistance VADJ = 1.0V VADJ = VADJ-OC 0.1 < VADJ < 1.2V VADJ = VADJ-OC mV AADJ VADJ-OC IADJ tDEL IIN ISD PFET DRIVER RPGATE SYSTEM CURRENTS 3 www.national.com LM3409/LM3409HV/LM3409Q/LM3409QHV Symbol OFF-TIMER AND ON-TIMER VOFT tD-OFF tON-MIN tOFF-MAX IUVLO VUVLO-R IUVLO-HYS ENABLE IEN VEN-TH VEN-HYS tEN-R tEN-F θJA Parameter Conditions Min Typ Max (Note 4) (Note 3) (Note 4) 1.122 1.243 25 115 300 211 1.364 Units Off-time threshold COFF threshold to PGATE falling delay Minimum on-time Maximum off-time UVLO pin current Rising UVLO threshold UVLO hysteresis current EN pin current EN pin threshold EN pin hysteresis EN pin rising delay EN pin falling delay Junction to Ambient EN rise - PGATE fall EN fall - PGATE rise eMSOP-10 Package (Note 5) VEN rising VEN falling VUVLO = 1V V ns ns µs nA UNDER VOLTAGE LOCKOUT 10 1.175 1.243 22 10 1.74 .5 420 42 21 50 mV ns ns °C/W 1.311 V µA nA V THERMAL RESISTANCE Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Operating Ratings is not implied. The recommended Operating Ratings indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Note 2: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Note 3: Typical values represent most likely parametric norms at the conditions specified and are not guaranteed. Note 4: Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate National's Average Outgoing Quality Level (AOQL). Note 5: θJA of 50°C/W with DAP soldered to a minimum of 2 square inches of 1oz. copper on the top or bottom PCB layer. Actual value will be different depending upon the application enviroment. Note 6: The current sense threshold limits are calculated by averaging the results from the two polarities of the high-side differential amplifier. Note 7: The measurements were made using the Bill of Materials from Design #3. Note 8: The measurements were made using the Bill of Materials from Design #3 except the LM3409 was substituted for the LM3409HV. Note 9: The waveforms were acquired using the standard evaluation board from AN-1953. www.national.com 4 LM3409/LM3409HV/LM3409Q/LM3409QHV Typical Performance Characteristics TA = +25°C, VIN = 24V, and characteristics are identical for LM3409 and LM3409HV unless otherwise specified. VCST vs. Junction Temperature VCC vs. Junction Temperature 300856b5 300856b6 VADJ vs. Junction Temperature IADJ vs. Junction Temperature 300856b8 300856b7 VOFT vs. Junction Temperature tON-MIN vs. Junction Temperature 300856b9 300856c0 5 www.national.com LM3409/LM3409HV/LM3409Q/LM3409QHV LM3409 Efficiency vs. Input Voltage VO = 17V (5 LEDs); ILED = 2A (Note 8) LM3409HV Efficiency vs. Input Voltage VO = 17V (5 LEDs); ILED = 2A (Note 7) 300856f0 300856b3 LM3409 LED Current vs. Input Voltage VO = 17V (5 LEDs) (Note 8) LM3409HV LED Current vs. Input Voltage VO = 17V (5 LEDs) (Note 7) 300856f1 300856b4 Normalized Switching Frequency vs. Input Voltage Amplitude Dimming Using IADJ Pin VO = 17V (5 LEDs); VIN = 24V 300856c1 300856b2 www.national.com 6 LM3409/LM3409HV/LM3409Q/LM3409QHV Internal EN Pin PWM Dimming VO = 17V (5 LEDs); VIN = 24V External Parallel FET PWM Dimming VO = 17V (5 LEDs); VIN = 24V 300856b0 300856b1 20kHz 50% EN pin PWM dimming VO = 42V (12 LEDs); VIN = 48V (Note 9) 100kHz 50% External FET PWM dimming VO = 42V (12 LEDs); VIN = 48V (Note 9) 300856f5 300856f6 20kHz 50% EN pin PWM dimming (rising edge) VO = 42V (12 LEDs); VIN = 48V (Note 9) 100kHz 50% External FET PWM dimming (rising edge) VO = 42V (12 LEDs); VIN = 48V (Note 9) 300856f7 300856f8 7 www.national.com LM3409/LM3409HV/LM3409Q/LM3409QHV Block Diagram 30085603 Theory of Operation The LM3409/09HV are P-channel MosFET (PFET) controllers for step-down (buck) current regulators which are ideal for driving LED loads. They have wide input voltage range allowing for regulation of a variety of LED loads. The high-side differential current sense, with low adjustable threshold voltage, provides an excellent method for regulating output current while maintaining high system efficiency. The LM3409/09HV uses a Controlled Off-Time (COFT) architecture that allows the converter to be operated in both continuous conduction mode (CCM) and discontinuous conduction mode (DCM) with no external control loop compensation, while providing an inherent cycle-by-cycle current limit. The adjustable current sense threshold provides the capability to amplitude (analog) dim the LED current over the full range and the fast output enable/disable function allows for high frequency PWM dimming using no external components. When designing, the maximum attainable LED current is not internally limited because the LM3409/09HV is a controller. Instead it is a function of the system operating point, component choices, and switching frequency allowing the LM3409/09HV to easily provide constant currents up to 5A. This simple controller contains all the features necessary to implement a high efficiency versatile LED driver. BUCK CURRENT REGULATORS The buck regulator is unique among non-isolated topologies due to the direct connection of the inductor to the load during the entire switching cycle. An inductor will control the rate of change of current that flows through it, therefore a direct connection to the load is excellent for current regulation. A buck current regulator, using the LM3409/09HV, is shown in the Typical Application section on the first page of this datasheet. During the time that the PFET (Q1) is turned on (tON), the input voltage charges up the inductor (L1). When Q1 is turned off (tOFF), the re-circulating diode (D1) becomes forward biased and L1 discharges. During both intervals, the current is supplied to the load keeping the LEDs forward biased. Figure 1 shows the inductor current (iL(t)) waveform for a buck converter operating in CCM. The average inductor current (IL) is equal to the average output LED current (ILED), therefore if IL is tightly controlled, ILED will be well regulated. As the system changes input voltage or output voltage, duty cycle (D) is varied to regulate IL and ultimately ILED. For any buck regulator, D is simply the conversion ratio divided by the efficiency (η): www.national.com 8 LM3409/LM3409HV/LM3409Q/LM3409QHV 30085604 FIGURE 1. Ideal CCM Buck Converter Inductor Current iL(t) CONTROLLED OFF-TIME (COFT) ARCHITECTURE The COFT architecture is used by the LM3409/09HV to control ILED. It is a combination of peak current detection and a one-shot off-timer that varies with output voltage. D is indirectly controlled by changes in both tOFF and tON, which vary depending on the operating point. This creates a variable switching frequency over the entire operating range. This type of hysteretic control eliminates the need for control loop compensation necessary in many switching regulators, simplifying the design process and providing fast transient response. Adjustable Peak Current Control At the beginning of a switching period, PFET Q1 is turned on and inductor current increases. Once peak current is detected, Q1 is turned off, the diode D1 forward biases, and inductor current decreases. Figure 2 shows how peak current detection is accomplished using the differential voltage signal created as current flows through the current setting resistor (RSNS). The voltage across RSNS (VSNS) is compared to the adjustable current sense threshold (VCST) and Q1 is turned off when VSNS exceeds VCST, providing that tON is greater than the minimum possible tON (typically 115ns). 30085605 FIGURE 2. Peak Current Control Circuit 9 www.national.com LM3409/LM3409HV/LM3409Q/LM3409QHV There are three different methods to set the current sense threshold (VCST) using the multi-function IADJ pin: 1. IADJ pin left open: 5µA internal current source biases the Zener diode and clamps the IADJ pin voltage (VADJ) at 1.24V causing the maximum threshold voltage: 2. 3. External voltage (VADJ) of 0V to 1.24V: Apply to the IADJ pin to adjust VCST from 0V to 248mV. If the VADJ voltage is adjustable, analog dimming can be achieved. External resistor (REXT) placed from IADJ pin to ground: 5µA current source sets the VADJ voltage and corresponding threshold voltage: 30085607 FIGURE 4. Exponential Charging Function vCOFF(t) Controlled Off-Time Once Q1 is turned off, it remains off for a constant time (tOFF) which is preset by an external resistor (ROFF), an external capacitor (COFF), and the output voltage (VO) as shown in Figure 3. Since ILED is tightly regulated, VO will remain nearly constant over widely varying input voltage and temperature yielding a nearly constant tOFF. Although the tOFF equation is non-linear, tOFF is actually very linear in most applications. Ignoring the 20pF parasitic capacitance at the COFF pin, vCOFF(t) is plotted in Figure 4. The time derivative of vCOFF(t) can be calculated to find a linear approximation to the tOFF equation: When tOFF > 1.24V), the slope of the function is essentially linear and tOFF can be approximated as a current source charging COFF: 30085606 FIGURE 3. Off-Time Control Circuit At the start of tOFF, the voltage across COFF (vCOFF(t)) is zero and the capacitor begins charging according to the time constant provided by ROFF and COFF. When vCOFF(t) reaches the off-time threshold (VOFT = 1.24V), then the off-time is terminated and vCOFF(t) is reset to zero. tOFF is calculated as follows: Using the actual tOFF equation, the inductor current ripple (ΔiL-PP) of a buck current regulator operating in CCM is: Using the tOFF approximation, the equation is reduced to: In reality, there is typically 20 pF parasitic capacitance at the off-timer pin in parallel with COFF, which is accounted for in the calculation of tOFF. Also, it should be noted that the tOFF equation has a preceding negative sign because the result of the logarithm should be negative for a properly designed circuit. The resulting tOFF is a positive value as long as VO > 1.24V. If VO < 1.24V, the off-timer cannot reach VOFT and an internally limited maximum off-time (typically 300µs) will occur. ΔiL-PP is independent of both VIN and VO when in CCM! The ΔiL-PP approximation only depends on ROFF, COFF, and L1, therefore the ripple is essentially constant over the operating range as long as VO >> 1.24V (when the tOFF approximation is valid). An exception to the tOFF approximation occurs if the IADJ pin is used to analog dim. As the LED/inductor current decreases, the converter will eventually enter DCM and the ripple will decrease with the peak current threshold. The approximation shows how the LM3409/09HV achieves constant ripple over a wide operating range, however tOFF should be calculated using the actual equation first presented. www.national.com 10 LM3409/LM3409HV/LM3409Q/LM3409QHV AVERAGE LED CURRENT For a buck converter, the average LED current is simply the average inductor current. INDUCTOR CURRENT RIPPLE Because the LM3409/09HV swaps the polarity of the differential current sense comparator every cycle, a minimum inductor current ripple (ΔiL-PP) is necessary to maintain accurate ILED regulation. Referring to Figure 6, the first tON is terminated at the higher of the two polarity-swapped thresholds (corresponding to IL-MAXH). During the following tOFF, iL decreases until the second tON begins. If tOFF is too short, then as the second tON begins, iL will still be above the lower peak current threshold (corresponding to IL-MAXL) and a minimum tON pulse will follow. This will result in degraded ILED regulation. The minimum inductor current ripple (ΔiL-PP-MIN) should adhere to the following equation in order to ensure accurate ILED regulation: 30085611 FIGURE 5. Sense Voltage vSNS(t) Using the COFT architecture, the peak transistor current (ITMAX) is sensed as shown in Figure 5, which is equal to the peak inductor current (IL-MAX) given by the following equation: Because IL-MAX is set using peak current control and ΔiL-PP is set using the controlled off-timer, IL and correspondingly ILED can be calculated as follows: SWITCHING FREQUENCY The switching frequency is dependent upon the actual operating point (VIN and VO). VO will remain relatively constant for a given application, therefore the switching frequency will vary with VIN (frequency increases as VIN increases). The target switching frequency (fSW) at the nominal operating point is selected based on the tradeoffs between efficiency (better at low frequency) and solution size/cost (smaller at high frequency). The off-time of the LM3409/09HV can be programmed for switching frequencies up to 5 MHz (theoretical limit imposed by minimum tON). In practice, switching frequencies higher than 1MHz may be difficult to obtain due to gate drive limitations, high input voltage, and thermal considerations. At CCM operating points, fSW is defined as: The threshold voltage VCST seen by the high-side sense comparator is affected by the comparator’s input offset voltage, which causes an error in the calculation of IL-MAX and ultimately ILED. To mitigate this problem, the polarity of the comparator inputs is swapped every cycle, which causes the actual IL-MAX to alternate between two peak values (IL-MAXH and IL-MAXL), equidistant from the theoretical IL-MAX as shown in Figure 6. ILED remains accurate through this averaging. At DCM operating points, fSW is defined as: In the CCM equation, it is apparent that the efficiency (η) factors into the switching frequency calculation. Efficiency is hard to estimate and, since switching frequency varies with input voltage, accuracy in setting the nominal switching frequency is not critical. Therefore, a general rule of thumb for the LM3409/09HV is to assume an efficiency between 85% and 100%. When approximating efficiency to target a nominal switching frequency, the following condition must be met: 30085612 FIGURE 6. Inductor Current iL(t) Showing IL-MAX Offset 11 www.national.com LM3409/LM3409HV/LM3409Q/LM3409QHV 30085614 FIGURE 7. LED Current iLED(t) During EN Pin PWM Dimming PWM DIMMING USING THE EN PIN The enable pin (EN) is a TTL compatible input for PWM dimming of the LED. A logic low (below 0.5V) at EN will disable the internal driver and shut off the current flow to the LED array. While the EN pin is in a logic low state the support circuitry (driver, bandgap, VCC regulator) remains active in order to minimize the time needed to turn the LED array back on when the EN pin sees a logic high (above 1.74V). Figure 7 shows the LED current (iLED(t)) during PWM dimming where duty cycle (DDIM) is the percentage of the dimming period (TDIM) that the PFET is switching. For the remainder of TDIM, the PFET is disabled. The resulting dimmed average LED current (IDIM-LED) is: 30085613 FIGURE 8. UVLO Circuit The turn-on threshold (VTURN-ON) is defined as follows: The LED current rise and fall times (which are limited by the slew rate of the inductor as well as the delay from activation of the EN pin to the response of the external PFET) limit the achievable TDIM and DDIM. In general, dimming frequency should be at least one order of magnitude lower than the steady state switching frequency in order to prevent aliasing. However, for good linear response across the entire dimming range, the dimming frequency may need to be even lower. HIGH VOLTAGE NEGATIVE BIAS REGULATOR The LM3409/09HV contains an internal linear regulator where the steady state VCC pin voltage is typically 6.2V below the voltage at the VIN pin. The VCC pin should be bypassed to the VIN pin with at least 1µF of ceramic capacitance connected as close as possible to the IC. INPUT UNDER-VOLTAGE LOCKOUT (UVLO) Under-voltage lockout is set with a resistor divider from VIN to GND and is compared against a 1.24V threshold as shown in Figure 8. Once the input voltage is above the preset UVLO rising threshold (and assuming the part is enabled), the internal circuitry becomes active and a 22µA current source at the UVLO pin is turned on. This extra current provides hysteresis to create a lower UVLO falling threshold. The resistor divider is chosen to set both the UVLO rising and falling thresholds. The hysteresis (VHYS) is defined as follows: LOW POWER SHUTDOWN The LM3409/09HV can be placed into a low power shutdown (typically 110µA) by grounding the EN terminal (any voltage below 0.5V) until VCC drops below the VCC UVLO threshold (typically 3.73V). During normal operation this terminal should be tied to a voltage above 1.74V and below absolute maximum input voltage rating. THERMAL SHUTDOWN Internal thermal shutdown circuitry is provided to protect the IC in the event that the maximum junction temperature is exceeded. The threshold for thermal shutdown is 160°C with 15° C of hysteresis (both values typical). During thermal shutdown the PFET and driver are disabled. www.national.com 12 LM3409/LM3409HV/LM3409Q/LM3409QHV Design Considerations OPERATION NEAR DROPOUT Because the power MosFET is a PFET, the LM3409/09HV can be operated into dropout which occurs when the input voltage is approximately equal to output voltage. Once the input voltage drops below the nominal output voltage, the switch remains constantly on (D=1) causing the output voltage to decrease with the input voltage. In normal operation, the average LED current is regulated to the peak current threshold minus half of the ripple. As the converter goes into dropout, the LED current is exactly at the peak current threshold because it is no longer switching. This causes the LED current to increase by half of the set ripple current as it makes the transition into dropout. Therefore, the inductor current ripple should be kept as small as possible (while remaining above the previously established minimum) and output capacitance should be added to help maintain good line regulation when approaching dropout. LED RIPPLE CURRENT Selection of the ripple current through the LED array is analogous to the selection of output ripple voltage in a standard voltage regulator. Where the output voltage ripple in a voltage regulator is commonly ±1% to ±5% of the DC output voltage, LED manufacturers generally recommend values for ΔiLEDPP ranging from ±5% to ±20% of ILED. For a nominal system operating point, a larger ΔiLED-PP specification can reduce the necessary inductor size and/or allow for smaller output capacitors (or no output capacitors at all) which helps to minimize the total solution size and cost. On the other hand, a smaller ΔiLED-PP specification would require more output inductance, a higher switching frequency, or additional output capacitance. BUCK CONVERTERS W/O OUTPUT CAPACITORS Because current is being regulated, not voltage, a buck current regulator is free of load current transients, therefore output capacitance is not needed to supply the load and maintain output voltage. This is very helpful when high frequency PWM dimming the LED load. When no output capacitor is used, the same design equations that govern ΔiL-PP also apply to ΔiLED-PP. BUCK CONVERTERS WITH OUTPUT CAPACITORS A capacitor placed in parallel with the LED load can be used to reduce ΔiLED-PP while keeping the same average current through both the inductor and the LED array. With an output capacitor, the inductance can be lowered, making the magnetics smaller and less expensive. Alternatively, the circuit can be run at lower frequency with the same inductor value, improving the efficiency and increasing the maximum allowable average output voltage. A parallel output capacitor is also useful in applications where the inductor or input voltage tolerance is poor. Adding a capacitor that reduces ΔiLED-PP to well below the target provides headroom for changes in inductance or VIN that might otherwise push the maximum ΔiLED-PP too high. 300856f2 FIGURE 9. Calculating Dynamic Resistance rD Output capacitance (CO) is determined knowing the desired ΔiLED-PP and the LED dynamic resistance (rD). rD can be calculated as the slope of the LED’s exponential DC characteristic at the nominal operating point as shown in Figure 9. Simply dividing the forward voltage by the forward current at the nominal operating point will give an incorrect value that is 5x to 10x too high. Total dynamic resistance for a string of n LEDs connected in series can be calculated as the rD of one device multiplied by n. The following equations can then be used to estimate ΔiLED-PP when using a parallel capacitor: In general, ZC should be at least half of rD to effectively reduce the ripple. Ceramic capacitors are the best choice for the output capacitors due to their high ripple current rating, low ESR, low cost, and small size compared to other types. When selecting a ceramic capacitor, special attention must be paid to the operating conditions of the application. Ceramic capacitors can lose one-half or more of their capacitance at their rated DC voltage bias and also lose capacitance with extremes in temperature. Make sure to check any recommended deratings and also verify if there is any significant change in capacitance at the operating voltage and temperature. OUTPUT OVER-VOLTAGE PROTECTION Because the LM3409/09HV controls a buck current regulator, there is no inherent need to provide output over-voltage protection. If the LED load is opened, the output voltage will only rise as high as the input voltage plus any ringing due to the parasitic inductance and capacitance present at the output node. If a ceramic output capacitor is used in the application, it should have a minimum rating equal to the input voltage. Ringing seen at the output node should not damage most ceramic capacitors, due to their high ripple current rating. 13 www.national.com LM3409/LM3409HV/LM3409Q/LM3409QHV INPUT CAPACITORS Input capacitors are selected using requirements for minimum capacitance and RMS ripple current. The PFET current during tON is approximately ILED, therefore the input capacitors discharge the difference between ILED and the average input current (IIN) during tON. During tOFF, the input voltage source charges up the input capacitors with IIN. The minimum input capacitance (CIN-MIN) is selected using the maximum input voltage ripple (ΔvIN-MAX) which can be tolerated. ΔvIN-MAX is equal to the change in voltage across CIN during tON when it supplies the load current. A good starting point for selection of CIN is to use ΔvIN-MAX of 2% to 10% of VIN. CIN-MIN can be selected as follows: An input capacitance at least 75% greater than the calculated CIN-MIN value is recommended. To determine the RMS input current rating (IIN-RMS) the following approximation can be used: Since this approximation assumes there is no inductor ripple current, the value should be increased by 10-30% depending on the amount of ripple that is expected. Ceramic capacitors are the best choice for input capacitors for the same reasons mentioned in the Buck Converters with Output Capacitors section. Careful selection of the capacitor requires checking capacitance ratings at the nominal operating voltage and temperature. P-CHANNEL MosFET (PFET) The LM3409/09HV requires an external PFET (Q1) as the main power MosFET for the switching regulator. Q1 should have a voltage rating at least 15% higher than the maximum input voltage to ensure safe operation during the ringing of the switch node. In practice all switching converters have some ringing at the switch node due to the diode parasitic capacitance and the lead inductance. The PFET should also have a current rating at least 10% higher than the average transistor current (IT): It is important to consider the gate charge of Q1. As the input voltage increases from a nominal voltage to its maximum input voltage, the COFT architecture will naturally increase the switching frequency. The dominant switching losses are determined by input voltage, switching frequency, and PFET total gate charge (Qg). The LM3409/09HV has to provide and remove charge Qg from the input capacitance of Q1 in order to turn it on and off. This occurs more often at higher switching frequencies which requires more current from the internal regulator, thereby increasing internal power dissipation and eventually causing the LM3409/09HV to thermally cycle. For a given range of operating points the only effective way to reduce these switching losses is to minimize Qg. A good rule of thumb is to limit Qg < 30nC (if the switching frequency remains below 300kHz for the entire operating range then a larger Qg can be considered). If a PFET with small RDS-ON and a high voltage rating is required, there may be no choice but to use a PFET with Qg > 30nC. When using a PFET with Qg > 30nC, the bypass capacitor (CF) should not be connected to the VIN pin. This will ensure that peak current detection through RSNS is not affected by the charging of the PFET input capacitance during switching, which can cause false triggering of the peak detection comparator. Instead, CF should be connected from the VCC pin to the CSN pin which will cause a small DC offset in VCST and ultimately ILED, however it avoids the problematic false triggering. In general, the PFET should be chosen to meet the Qg specification whenever possible, while minimizing RDS-ON. This will minimize power losses while ensuring the part functions correctly over the full operating range. RE-CIRCULATING DIODE A re-circulating diode (D1) is required to carry the inductor current during tOFF. The most efficient choice for D1 is a Schottky diode due to low forward voltage drop and near-zero reverse recovery time. Similar to Q1, D1 must have a voltage rating at least 15% higher than the maximum input voltage to ensure safe operation during the ringing of the switch node and a current rating at least 10% higher than the average diode current (ID): The power rating is verified by calculating the power loss through the diode. This is accomplished by checking the typical diode forward voltage (VD) from the I-V curve on the product datasheet and calculating as follows: The power rating is verified by calculating the power loss (PT) using the RMS transistor current (IT-RMS) and the PFET on-resistance (RDS-ON): In general, higher current diodes have a lower VD and come in better performing packages minimizing both power losses and temperature rise. www.national.com 14 LM3409/LM3409HV/LM3409Q/LM3409QHV 30085616 FIGURE 10. Ideal LED Current iLED(t) During Parallel FET Dimming EXTERNAL PARALLEL FET PWM DIMMING Any buck topology LED driver is a good candidate for parallel FET dimming because high slew rates are achievable, due to the fact that no output capacitance is required. This allows for much higher dimming frequencies than are achievable using the EN pin. When using external parallel FET dimming, a situation can arise where maximum off-time occurs due to a shorted output. To mitigate this situation, capacitive coupling to the enable pin can be employed. The ideal LED current waveform iLED(t) during parallel FET PWM dimming is very similar to the EN pin PWM dimming shown previously. The LED current does not rise and fall infinitely fast as shown in Figure 10 however with this method, only the speed of the parallel Dim FET ultimately limits the dimming frequency and dimming duty cycle. This allows for much faster PWM dimming than can be attained with the EN pin. CIRCUIT LAYOUT The performance of any switching converter depends as much upon the layout of the PCB as the component selection. Following a few simple guidelines will maximimize noise rejection and minimize the generation of EMI within the circuit. Discontinuous currents are the most likely to generate EMI, therefore care should be taken when routing these paths. The main path for discontinuous current in the LM3409/09HV buck converter contains the input capacitor (CIN), the recirculating diode (D1), the P-channel MosFET (Q1), and the sense resistor (RSNS). This loop should be kept as small as possible and the connections between all three components should be short and thick to minimize parasitic inductance. In particular, the switch node (where L1, D1 and Q1 connect) should be just large enough to connect the components without excessive heating from the current it carries. The IADJ, COFF, CSN and CSP pins are all high-impedance control inputs which couple external noise easily, therefore the loops containing these high impedance nodes should be minimized. The most sensitive loop contains the sense resistor (RSNS) which should be placed as close as possible to the CSN and CSP pins to maximize noise rejection. The off-time capacitor (COFF) should be placed close to the COFF and GND pins for the same reason. Finally, if an external resistor (REXT) is used to bias the IADJ pin, it should be placed close to the IADJ and GND pins, also. In some applications the LED or LED array can be far away (several inches or more) from the LM3409/09HV, or on a separate PCB connected by a wiring harness. When an output capacitor is used and the LED array is large or separated from the rest of the converter, the output capacitor should be placed close to the LEDs to reduce the effects of parasitic inductance on the AC impedance of the capacitor. 30085617 FIGURE 11. External Parallel FET Dimming Circuit As shown in Figure 11, a small capacitor (CEXT) is connected from the gate drive signal of the parallel Dim FET to the EN pin and a pull-up resistor (REXT) is placed from the EN pin to the external VDD supply for the Dim FET gate driver. This forces the on-timer to restart corresponding to every rising edge of the LED voltage, ensuring that the unwanted maximum off-time condition does not occur. With this type of dimming, the EN pin does not control the dimming; it simply resets the controller. A good design choice is to size REXT and CEXT to give a time constant smaller than tOFF: 15 www.national.com LM3409/LM3409HV/LM3409Q/LM3409QHV Design Guide TYPICAL APPLICATION 30085601 SPECIFICATIONS Nominal input voltage: VIN Maximum input voltage: VIN-MAX Nominal output voltage (# of LEDs x forward voltage): VO LED string dynamic resistance: rD Switching frequency (at nominal VIN, VO): fSW Average LED current: ILED Inductor current ripple: ΔiL-PP LED current ripple: ΔiLED-PP Input voltage ripple: ΔvIN-PP UVLO characteristics: VTURN-ON and VHYS Expected efficiency: η 1. NOMINAL SWITCHING FREQUENCY Calculate switching frequency (fSW) at the nominal operating point (VIN and VO). Assume a COFF value (between 470pF and 1nF) and a system efficiency (η). Solve for ROFF: 3. AVERAGE LED CURRENT Set the average LED current (ILED) by first solving for the peak inductor current (IL-MAX): Peak inductor current is detected across the sense resistor (RSNS). In most cases, assume the maximum value (VADJ = 1.24V) at the IADJ pin and solve for RSNS: If the calculated RSNS is far from a standard value, the beginning of the process can be iterated to choose a new ROFF, L1, and RSNS value that is a closer fit. The easiest way to approach the iterative process is to change the nominal fSW target knowing that the switching frequency varies with operating conditions anyways. Another method for finding a standard RSNS value is to change the VADJ value. However, this would require an external voltage source or a resistor from the IADJ pin to GND as explained in the Theory of Operation section of this datasheet. 2. INDUCTOR RIPPLE CURRENT Set the inductor ripple current (ΔiL-PP) by solving for the appropriate inductor (L1): www.national.com 16 LM3409/LM3409HV/LM3409Q/LM3409QHV 4. OUTPUT CAPACITANCE A minimum output capacitance (CO-MIN) may be necessary to reduce ΔiLED-PP below ΔiL-PP. With the specified ΔiLED-PP and the known dynamic resistance (rD) of the LED string, solve for the required impedance (ZC) for CO-MIN: 8. INPUT UVLO Input UVLO is set with the turn-on threshold voltage (VTURNON) and the desired hysteresis (VHYS). To set V HYS, solve for RUV2: Solve for CO-MIN: To set VTURN-ON, solve for RUV1: 5. INPUT CAPACITANCE Set the input voltage ripple (ΔvIN-PP) by solving for the required minimum capacitance (CIN-MIN): 9. IADJ CONNECTION METHOD The IADJ pin controls the high-side current sense threshold in three ways outlined in the Theory of Operation section. Method #1: Leave IADJ pin open and ILED is calculated as in the Average LED Current section of the Design Guide. Method #2: Apply an external voltage (VADJ) to the IADJ pin between 0 and 1.24V to analog dim or to reduce ILED as follows: The necessary RMS input current rating (IIN-RMS) is: Keep in mind that analog dimming will eventually push the converter in to DCM and the inductor current ripple will no longer be constant causing a divergence from linear dimming at low levels. A 0.1µF capacitor connected from the IADJ pin to GND is recommended when using this method. It may also be necessary to have a 1kΩ series resistor with the capacitor to create an RC filter. The filter will help remove high frequency noise created by other connected circuitry. Method #3: Connect an external resistor or potentiometer to GND (REXT) and the internal 5µA current source will set the voltage. Again, a 0.1µF capacitor connected from the IADJ pin to GND is recommended. To set ILED, solve for REXT: 6. PFET The PFET voltage rating should be at least 15% higher than the maximum input voltage (VIN-MAX) and current rating should be at least 10% higher than the average PFET current (IT): Given a PFET with on-resistance (RDS-ON), solve for the RMS transistor current (IT-RMS) and power dissipation (PT): 7. DIODE The Schottky diode needs a voltage rating similar to the PFET. Higher current diodes with a lower forward voltage are suggested. Given a diode with forward voltage (VD), solve for the average diode current (ID) and power dissipation (PD): 10. PWM DIMMING METHOD There are two methods to PWM dim using the LM3409/09HV: Method #1: Apply an external PWM signal to the EN terminal. Method #2: Perform external parallel FET shunt dimming as detailed in the External Parallel FET PWM Dimming section. 17 www.national.com LM3409/LM3409HV/LM3409Q/LM3409QHV Design Example #1 EN PIN PWM DIMMING APPLICATION FOR 10 LEDS 30085618 SPECIFICATIONS fSW = 525kHz VIN = 48V; VIN-MAX = 75V VO = 35V ILED = 2A ΔiLED-PP = ΔiL-PP = 1A ΔvIN-PP = 1.44V VTURN-ON = 10V; VHYS = 1.1V η = 0.95 1. NOMINAL SWITCHING FREQUENCY Assume COFF = 470pF and η = 0.95. Solve for ROFF: The chosen components from step 1 are: 2. INDUCTOR RIPPLE CURRENT Solve for L1: The closest standard inductor value is 15 µH therefore the actual ΔiL-PP is: The chosen component from step 2 is: The closest 1% tolerance resistor is 24.9 kΩ therefore the actual tOFF and target fSW are: www.national.com 18 LM3409/LM3409HV/LM3409Q/LM3409QHV 3. AVERAGE LED CURRENT Determine IL-MAX: 6. PFET Determine minimum Q1 voltage rating and current rating: Assume VADJ = 1.24V and solve for RSNS: A 100V, 3.8A PFET is chosen with RDS-ON = 190mΩ and Qg = 20nC. Determine IT-RMS and PT: The closest 1% tolerance resistor is 0.1 Ω therefore the ILED is: The chosen component from step 3 is: 4. OUTPUT CAPACITANCE No output capacitance is necessary. 5. INPUT CAPACITANCE Determine tON: The chosen component from step 6 is: 7. DIODE Determine minimum D1 voltage rating and current rating: Solve for CIN-MIN: Choose CIN: A 100V, 3A diode is chosen with VD = 750mV. Determine PD : Determine IIN-RMS: The chosen component from step 7 is: The chosen components from step 5 are: 19 www.national.com LM3409/LM3409HV/LM3409Q/LM3409QHV 8. INPUT UVLO Solve for RUV2: The closest 1% tolerance resistor is 6.98 kΩ therefore VTURNON is: The closest 1% tolerance resistor is 49.9 kΩ therefore VHYS is: The chosen components from step 8 are: Solve for RUV1: 9. IADJ CONNECTION METHOD The IADJ pin is left open forcing VADJ = 1.24V. 10. PWM DIMMING METHOD PWM dimming signal pair is applied to the EN pin and GND at fDIM = 1 kHz. Design #1 Bill of Materials Qty 1 2 1 1 1 1 1 1 1 1 1 Part ID LM3409HV/ LM3409QHV CIN1, CIN2 CF COFF Q1 D1 L1 ROFF RUV1 RUV2 RSNS Part Value Buck controller 2.2µF X7R 10% 100V 1.0µF X7R 10% 16V 470pF X7R 10% 50V PMOS 100V 3.8A Schottky 100V 3A 15 µH 20% 4.2A 24.9kΩ 1% 6.98kΩ 1% 49.9kΩ 1% 0.1Ω 1% 1W Manufacturer NSC MURATA TDK TDK ZETEX VISHAY TDK VISHAY VISHAY VISHAY VISHAY Part Number LM3409HVMY/ LM3409QHVMY GRM43ER72A225KA01 L C1608X7R1C105K C1608X7R1H471K ZXMP10A18KTC SS3H10-E3/57T SLF12565T-150M4R2 CRCW060324K9FKEA CRCW06036K98FKEA CRCW060349K9FKEA WSL2512R1000FEA www.national.com 20 LM3409/LM3409HV/LM3409Q/LM3409QHV Design Example #2 ANALOG DIMMING APPLICATION FOR 4 LEDS 30085619 SPECIFICATIONS fSW = 500kHz VIN = 24V; VIN-MAX = 42V VO = 14V ILED = 1A ΔiL-PP = 450mA; ΔiLED-PP = 50mA ΔvIN-PP = 1V VTURN-ON = 10V; VHYS = 1.1V η = 0.90 1. NOMINAL SWITCHING FREQUENCY Assume COFF = 470pF and η = 0.90. Solve for ROFF: The chosen components from step 1 are: 2. INDUCTOR RIPPLE CURRENT Solve for L1: The closest standard inductor value is 22 µH therefore the actual ΔiL-PP is: The chosen component from step 2 is: The closest 1% tolerance resistor is 15.4 kΩ therefore the actual tOFF and target fSW are: 21 www.national.com LM3409/LM3409HV/LM3409Q/LM3409QHV 3. AVERAGE LED CURRENT Determine IL-MAX: Determine IIN-RMS: Assume VADJ = 1.24V and solve for RSNS: The chosen component from step 5 is: The closest 1% tolerance resistor is 0.2 Ω therefore ILED is: 6. PFET Determine minimum Q1 voltage rating and current rating: The chosen component from step 3 is: A 70V, 5.7A PFET is chosen with RDS-ON = 190mΩ and Qg = 20nC. Determine IT-RMS and PT: 4. OUTPUT CAPACITANCE Assume rD = 2 Ω and determine ZC: Solve for CO-MIN and : The chosen component from step 6 is: Choose CO: 7. DIODE Determine minimum D1 voltage rating and current rating: The chosen component from step 5 is: 5. INPUT CAPACITANCE Determine tON: Solve for CIN-MIN: A 60V, 5A diode is chosen with VD = 750mV. Determine PD: The chosen component from step 7 is: Choose CIN: www.national.com 22 LM3409/LM3409HV/LM3409Q/LM3409QHV 8. INPUT UVLO Solve for RUV2: The closest 1% tolerance resistor is 6.98 kΩ therefore VTURNON is: The closest 1% tolerance resistor is 49.9 kΩ therefore VHYS is: The chosen components from step 8 are: Solve for RUV1: 9. IADJ CONNECTION METHOD The IADJ pin is connected to an external voltage source and varied from 0 – 1.24V to dim. An RC filter (RF2 = 1 kΩ and CF2 = 0.1µF) is used as recommended. 10. PWM DIMMING METHOD No PWM dimming is necessary. Design #2 Bill of Materials Qty 1 2 1 1 1 1 1 1 1 1 1 1 1 1 Part ID LM3409/LM3409Q CIN1 CF CF2 COFF CO Q1 D1 L1 RF2 ROFF RUV1 RUV2 RSNS Part Value Buck controller 4.7µF X7R 10% 50V 1.0µF X7R 10% 16V 0.1µF X7R 10% 16V 470pF X7R 10% 50V 2.2µF X7R 10% 50V PMOS 70V 5.7A Schottky 60V 5A 22 µH 20% 4.2A 1.0kΩ 1% 15.4kΩ 1% 6.98kΩ 1% 49.9kΩ 1% 0.2Ω 1% 1W Manufacturer NSC MURATA TDK TDK TDK MURATA ZETEX COMCHIP TDK VISHAY VISHAY VISHAY VISHAY VISHAY Part Number LM3409MY/LM3409QMY GRM55ER71H475MA01L C1608X7R1C105K C1608X7R1C104K C1608X7R1H471K GRM43ER71H225MA01L ZXMP7A17KTC CDBC560-G SLF12575T-220M4R0 CRCW06031K00FKEA CRCW060315K4FKEA CRCW06036K98FKEA CRCW060349K9FKEA WSL2512R2000FEA 23 www.national.com LM3409/LM3409HV/LM3409Q/LM3409QHV Applications Information DESIGN #3: EXTERNAL PARALLEL FET PWM DIMMING APPLICATION FOR 10 LEDS 30085623 Design #3 Bill of Materials Qty 1 2 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 Part ID LM3409HV/ LM3409QHV CIN1, CIN2 CF COFF C1 Q1 Q2 Q3 D1 L1 R1, R2 R3 REXT ROFF RUV1 RUV2 RSNS Part Value Buck controller 2.2µF X7R 10% 100V 1.0µF X7R 10% 16V 470pF X7R 10% 50V 2200pF X7R 10% 50V PMOS 100V 3.8A CMOS 30V 2A NMOS 100V 7.5A Schottky 100V 3A 15 µH 20% 4.2A 1Ω 1% 10kΩ 1% 100Ω 1% 24.9kΩ 1% 6.98kΩ 1% 49.9kΩ 1% 0.1Ω 1% 1W Manufacturer NSC MURATA TDK TDK MURATA ZETEX FAIRCHILD FAIRCHILD VISHAY TDK VISHAY VISHAY VISHAY VISHAY VISHAY VISHAY VISHAY Part Number LM3409HVMY/ LM3409QHVMY GRM43ER72A225KA01L C1608X7R1C105K C1608X7R1H471K GRM188R71H222KA01D ZXMP10A18KTC FDC6333C FDS3672 SS3H10-E3/57T SLF12565T-150M4R2 CRCW06031R00FNEA CRCW060310K0FKEA CRCW0603100RFKEA CRCW060324K9FKEA CRCW06036K98FKEA CRCW060349K9FKEA WSL2512R1000FEA www.national.com 24 LM3409/LM3409HV/LM3409Q/LM3409QHV DESIGN #4: SINGLE POTENTIOMETER ANALOG DIMMING APPLICATION FOR 6 LEDS 30085622 Design #4 Bill of Materials Qty 1 2 1 1 1 1 1 1 1 1 1 1 1 1 Part ID LM3409/LM3409Q CIN1, CIN2 CF CF2 COFF CO Q1 D1 L1 ROFF RUV1 RUV2 RSNS RADJ Part Value Buck controller 2.2µF X7R 10% 50V 1.0µF X7R 10% 16V 0.1µF X7R 10% 16V 470pF X7R 10% 50V 1.0µF X7R 10% 50V PMOS 60V 3A Schottky 60V 2A 68 µH 20% 2A 25.5kΩ 1% 6.98kΩ 1% 49.9kΩ 1% 0.3Ω 1% 1W 250kΩ potentiometer Manufacturer NSC MURATA TDK TDK TDK MURATA ZETEX ST-MICRO TDK VISHAY VISHAY VISHAY VISHAY BOURNS Part Number LM3409MY/LM3409QMY GRM43ER71H225MA01L C1608X7R1C105K C1608X7R1C104K C1608X7R1H471K GRM32RR71H105KA01L ZXMP6A17GTA STPS2L60A SLF12565T-680M2R0 CRCW060325K5FKEA CRCW06036K98FKEA CRCW060349K9FKEA WSL2512R3000FEA 3352P-1-254 25 www.national.com LM3409/LM3409HV/LM3409Q/LM3409QHV DESIGN #5: 75°C THERMAL FOLDBACK APPLICATION FOR 16 LEDS 30085624 Design #5 Bill of Materials Qty 1 1 2 1 1 1 1 1 1 1 1 1 1 Part ID LM3409HV/ LM3409QHV U1 CIN1, CIN2 CF CF2 COFF Q1 D1 L1 ROFF RUV1 RUV2 RSNS Part Value Buck controller Analog Temperature Sensor 2.2µF X7R 10% 100V 1.0µF X7R 10% 16V 0.1µF X7R 10% 16V 470pF X7R 10% 50V PMOS 100V 3.8A Schottky 100V 3A 15 µH 20% 4.7A 24.9kΩ 1% 6.98kΩ 1% 49.9kΩ 1% 0.07Ω 1% 1W Manufacturer NSC NSC MURATA TDK TDK TDK ZETEX COMCHIP TDK VISHAY VISHAY VISHAY VISHAY Part Number LM3409HVMY/LM3409QHVMY LM94022 GRM43ER72A225KA01L C1608X7R1C105K C1608X7R1C104K C1608X7R1H471K ZXMP10A18KTC SS3H10-E3/57T SLF12575T-150M4R7 CRCW060324K9FKEA CRCW06036K98FKEA CRCW060349K9FKEA WSL2512R0700FEA *U2 could be replaced with a 500kΩ NTC thermistor connected from IADJ to GND. www.national.com 26 LM3409/LM3409HV/LM3409Q/LM3409QHV DESIGN #6: HIGH CURRENT APPLICATION FOR 4 LEDS 300856f4 Design #6 Bill of Materials Qty 1 2 1 1 1 1 1 1 1 1 1 1 1 1 Part ID LM3409/LM3409Q CIN1 CF CF2 COFF CO Q1 D1 L1 RF2 ROFF RUV1 RUV2 RSNS Part Value Buck controller 10µF X7R 10% 50V 1.0µF X7R 10% 16V 0.1µF X7R 10% 16V 470pF X7R 10% 50V 1.0µF X7R 10% 50V PMOS 30V 24A Schottky 30V 5A 15 µH 20% 7.5A 1.0kΩ 1% 23.2kΩ 1% 6.98kΩ 1% 49.9kΩ 1% 0.05Ω 1% 1W Manufacturer NSC TDK TDK TDK TDK MURATA ST-MICRO VISHAY COILCRAFT VISHAY VISHAY VISHAY VISHAY VISHAY Part Number LM3409MY/LM3409QMY C5750X7R1H106K C1608X7R1C105K C1608X7R1C104K C1608X7R1H471K GRM32RR71H105KA01L STD30PF03LT4 SSC53L-E3/57T DO5022P-153ML CRCW06031K00FKEA CRCW060323K2FKEA CRCW06036K98FKEA CRCW060349K9FKEA WSL2512R0500FEA *U2 could be replaced with a 500kΩ NTC thermistor connected from IADJ to GND. 27 www.national.com LM3409/LM3409HV/LM3409Q/LM3409QHV Physical Dimensions inches (millimeters) unless otherwise noted 10-Lead Exposed Pad Plastic eMSOP Package NS Package Number MUC10A www.national.com 28 LM3409/LM3409HV/LM3409Q/LM3409QHV Notes 29 www.national.com LM3409 / LM3409HV / LM3409Q / LM3409QHV PFET Buck Controller for High Power LED Drives Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Amplifiers Audio Clock and Timing Data Converters Interface LVDS Power Management Switching Regulators LDOs LED Lighting Voltage References PowerWise® Solutions Temperature Sensors PLL/VCO www.national.com/amplifiers www.national.com/audio www.national.com/timing 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