LM3475MF

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LM3475 SNVS239C – OCTOBER 2004 – REVISED OCTOBER 2015 LM3475 Hysteretic PFET Buck Controller 1 Features 3 Description • • • • The LM3475 is a hysteretic P-FET buck controller designed to support a wide range of high efficiency applications in a very small SOT-23-5 package. The hysteretic control scheme has several advantages, including simple system design with no external compensation, stable operation with a wide range of components, and extremely fast transient response. Hysteretic control also provides high efficiency operation, even at light loads. The PFET architecture allows for low component count as well as 100% duty cycle and ultra-low dropout operation. 1 • • • • Easy-to-Use Control Methodology 0.8 V to VIN Adjustable Output Range High Efficiency (90% Typical) ±0.9% (±1.5% Over Temperature) Feedback Voltage 100% Duty Cycle Capable Maximum Operating Frequency up to 2 MHz Internal Soft-Start Enable Pin Device Information(1) 2 Applications • • • • • • • PART NUMBER TFT Monitor Auto PC Vehicle Security Navigation Systems Notebook Standby Supply Battery Powered Portable Applications Distributed Power Systems LM3475 PACKAGE BODY SIZE (NOM) SOT-23 (5) 1.60 mm × 2.90 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application L1 10 PH Q1 Si2343 VIN = 5V VOUT = 2.5V/2A COUT CIN 10 PF D1 5 PGATE 4 VIN GND 2 CFF 1 nF LM3475 3 EN FB 100 PF RFB1 2.15k 1 RFB2 1k 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM3475 SNVS239C – OCTOBER 2004 – REVISED OCTOBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 4 5 6 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Ratings ........................... Thermal Information .................................................. Electrical Characteristics........................................... Typical Characteristics .............................................. Detailed Description .............................................. 8 7.1 Overview ................................................................... 8 7.2 Functional Block Diagram ......................................... 8 7.3 Feature Description................................................... 8 7.4 Device Functional Modes........................................ 10 8 Application and Implementation ........................ 11 8.1 Application Information............................................ 11 8.2 Typical Application ................................................. 11 9 Power Supply Recommendations...................... 16 10 Layout................................................................... 16 10.1 Layout Guidelines ................................................. 16 10.2 Layout Example .................................................... 17 11 Device and Documentation Support ................. 18 11.1 11.2 11.3 11.4 11.5 Device Support...................................................... Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 18 18 18 18 18 12 Mechanical, Packaging, and Orderable Information ........................................................... 18 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (March 2013) to Revision C • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1 Changes from Revision A (March 2013) to Revision B • 2 Page Page Changed layout of National Data Sheet to TI format. ........................................................................................................... 1 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: LM3475 LM3475 www.ti.com SNVS239C – OCTOBER 2004 – REVISED OCTOBER 2015 5 Pin Configuration and Functions DBV Package 5-Pin SOT-23 Top View 1 2 3 FB PGATE 5 GND 4 EN VIN Pin Functions PIN NAME NO. I/O DESCRIPTION FB 1 I Feedback input. Connect to a resistor divider between the output and GND. GND 2 G Ground. EN 3 O Enable. Pull this pin above 1.5 V (typical) for normal operation. When EN is low, the device enters shutdown mode. VIN 4 P Power supply input. PGATE 5 O Gate drive output for the external PFET. Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: LM3475 3 LM3475 SNVS239C – OCTOBER 2004 – REVISED OCTOBER 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings (1) (2) See MIN MAX UNIT VIN −0.3 16 V PGATE −0.3 16 V FB −0.3 5 V EN −0.3 16 V 440 mW Power dissipation (3) Lead temperature Tstg (1) (2) (3) Vapor phase (60 s) 215 Infrared (15 s) 220 −65 Storage temperature °C 1150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. The maximum allowable power dissipation is a function of the maximum junction temperature, TJ_MAX, the junction-to-ambient thermal resistance, θJA and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using: PD_MAX = (TJ_MAX - TA)/θJA. The maximum power dissipation of 0.44 W is determined using TA = 25°C, θJA = 225°C/W, and TJ_MAX = 125°C. 6.2 ESD Ratings over operating free-air temperature range (unless otherwise noted) V(ESD) (1) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) VALUE UNIT 2500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Ratings MIN TJ NOM MAX UNIT Supply voltage 2.7 10 V Operating junction temperature -40 125 °C 6.4 Thermal Information LM3475 THERMAL METRIC (1) DBV (SOT-23) UNIT 5 PINS RθJA Junction-to-ambient thermal resistance 164.2 °C/W RθJC(top) Junction-to-case (top) thermal resistance 115.3 °C/W RθJB Junction-to-board thermal resistance 27.0 °C/W ψJT Junction-to-top characterization parameter 12.8 °C/W ψJB Junction-to-board characterization parameter 26.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W (1) 4 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: LM3475 LM3475 www.ti.com SNVS239C – OCTOBER 2004 – REVISED OCTOBER 2015 6.5 Electrical Characteristics Typical limits are for TJ = 25°C, unless otherwise specified, VIN = EN = 5.0 V. Maximum and minimum specification limits are specified by design, test, or statistical analysis. PARAMETER IQ Quiescent current TEST CONDITIONS EN = VIN (PGATE Open) TJ = 25°C EN = 0V TJ = 25°C TJ = −40°C to +125°C TJ = −40°C to +125°C VFB Feedback voltage TJ = −40°C to +125°C 2.7 V < VIN < 10 V VHYST Comparator hysteresis 2.7 V < VIN < 10 V 170 VthEN 320 4 0.812 0.01 21 28 −40°C to +125°C 21 32 50 Increasing RPGATE IPGATE Enable leakage current Driver resistance Driver output current mV nA 600 TJ = 25°C −40°C to +125°C 1.5 1.2 1.8 365 TJ = 25°C EN = 10 V V %/V TJ = 25°C TJ = 25°C µA 10 0.788 Hysteresis IEN UNIT 7 −40°C to +125°C Enable threshold voltage MAX 0.8 Feedback voltage line regulation FB bias current TYP 260 TJ = 25°C %ΔVFB/ΔVIN IFB MIN mV 0.025 −40°C to +125°C 1 Source ISOURCE = 100 mA 2.8 Sink ISink = 100 mA 1.8 V µA Ω Source VPGATE = 3.5 V CPGATE = 1 nF 0.475 Sink VPGATE = 3.5 V CPGATE = 1 nF 1.0 A TSS Soft-start time 2.7 V < VIN < 10 V (EN Rising) TONMIN Minimum on-time PGATE Open VUVD Undervoltage detection Measured at the FB Pin TJ = 25°C −40°C to +125°C 4 ms 180 ns 0.56 0.487 0.613 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: LM3475 V 5 LM3475 SNVS239C – OCTOBER 2004 – REVISED OCTOBER 2015 www.ti.com 6.6 Typical Characteristics Unless specified otherwise, all curves taken at VIN = 5 V, VOUT = 2.5 V, L = 10 µH, COUT = 100 µF, ESR = 100 mΩ, and TA = 25°C. Figure 1. Quiescent Current vs Input Voltage Figure 2. Feedback Voltage vs Temperature Figure 3. Hysteresis Voltage vs Input Voltage Figure 4. Hysteresis Voltage vs Temperature 100 98 96 EFFICIENCY (%) EFFICIENCY (%) 80 94 92 90 88 60 40 20 86 0 84 0.5 1 1.5 4 2 OUTPUT CURRENT (A) 5 6 7 8 9 10 INPUT VOLTAGE (VIN) IOUT = 2 A Figure 5. Efficiency vs Load Current 6 Submit Documentation Feedback Figure 6. Efficiency vs Input Voltage Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: LM3475 LM3475 www.ti.com SNVS239C – OCTOBER 2004 – REVISED OCTOBER 2015 Typical Characteristics (continued) VSW 2.5V/DIV VRIPPLE 20 mV/DIV VIN 2V/DIV VOUT 1V/DIV Unless specified otherwise, all curves taken at VIN = 5 V, VOUT = 2.5 V, L = 10 µH, COUT = 100 µF, ESR = 100 mΩ, and TA = 25°C. 1 ms/DIV 2 Ps/DIV Figure 7. Start Up Figure 8. Output Ripple Voltage Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: LM3475 7 LM3475 SNVS239C – OCTOBER 2004 – REVISED OCTOBER 2015 www.ti.com 7 Detailed Description 7.1 Overview The LM3475 is a buck (step-down) DC-DC controller that uses a hysteretic control architecture, which results in Pulse Frequency Modulated (PFM) regulation. The hysteretic control scheme does not utilize an internal oscillator. Switching frequency depends on external components and operating conditions. Operating frequency decreases at light loads, resulting in excellent efficiency compared to PWM architectures. Because switching is directly controlled by the output conditions, hysteretic control provides exceptional load transient response. 7.2 Functional Block Diagram reset Internal Regulator Level Shift PGATE UVD-Disable + VCC EN Pdrive en VIN en UVD Comp Blanking Timer FB UVD-Disable 70% VREF Band Gap Reference Hysteretic Comp + - VREF Vref Ramp Current Bias reset Soft-Start GND 7.3 Feature Description 7.3.1 Hysteretic Control Circuit The LM3475 uses a comparator-based voltage control loop. The voltage on the feedback pin is compared to a 0.8V reference with 21mV of hysteresis. When the FB input to the comparator falls below the reference voltage, the output of the comparator goes low. This results in the driver output, PGATE, pulling the gate of the PFET low and turning on the PFET. With the PFET on, the input supply charges COUT and supplies current to the load through the PFET and the inductor. Current through the inductor ramps up linearly, and the output voltage increases. As the FB voltage reaches the upper threshold (reference voltage plus hysteresis) the output of the comparator goes high, and the PGATE turns the PFET off. When the PFET turns off, the catch diode turns on, and the current through the inductor ramps down. As the output voltage falls below the reference voltage, the cycle repeats. The resulting output, inductor current, and switch node waveforms are shown in Figure 9. 8 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: LM3475 LM3475 www.ti.com SNVS239C – OCTOBER 2004 – REVISED OCTOBER 2015 Feature Description (continued) VIN tON tOFF -VD Switch Voltage Iout 'IL Inductor Current td VOUT VOUT ripple (DC) VHYST td Output Voltage Figure 9. Hysteretic Waveforms 7.3.2 Soft-Start The LM3475 includes an internal soft-start function to protect components from excessive inrush current and output voltage overshoot. As VIN rises above 2.7 V (typical), the internal bias circuitry becomes active. When EN goes high, the device enters soft-start. During soft-start, the reference voltage is ramped up to the nominal value of 0.8 V in approximately 4ms. Duty cycle and output voltage will increase as the reference voltage is ramped up. 7.3.3 Under Voltage Detection When the output voltage falls below 70% (typical) of the normal voltage, as measured at the FB pin, the device turns off PFET and restarts a new soft-start cycle. In short circuit, the PFET is always on, and the converter is effectively a resistor divider from input to output to ground. Whether the part restarts depends on the power path resistance and the short circuit resistance. This feature should not be considered as overcurrent protection or output short circuit protection. 7.3.4 PGATE During switching, the PGATE pin swings from VIN (off) to ground (on). As input voltage increases, the time it takes to slew the gate of the PFET on and off also increases. Also, as the PFET gate voltage approaches VIN, the PGATE current driving capability decreases. This can cause a significant additional delay in turning the switch off when using a PFET with a low threshold voltage. These two effects will increase power dissipation and reduce efficiency. Therefore, a PFET with relatively high threshold voltage and low gate capacitance is recommended. 7.3.5 Minimum On or Off Time To ensure accurate comparator switching, the LM3475 imposes a blanking time after each comparator state change. This blanking time is 180 ns typically. Immediately after the comparator goes high or low, it will be held in that state for the duration of the blanking time. This helps keep the hysteretic comparator from improperly responding to switching noise spikes (See Reducing Switching Noise) and ESL spikes (See Output Capacitor Selection) at the output. At very low or very high duty cycle operation, maximum frequency will be limited by the blanking time. The maximum operating frequency can be determined by the following equations: FMAX = D / tonmin FMAX = (1-D) / toffmin (1) where Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: LM3475 9 LM3475 SNVS239C – OCTOBER 2004 – REVISED OCTOBER 2015 www.ti.com Feature Description (continued) • • D is the duty cycle, defined as VOUT/VIN, and tonmin toffmin is the sum of the blanking time, the propagation delay time, and the PFET delay time (see Figure 9) (2) 7.3.6 Enable Pin (EN) The LM3475 provides a shutdown function via the EN pin to disable the device. The device is active when the EN pin is pulled above 1.5 V (typ) and in shutdown mode when EN is below 1.135 V (typ). In shutdown mode, total quiescent current is less than 10 µA. The EN pin can be directly connected to VIN for always-on operation. 7.4 Device Functional Modes The LM3475 operates in discontinuous conduction mode at light load current and continuous conduction mode at heavy load current. In discontinuous conduction mode, current through the inductor starts at zero and ramps up to the peak, then ramps down to zero. The next cycle starts when the FB voltage reaches the reference voltage. Until then, the inductor current remains zero. Operating frequency is low, as are switching losses. In continuous conduction mode, current always flows through the inductor and never ramps down to zero. 10 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: LM3475 LM3475 www.ti.com SNVS239C – OCTOBER 2004 – REVISED OCTOBER 2015 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LM3475 employs a hysteretic control architecture; which provides excellent load transient response and efficiency even at light loads, as compared to its PWM architectures. No external compensation is required which results in a simple design and low component count. A typical schematic is described in the next section. 8.2 Typical Application L1 10 PH Q1 Si2343 VIN = 5V VOUT = 2.5V/2A COUT CIN 10 PF D1 5 PGATE 4 VIN GND 2 CFF 1 nF LM3475 3 EN FB 100 PF RFB1 2.15k 1 RFB2 1k Figure 10. Full Demo Board Schematic 8.2.1 Design Requirements To properly size the components for the application, the designer needs the following parameters: input voltage range, output voltage, output current range, and required switching frequency. These four main parameters affect the choices of component available to achieve a proper system behavior. Although hysteretic control is a simple control scheme, the operating frequency and other performance characteristics depend on external conditions and components. If the inductance, output capacitance, ESR, VIN, or Cff is changed, there will be a change in the operating frequency and possibly output ripple. Therefore, care must be taken to select components which will provide the desired operating range. 8.2.2 Detailed Design Procedure Table 1. Bill of Materials DESIGNATOR DESCRIPTION PART NUMBER VENDOR CIN 10 µF, 16 V, X5R EMK325BJ106MN TAIYO YUDEN COUT 100 µF, 6 V, Ta TPSY107M006R0100 AVX CFF 1 nF, 25 V, X7R VJ1206Y102KXXA Vishay D1 Schottky, 20 V, 2 A CMSH2-20L Central Semiconductor L1 10 µH, 3.1 A CDRH103R100 Sumida Q1 30 V, 2.5 A Si2343 Vishay RFB2 1 kΩ, 0805, 1% CRW08051001F Vishay RFB1 2.15 kΩ, 0805, 1% CRCW08052151F Vishay Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: LM3475 11 LM3475 SNVS239C – OCTOBER 2004 – REVISED OCTOBER 2015 www.ti.com 8.2.2.1 Setting Output Voltage The output voltage is programmed using a resistor divider between VOUT and GND as shown in Figure 11. The feedback resistors can be calculated as follows: R 1 + R2 VOUT = R2 x VFB where • Vfb is 0.8 V typically (3) The feedback resistor ratio, α = (R1+R2) / R2, will also be used below to calculate output ripple and operating frequency. PGATE VOUT L PMOS_drv + COUT Cff R1 FB + - R2 Hyst Comp + - Reference Voltage VHYST = 21 mV VFB = 0.8V PGATE Figure 11. Hysteretic Window 8.2.2.2 Setting Operating Frequency and Output Ripple Although hysteretic control is a simple control scheme, the operating frequency and other performance characteristics depend on external conditions and components. If the inductance, output capacitance, ESR, VIN, or Cff is changed, there will be a change in the operating frequency and possibly output ripple. Therefore, care must be taken to select components which will provide the desired operating range. The best approach is to determine what operating frequency is desirable in the application and then begin with the selection of the inductor and output capacitor ESR. The design process usually involves a few iterations to select appropriate standard values that will result in the desired frequency and ripple. Without the feedforward capacitor (Cff), the operating frequency (F) can be approximately calculated using the formula: VOUT F= VIN (VIN - VOUT) x ESR x (VHYST x D x L) + (VIN x delay x ESR) where • • Delay is the sum of the LM3475 propagation delay time and the PFET delay time The propagation delay is 90ns typically (4) Minimum output ripple voltage can be determined using the following equation: VOUT_PP = VHYST ( R1 + R2 ) / R2 12 (5) Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: LM3475 LM3475 www.ti.com SNVS239C – OCTOBER 2004 – REVISED OCTOBER 2015 8.2.2.3 Using a Feed-forward Capacitor The operating frequency and output ripple voltage can also be significantly influenced using a speed up capacitor, Cff, as shown in Figure 11. Cff is connected in parallel with the high side feedback resistor, R1. The output ripple causes a current to be sourced or sunk through this capacitor. This current is essentially a square wave. Since the input to the feedback pin (FB) is a high impedance node, the bulk of the current flows through R2. This superimposes a square wave ripple voltage on the FB node. The end result is a reduction in output ripple and an increase in operating frequency. When adding Cff, calculate the formula above with α= 1. The value of Cff depends on the desired operating frequency and the value of R2. A good starting point is 1nF ceramic at 100kHz decreasing linearly with increased operating frequency. Also note that as the output voltage is programmed below 1.6V, the effect of Cff will decrease significantly. 8.2.2.4 Inductor Selection The most important parameters for the inductor are the inductance and the current rating. The LM3475 operates over a wide frequency range and can use a wide range of inductance values. Minimum inductance can be calculated using the following equation: VIN - VSD - VOUT x L= 'I D F where • • D is the duty cycle, defined as VOUT/VIN ΔI is the allowable inductor ripple current (6) Maximum allowable inductor ripple current should be calculated as a function of output current (IOUT) as shown below: ΔImax = IOUT x 0.3 The inductor must also be rated to handle the peak current (IPK) and RMS current given by: IPK = (IOUT + ΔI/2) x 1.1 (7) 2 IRMS = IOUT2 + 'I 3 (8) The inductance value and the resulting ripple is one of the key parameters controlling operating frequency. 8.2.2.5 Output Capacitor Selection Once the desired operating frequency and inductance value are selected, ESR must be selected based on Equation 4. This process may involve a few iterations to select standard ESR and inductance values. In general, the ESR of the output capacitor and the inductor ripple current create the output ripple of the regulator. However, the comparator hysteresis sets the first order value of this ripple. Therefore, as ESR and ripple current vary, operating frequency must also vary to keep the output ripple voltage regulated. The hysteretic control topology is well suited to using ceramic output capacitors. However, ceramic capacitors have a very low ESR, resulting in a 90° phase shift of the output voltage ripple. This results in low operating frequency and increased output ripple. To fix this problem a low value resistor could be added in series with the ceramic output capacitor. Although counter intuitive, this combination of a ceramic capacitor and external series resistance provide highly accurate control over the output voltage ripple. Another method is to add an external ramp at the FB pin as shown in Figure 12. By proper selection of R1 and C2, the FB pin sees faster voltage change than the output ripple can cause. As a result, the switching frequency is higher while the output ripple becomes lower. The switching frequency is approximately: VIN F= 2S x R1 x C2 x VHYS (9) Other types of capacitor, such as Sanyo POSCAP, OS-CON, and Nichicon ’NA’ series are also recommended and may be used without additional series resistance. For all practical purposes, any type of output capacitor may be used with proper circuit verification. Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: LM3475 13 LM3475 SNVS239C – OCTOBER 2004 – REVISED OCTOBER 2015 www.ti.com Capacitors with high ESL (equivalent series inductance) values should not be used. As shown in Figure 9, the output ripple voltage contains a small step at both the high and low peaks. This step is caused by and is directly proportional to the output capacitor’s ESL. A large ESL, such as in an electrolytic capacitor, can create a step large enough to cause abnormal switching behavior. 8.2.2.6 Input Capacitor Selection A bypass capacitor is required between VIN and ground. It must be placed near the source of the external PFET. The input capacitor prevents large voltage transients at the input and provides the instantaneous current when the PFET turns on. The important parameters for the input capacitor are the voltage rating and the RMS current rating. Follow the manufacturer’s recommended voltage de-rating. RMS current and power dissipation (PD) can be calculated with the equations below: IOUT IRMS_CIN = VIN VOUT x (VIN - VOUT) (10) L1 10 PH Q1 Si2343 VIN VOUT = 0.9V/2A COUT CIN 10 PF D1 5 4 PGATE VIN GND 100 PF 2 EN RFB1 1.27k C1 3.9 nF LM3475 3 R1 200k FB 1 C2 390 pF RFB2 10k Figure 12. External Ramp 8.2.2.7 Diode Selection The catch diode provides the current path to the load during the PFET off time. Therefore, the current rating of the diode must be higher than the average current through the diode, which be calculated as shown: ID_AVE = IOUT x (1 − D) (11) The peak voltage across the catch diode is approximately equal to the input voltage. Therefore, the diode’s peak reverse voltage rating should be greater than 1.3 times the input voltage. A Schottky diode is recommended, since a low forward voltage drop will improve efficiency. For high temperature applications, diode leakage current may become significant and require a higher reverse voltage rating to achieve acceptable performance. 8.2.2.8 P-Channel MOSFET Selection The PFET switch should be selected based on the maximum Drain-Source voltage (VDS), Drain current rating (ID), maximum Gate-Source voltage (VGS), on resistance (RDSON), and Gate capacitance. The voltage across the PFET when it is turned off is equal to the sum of the input voltage and the diode forward voltage. The VDS must be selected to provide some margin beyond the sum of the input voltage and Vd. Since the current flowing through the PFET is equal to the current through the inductor, ID must be rated higher than the maximum IPK. During switching, PGATE swings the PFET’s gate from VIN to ground. Therefore, A PFET must be selected with a maximum VGS larger than VIN. To insure that the PFET turns on completely and quickly, refer to the PGATE section. 14 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: LM3475 LM3475 www.ti.com SNVS239C – OCTOBER 2004 – REVISED OCTOBER 2015 The power loss in the PFET consists of switching losses and conducting losses. Although switching losses are difficult to precisely calculate, the equation below can be used to estimate total power dissipation. Increasing RDSON will increase power losses and degrade efficiency. Note that switching losses will also increase with lower gate threshold voltages. PDswitch = RDSONx (IOUT)2x D + F x IOUTx VINx (ton + toff)/2 where • • • ton = FET turn on time toff = FET turn off time A value of 10ns to 50ns is typical for ton and toff (12) Note that the RDSON has a positive temperature coefficient. At 100°C, the RDSON may be as much as 150% higher than the value at 25°C. The Gate capacitance of the PFET has a direct impact on both PFET transition time and the power dissipation in the LM3475. Most of the power dissipated in the LM3475 is used to drive the PFET switch. This power can be calculated as follows: The amount of average gate driver current required during switching (IG) is: IG = Qg x F (13) And the total power dissipated in the device is: IqVIN + IGVIN where • Iq is typically 260µA as shown in Electrical Characteristics (14) As gate capacitance increases, operating frequency may need to be reduced, or additional heat sinking may be required to lower the power dissipation in the device. In general, keeping the gate capacitance below 2000 pF is recommended to keep transition times (switching losses), and power losses low. 8.2.2.9 Reducing Switching Noise Although the LM3475 employs internal noise suppression circuitry, external noise may continue to be excessive. There are several methods available to reduce noise and EMI. MOSFETs are very fast switching devices. The fast increase in PFET current coupled with parasitic trace inductance can create unwanted noise spikes at both the switch node and at VIN. Switching noise will increase with load current and input voltage. This noise can also propagate through the ground plane, sometimes causing unpredictable device performance. Slowing the rise and fall times of the PFET can be very effective in reducing this noise. Referring to Figure 13, the PFET can be slowed down by placing a small (1-Ω to 10-Ω) resistor in series with PGATE. However, this resistor will increase the switching losses in the PFET and will lower efficiency. Therefore it should be kept as small as possible and only used when necessary. Another method to reduce switching noise (other than good PCB layout, see Layout) is to use a small RC filter or snubber. The snubber should be placed in parallel with the catch diode, connected close to the drain of the PFET, as shown in Figure 13. Again, the snubber should be kept as small as possible to limit its impact on system efficiency. A typical range is a 10-Ω to 100-Ω resistor and a 470-pF to 2.2-nF ceramic capacitor. 5 RPGATE Q1 PGATE 3.3: L1 CSNUB D1 RSNUB Figure 13. PGATE Resistor and Snubber Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: LM3475 15 LM3475 SNVS239C – OCTOBER 2004 – REVISED OCTOBER 2015 www.ti.com 8.2.3 Application Curves Figure 14. Load Transient Response with External Ramp (Circuit from Figure 12) Figure 15. Load Transient Response (Typical Application Circuit from Figure 16) 9 Power Supply Recommendations The LM3475 controller is designed to operate from various DC power supplies. VIN input should be protected from reversal voltage and voltage dump over 16 volts. The impedance of the input supply rail should be low enough that the input current transient does not cause drop below VIN UVLO level. If the input supply is connected by using long wires, additional bulk capacitance may be required in addition to normal input capacitor. 10 Layout 10.1 Layout Guidelines PC board layout is very important in all switching regulator designs. Poor layout can cause EMI problems, excess switching noise and poor operation. As shown in Figure 16, place the ground of the input capacitor as close as possible to the anode of the diode. This path also carries a large AC current. The switch node, the node connecting the diode cathode, inductor, and PFET drain, should be kept as small as possible. This node is one of the main sources for radiated EMI. The feedback pin is a high impedance node and is therefore sensitive to noise. Be sure to keep all feedback traces away from the inductor and the switch node, which are sources of noise. Also, the resistor divider should be placed close to the FB pin. The gate pin of the external PFET should be located close to the PGATE pin. TI also recommends using a large, continuous ground plane, particularly in higher current applications. 16 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: LM3475 LM3475 www.ti.com SNVS239C – OCTOBER 2004 – REVISED OCTOBER 2015 10.2 Layout Example Q1 Cout D1 Cin GND RFB2 RFB1 L1 CFF 0Ω Vout EN Vin Figure 16. Layout Example (2:1 Scale) Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: LM3475 17 LM3475 SNVS239C – OCTOBER 2004 – REVISED OCTOBER 2015 www.ti.com 11 Device and Documentation Support 11.1 Device Support 11.1.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 18 Submit Documentation Feedback Copyright © 2004–2015, Texas Instruments Incorporated Product Folder Links: LM3475 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) LM3475MF/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 S65B LM3475MFX/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 S65B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of