LM3475

LM3475 Hysteretic PFET Buck Controller October 2004 LM3475 Hysteretic PFET Buck Controller General Description The LM3475 is a hysteretic P-FET buck controller designed to support a wide range of high efficiency applications in a very small SOT23-5 package. The hysteretic control scheme has several advantages, including simple system design with no external compensation, stable operation with a wide range of components, and extremely fast transient response. Hysteretic control also provides high efficiency operation, even at light loads. The PFET architecture allows for low component count as well as 100% duty cycle and ultralow dropout operation. Features n n n n n n n n n Easy to use control methodology 0.8V to VIN adjustable output range High Efficiency (90% typical) ± 0.9% ( ± 1.5% over temp) feedback voltage 100% duty cycle capable Maximum operating frequency up to 2MHz Internal Soft-Start Enable pin SOT23-5 package Applications n n n n n n n TFT Monitor Auto PC Vehicle Security Navigation Systems Notebook Standby Supply Battery Powered Portable Applications Distributed Power Systems Typical Application Circuit 20070101 © 2004 National Semiconductor Corporation DS200701 www.national.com LM3475 Connection Diagram Top View 20070102 5 Lead Plastic SOT23-5 NS package Number MF05A Package Marking and Ordering Information Order Number LM3475MF LM3475MFX Package Type SOT23-5 SOT23-5 Package Marking S65B S65B Supplied As: 1000 units on Tape and Reel 3000 units on Tape and Reel Pin Description Pin Name FB GND EN VIN PGATE Pin Number 1 2 3 4 5 Description Feedback input. Connect to a resistor divider between the output and GND. Ground. Enable. Pull this pin above 1.5V (typical) for normal operation. When EN is low, the device enters shutdown mode. Power supply input. Gate drive output for the external PFET. www.national.com 2 LM3475 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VIN PGATE FB EN Storage Temperature Power Dissipation (Note 2) ESD Susceptibilty Human Body Model (Note 3) −0.3V to 16V −0.3V to 16V −0.3V to 5V −0.3V to 16V −65˚C to 150˚C 440mW 2.5kV Lead Temperature Vapor Phase (60 sec.) Infared (15 sec.) 215˚C 220˚C Operating Ratings (Note 1) Supply Voltage Operating Junction Temperature 2.7V to 10V −40˚C to +125˚C Electrical Characteristics Specifications in Standard type face are for TJ = 25˚C, and in bold type face apply over the full Operating Temperature Range (TJ = −40˚C to +125˚C). Unless otherwise specified, VIN = EN = 5.0V. Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Symbol IQ Parameter Quiescent Current Conditions EN = VIN (PGATE Open) EN = 0V VFB %∆VFB/∆VIN VHYST IFB VthEN IEN Feedback Voltage Feedback Voltage Line Regulation Comparator Hysteresis FB Bias Current Enable Threshold Voltage Hysteresis Enable Leakage Current EN = 10V Source ISOURCE = 100mA Sink ISink = 100mA Source VPGATE = 3.5V CPGATE = 1nF Sink VPGATE = 3.5V CPGATE = 1nF 2.7V < VIN < 10V (EN Rising) PGATE Open Measured at the FB Pin 0.487 Increasing 1.2 2.7V < VIN < 10V 2.7V < VIN < 10V −40˚C to +125˚C Min 170 4 0.788 Typ 260 7 0.8 0.01 21 21 50 1.5 365 .025 2.8 Ω 1.8 1 28 32 600 1.8 Max 320 10 0.812 V %/V mV nA V mV µA Unit µA RPGATE Driver Resistance 0.475 A 1.0 IPGATE Driver Output Current TSS TONMIN VUVD Soft-Start Time Minimum On-Time Under Voltage Detection 4 180 0.56 0.613 ms ns V 3 www.national.com LM3475 Electrical Characteristics (Continued) Note 1: Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is intended to be functional, but device parameter specifications may not be guaranteed. For guaranteed specifications and test conditions, see the Electrical Characteristics. Note 2: The maximum allowable power dissipation is a function of the maximum junction temperature, TJ_MAX, the junction-to-ambient thermal resistance, θJA and the ambient temperature, TA. The maximum allowable power dissipation at any ambient temperature is calculated using: PD_MAX = (TJ_MAX - TA)/θJA. The maximum power dissipation of 0.44W is determined using TA = 25˚C, θJA = 225˚C/W, and TJ_MAX = 125˚C. Note 3: The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. www.national.com 4 LM3475 Typical Performance Characteristics Unless specified otherwise, all curves taken at VIN = 5V, VOUT = 2.5V, L = 10 µH, COUT = 100 µF, ESR = 100mΩ, and TA = 25˚C. Quiescent Current vs Input Voltage Feedback Voltage vs Temperature 20070122 20070123 Hysteresis Voltage vs Input Voltage Hysteresis Voltage vs Temperature 20070124 20070125 Efficiency vs Load Current Efficiency vs Input Voltage IOUT = 2A 20070126 20070127 5 www.national.com LM3475 Typical Performance Characteristics Unless specified otherwise, all curves taken at VIN = 5V, VOUT = 2.5V, L = 10 µH, COUT = 100 µF, ESR = 100mΩ, and TA = 25˚C. (Continued) Start Up Output Ripple Voltage 20070128 20070129 Load Transient Response with External Ramp (Circuit from Figure 3) Load Transient Response (Typical Application Circuit from Figure 5) 20070131 20070132 www.national.com 6 LM3475 Block Diagram 20070103 Operation Description OVERVIEW The LM3475 is a buck (step-down) DC-DC controller that uses a hysteretic control architecture, which results in Pulse Frequency Modulated (PFM) regulation. The hysteretic control scheme does not utilize an internal oscillator. Switching frequency depends on external components and operating conditions. Operating frequency decreases at light loads, resulting in excellent efficiency compared to PWM architectures. Because switching is directly controlled by the output conditions, hysteretic control provides exceptional load transient response. HYSTERETIC CONTROL CIRCUIT The LM3475 uses a comparator-based voltage control loop. The voltage on the feedback pin is compared to a 0.8V reference with 21mV of hysteresis. When the FB input to the comparator falls below the reference voltage, the output of the comparator goes low. This results in the driver output, PGATE, pulling the gate of the PFET low and turning on the PFET. With the PFET on, the input supply charges COUT and supplies current to the load through the PFET and the inductor. Current through the inductor ramps up linearly, and the output voltage increases. As the FB voltage reaches the upper threshold (reference voltage plus hysteresis) the output of the comparator goes high, and the PGATE turns the PFET off. When the PFET turns off, the catch diode turns on, and the current through the inductor ramps down. As the output voltage falls below the reference voltage, the cycle repeats. The resulting output, inductor current, and switch node waveforms are shown in Figure 1. 20070104 FIGURE 1. Hysteretic Waveforms The LM3475 operates in discontinuous conduction mode at light load current and continuous conduction mode at heavy load current. In discontinuous conduction mode, current through the inductor starts at zero and ramps up to the peak, then ramps down to zero. The next cycle starts when the FB voltage reaches the reference voltage. Until then, the inductor current remains zero. Operating frequency is low, as are switching losses. In continuous conduction mode, current always flows through the inductor and never ramps down to zero. SOFT-START The LM3475 includes an internal soft-start function to protect components from excessive inrush current and output voltage overshoot. As VIN rises above 2.7V (typical), the internal bias circuitry becomes active. When EN goes high, the 7 www.national.com LM3475 Operation Description (Continued) MINIMUM ON/OFF TIME To ensure accurate comparator switching, the LM3475 imposes a blanking time after each comparator state change. This blanking time is 180ns typically. Immediately after the comparator goes high or low, it will be held in that state for the duration of the blanking time. This helps keep the hysteretic comparator from improperly responding to switching noise spikes (See Reducing Switching Noise) and ESL spikes (See Output Capacitor Selection) at the output. At very low or very high duty cycle operation, maximum frequency will be limited by the blanking time. The maximum operating frequency can be determined by the following equations: FMAX = D / tonmin FMAX = (1-D) / toffmin Where D is the duty cycle, defined as VOUT/VIN, and tonmin and toffmin is the sum of the blanking time, the propagation delay time and the PFET delay time (see Figure 1). ENABLE PIN (EN) The LM3475 provides a shutdown function via the EN pin to disable the device. The device is active when the EN pin is pulled above 1.5V (typ) and in shutdown mode when EN is below 1.135V (typ). In shutdown mode, total quiescent current is less than 10µA. The EN pin can be directly connected to VIN for always-on operation. device enters soft-start. During soft-start, the reference voltage is ramped up to the nominal value of 0.8V in approximately 4ms. Duty cycle and output voltage will increase as the reference voltage is ramped up. UNDER VOLTAGE DETECTION When the output voltage falls below 70% (typical) of the normal voltage, as measured at the FB pin, the device turns off PFET and restarts a new soft-start cycle. In short circuit, the PFET is always on, and the converter is effectively a resistor divider from input to output to ground. Whether the part restarts depends on the power path resistance and the short circuit resistance. This feature should not be considered as overcurrent protection or output short circuit protection. PGATE During switching, the PGATE pin swings from VIN (off) to ground (on). As input voltage increases, the time it takes to slew the gate of the PFET on and off also increases. Also, as the PFET gate voltage approaches VIN, the PGATE current driving capability decreases. This can cause a significant additional delay in turning the switch off when using a PFET with a low threshold voltage. These two effects will increase power dissipation and reduce efficiency. Therefore, a PFET with relatively high threshold voltage and low gate capacitance is recommended. www.national.com 8 LM3475 Design Information SETTING OUTPUT VOLTAGE The output voltage is programmed using a resistor divider between VOUT and GND as shown in Figure 2. The feedback resistors can be calculated as follows: Where delay is the sum of the LM3475 propagation delay time and the PFET delay time. The propagation delay is 90ns typically. Minimum output ripple voltage can be determined using the following equation: VOUT_PP = VHYST ( R1 + R2 ) / R2 USING A FEED-FORWARD CAPACITOR Where Vfb is 0.8V typically. The feedback resistor ratio, α = (R1+R2) / R2, will also be used below to calculate output ripple and operating frequency. The operating frequency and output ripple voltage can also be significantly influenced using a speed up capacitor, Cff, as shown in Figure 2. Cff is connected in parallel with the high side feedback resistor, R1. The output ripple causes a current to be sourced or sunk through this capacitor. This current is essentially a square wave. Since the input to the feedback pin (FB) is a high impedance node, the bulk of the current flows through R2. This superimposes a square wave ripple voltage on the FB node. The end result is a reduction in output ripple and an increase in operating frequency. When adding Cff, calculate the formula above with α= 1. The value of Cff depends on the desired operating frequency and the value of R2. A good starting point is 1nF ceramic at 100kHz decreasing linearly with increased operating frequency. Also note that as the output voltage is programmed below 1.6V, the effect of Cff will decrease significantly. INDUCTOR SELECTION The most important parameters for the inductor are the inductance and the current rating. The LM3475 operates over a wide frequency range and can use a wide range of inductance values. Minimum inductance can be calculated using the following equation: 20070115 FIGURE 2. Hysteretic Window SETTING OPERATING FREQUENCY AND OUTPUT RIPPLE Although hysteretic control is a simple control scheme, the operating frequency and other performance characteristics depend on external conditions and components. If the inductance, output capacitance, ESR, VIN, or Cff is changed, there will be a change in the operating frequency and possibly output ripple. Therefore, care must be taken to select components which will provide the desired operating range. The best approach is to determine what operating frequency is desirable in the application and then begin with the selection of the inductor and output capacitor ESR. The design process usually involves a few iterations to select appropriate standard values that will result in the desired frequency and ripple. Without the feedforward capacitor (Cff), the operating frequency (F) can be approximately calculated using the formula: Where D is the duty cycle, defined as VOUT/VIN, and ∆I is the allowable inductor ripple current. Maximum allowable inductor ripple current should be calculated as a function of output current (IOUT) as shown below: ∆Imax = IOUT x 0.3 The inductor must also be rated to handle the peak current (IPK) and RMS current given by: IPK = (IOUT + ∆I/2) x 1.1 The inductance value and the resulting ripple is one of the key parameters controlling operating frequency. OUTPUT CAPACITOR SELECTION Once the desired operating frequency and inductance value are selected, ESR must be selected based on the equation in the Setting Operating Frequency and Output Ripple. This process may involve a few iterations to select standard ESR and inductance values. In general, the ESR of the output capacitor and the inductor ripple current create the output ripple of the regulator. However, the comparator hysteresis sets the first order value of this ripple. Therefore, as ESR and ripple current vary, operating frequency must also vary to keep the output ripple 9 www.national.com LM3475 Design Information (Continued) voltage regulated. The hysteretic control topology is well suited to using ceramic output capacitors. However, ceramic capacitors have a very low ESR, resulting in a 90˚ phase shift of the output voltage ripple. This results in low operating frequency and increased output ripple. To fix this problem a low value resistor could be added in series with the ceramic output capacitor. Although counter intuitive, this combination of a ceramic capacitor and external series resistance provide highly accurate control over the output voltage ripple. Another method is to add an external ramp at the FB pin as shown in Figure 3. By proper selection of R1 and C2, the FB pin sees faster voltage change than the output ripple can cause. As a result, the switching frequency is higher while the output ripple becomes lower. The switching frequency is approximately: Capacitors with high ESL (equivalent series inductance) values should not be used. As shown in Figure 1, the output ripple voltage contains a small step at both the high and low peaks. This step is caused by and is directly proportional to the output capacitor’s ESL. A large ESL, such as in an electrolytic capacitor, can create a step large enough to cause abnormal switching behavior. INPUT CAPACITOR SELECTION A bypass capacitor is required between VIN and ground. It must be placed near the source of the external PFET. The input capacitor prevents large voltage transients at the input and provides the instantaneous current when the PFET turns on. The important parameters for the input capacitor are the voltage rating and the RMS current rating. Follow the manufacturer’s recommended voltage de-rating. RMS current and power dissipation (PD) can be calculated with the equations below: Other types of capacitor, such as Sanyo POSCAP, OS-CON, and Nichicon ’NA’ series are also recommended and may be used without additional series resistance. For all practical purposes, any type of output capacitor may be used with proper circuit verification. 20070120 FIGURE 3. External Ramp DIODE SELECTION The catch diode provides the current path to the load during the PFET off time. Therefore, the current rating of the diode must be higher than the average current through the diode, which be calculated as shown: ID_AVE = IOUT x (1 − D) The peak voltage across the catch diode is approximately equal to the input voltage. Therefore, the diode’s peak reverse voltage rating should be greater than 1.3 times the input voltage. A Schottky diode is recommended, since a low forward voltage drop will improve efficiency. For high temperature applications, diode leakage current may become significant and require a higher reverse voltage rating to achieve acceptable performance. www.national.com 10 P-CHANNEL MOSFET SELECTION The PFET switch should be selected based on the maximum Drain-Source voltage (VDS), Drain current rating (ID), maximum Gate-Source voltage (VGS), on resistance (RDSON), and Gate capacitance. The voltage across the PFET when it is turned off is equal to the sum of the input voltage and the diode forward voltage. The VDS must be selected to provide some margin beyond the sum of the input voltage and Vd. Since the current flowing through the PFET is equal to the current through the inductor, ID must be rated higher than the maximum IPK. During switching, PGATE swings the PFET’s gate from VIN to ground. Therefore, A PFET must be selected with a maximum VGS larger than VIN. To insure that the PFET turns on completely and quickly, refer to the PGATE section. LM3475 Design Information (Continued) The power loss in the PFET consists of switching losses and conducting losses. Although switching losses are difficult to precisely calculate, the equation below can be used to estimate total power dissipation. Increasing RDSON will increase power losses and degrade efficiency. Note that switching losses will also increase with lower gate threshold voltages. PDswitch = RDSONx (IOUT)2x D + F x IOUTx VINx (ton + toff)/2 where: ton = FET turn on time toff = FET turn off time A value of 10ns to 50ns is typical for ton and toff. Note that the RDSON has a positive temperature coefficient. At 100˚C, the RDSON may be as much as 150% higher than the value at 25˚C. The Gate capacitance of the PFET has a direct impact on both PFET transition time and the power dissipation in the LM3475. Most of the power dissipated in the LM3475 is used to drive the PFET switch. This power can be calculated as follows: The amount of average gate driver current required during switching (IG) is: IG = Qg x F And the total power dissipated in the device is: IqVIN + IGVIN Where Iq is typically 260µA as shown in the Electrical Characteristics table. As gate capacitance increases, operating frequency may need to be reduced, or additional heat sinking may be required to lower the power dissipation in the device. In general, keeping the gate capacitance below 2000pF is recommended to keep transition times (switching losses), and power losses low. REDUCING SWITCHING NOISE Although the LM3475 employs internal noise suppression circuitry, external noise may continue to be excessive. There are several methods available to reduce noise and EMI. MOSFETs are very fast switching devices. The fast increase in PFET current coupled with parasitic trace inductance can create unwanted noise spikes at both the switch node and at VIN. Switching noise will increase with load current and input voltage. This noise can also propagate through the ground plane, sometimes causing unpredictable device performance. Slowing the rise and fall times of the PFET can be very effective in reducing this noise. Referring to Figure 4, the PFET can be slowed down by placing a small (1Ω-10Ω) resistor in series with PGATE. However, this resistor will increase the switching losses in the PFET and will lower efficiency. Therefore it should be kept as small as possible and only used when necessary. Another method to reduce switching noise (other than good PCB layout, see Layout section) is to use a small RC filter or snubber. The snubber should be placed in parallel with the catch diode, connected close to the drain of the PFET, as shown in Figure 4. Again, the snubber should be kept as small as possible to limit its impact on system efficiency. A typical range is a 10Ω-100Ω resistor and a 470pF to 2.2nF ceramic capacitor. 20070105 FIGURE 4. PGATE Resistor and Snubber Layout PC board layout is very important in all switching regulator designs. Poor layout can cause EMI problems, excess switching noise and poor operation. As shown in Figure 6 and Figure 7, place the ground of the input capacitor as close as possible to the anode of the diode. This path also carries a large AC current. The switch node, the node connecting the diode cathode, inductor, and PFET drain, should be kept as small as possible. This node is one of the main sources for radiated EMI. The feedback pin is a high impedance node and is therefore sensitive to noise. Be sure to keep all feedback traces away from the inductor and the switch node, which are sources of noise. Also, the resistor divider should be placed close to the FB pin. The gate pin of the external PFET should be located close to the PGATE pin. Using a large, continuous ground plane is also recommended, particularly in higher current applications. 11 www.national.com LM3475 Layout (Continued) 20070101 FIGURE 5. Bill of Materials Designator CIN COUT CFF D1 L1 Q1 RFB2 RFB1 Description 10µF, 16V, X5R 100µF, 6V, Ta 1nF, 25V, X7R Schottky, 20V, 2A 10µH, 3.1A 30V, 2.5A 1kΩ, 0805, 1% 2.15kΩ, 0805, 1% Part Number EMK325BJ106MN TPSY107M006R0100 VJ1206Y102KXXA CMSH2-20L CDRH103R100 Si2343 CRW08051001F CRCW08052151F Vendor TAIYO YUDEN AVX Vishay Central Semiconductor Sumida Vishay Vishay Vishay 20070106 FIGURE 6. Top Layer (Standard Board) (2:1 Scale) www.national.com 12 LM3475 Layout (Continued) 20070107 FIGURE 7. Top Layer (with External Ramp) (2:1 Scale) 20070130 FIGURE 8. Bottom Layer (2:1 Scale) 13 www.national.com LM3475 Hysteretic PFET Buck Controller Physical Dimensions inches (millimeters) unless otherwise noted 5 Lead Plastic SOT23-5 NS package Number MF05A National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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