User's Guide
SNVA304A – April 2008 – Revised May 2013
AN-1756 LM3481 Evaluation Board
1
Introduction
The LM3481 is a current mode, low side N channel FET controller. It can be utilized in numerous
configurations including a Boost, Flyback or SEPIC (Single Ended Primary Inductor Converter). This
evaluation board demonstrates the flexibility of the LM3481 in a boost topology. The operating conditions
for the evaluation board are listed below:
3V ≤ VIN ≤ 11V
VOUT = 12V
0A ≤ IOUT ≤ 1.5A
The circuit and bill of materials for this design are given below:
R7
121 kÖ
VIN
J1
R8
121 kÖ
C8
390 pF
VIN
ISEN
VC
UVLO
C
COMP
R3
1.37 kÖ
C6
0.12 éF
LM3481
FB
R2
20 kÖ
L1
7.8 éH
C3
0.47 éF
1 éF
VOUT
C9
Q1
DR
PGND
+ C1, C2
100 éF
D1
+ C4, C5
100 éF
R4
100Ö
FA/SYNC/SD
AGND
R6
61.9 kÖ
R1
169 kÖ
C7
2.2 nF
R5
20
mÖ
Figure 1. Circuit Diagram
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SNVA304A – April 2008 – Revised May 2013
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1
Bill of Materials
2
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Bill of Materials
Table 1. Bill of Materials
300 kHz, Vin = 5V, Vo = 12V, IO = 1.5A
2
Designat
or
Function
Description
Part Number
Vendor
U1
Controller
LM3481 VSSOP-10
LM3481
Texas
Instruments
C1
Input Filter Cap
100 µF, 20V, D case, OxiCap
TPSV107M020R0060
AVX
C2
Input Filter Cap
100 µF, 20V, D case, OxiCap
TPSV107M020R0060
AVX
C3
Decoupling Cap
.47 µF, 16V, X7R, 1206
ECJ-3VB1C474K
Panasonic
C4
Output Filter Cap
100 µF, 16V, Y case, Ta
TPSD107M016R0100
AVX
C5
Output Filter Cap
100 µF, 16V, Y case, Ta
TPSD107M016R0100
AVX
C6
Comp Cap
0.12 µF, 25V, 0805
ECJ-2YB1E124K
Panasonic
C7
Current Limit Sense Cap
2200 pF, 50V, 0805
ECJ-2VB1H222K
Panasonic
C8
Comp Cap
390 pF, 50V, 0805
08055C391KAT2A
AVX
C9
VCC Cap
1 µF, 25V, 1206
12063C105KAT
AVX
C11
Analog Input By. Cap
1 µF, 10V, 0805
0805ZC105KAT
AVX
R1
Resistor Divider (Upper)
169 kΩ, 1%, 0805
CRCW0805169KFK
Vishay
R2
Resistor Divider (Lower)
20k, 1%, 0805
CRCW080520K0FK
Vishay
R3
Comp Resistor
1.37k, 1%, 0805
CRCW08051K37FK
Vishay
R4
Filter Resistor
100Ω, 1%, 0805
CRCW0805100RFK
Vishay
R5
Sense Resistor
20 mΩ, 1%
WSL2512R0200FE
Vishay
R6
Freq. Adj. Resistor
61.9 kΩ, 1%, 0805
CRCW08056192F
Vishay
R7
UVLO Res. Div.
121 kΩ, 1%, 0805
CRCW08051213F
Vishay
R8
UVLO Res. Div.
121 kΩ, 1%, 0805
CRCW08051213F
Vishay
L1
Input Filter
7.8µ , 8A, DCR = 10 mΩ
RLF12560-7R8N8R2
TDK
D1
Schottky Diode
4A,30V, Vf = 0.4V
SL-43
Vishay
Q1
FET
SO-8, Rdson = 2.9 mΩ@VDS = 30V
SI4368DY
Vishay
J1
Jumper
Shunt LM with handle, 2 positions
881545-2
Tyco
Electronics
VIN
VIN Post Turret
90mil mounting diameter
97H6305
Newark
Catalog
GND
VIN GND Post Turret
90mil mounting diameter
97H6305
Newark
Catalog
GND
VOUT Post Turret
90mil mounting diameter
97H6305
Newark
Catalog
VOUT
VOUT GND Post Turret
90mil mounting diameter
97H6305
Newark
Catalog
AN-1756 LM3481 Evaluation Board
SNVA304A – April 2008 – Revised May 2013
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Performance
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3
Performance
Benchmark data has been taken from the evaluation board using the LM3481. Figure 2 shows an
efficiency measurement taken at the maximum load of 1.5A with Vin at 5V.
Figure 2. Efficiency vs Load
The advantage of the evaluation board is the ability to examine performance tradeoffs through substitution
of parts. By careful selection of the components used, it is possible to optimize the application circuit for a
given parameter. For instance, the FET footprint has been designed to accommodate either one SO-8 or
two parallel SO-8 packages. The selection of the FET would then be determined by the design
constraints. An example would be that a lower system cost could be obtained by selection of a FET with a
higher RDS(ON), although performance would be sacrificed through reduced efficiency.
4
Current Limit
The purpose of the R4 (RSL) resistor is to provide flexibility in the selection of the slope compensation
needed for the required application. The amount of slope compensation directly determines the minimum
inductance required for stability. (Please see the LM3481/LM3481Q High Efficiency Low-Side N-Channel
Control for Switching Regulators (SNVS346) data sheet for adjustment of slope compensation and for a
complete discussion on how to calculate the R4 value needed). This evaluation board uses R4 and C7 to
filter the Isen signal with negligible affect on the slope compensation.
5
Layout Fundamentals
Good layout for DC-DC converters can be implemented by following a few simple design guidelines:
1. Place the power components (catch diode, inductor, and filter capacitors) close together. Make the
traces between them as short and wide as possible.
2. Use wide traces between the power components and for power connections to the DC-DC converter
circuit.
3. Connect the ground pins of the input and output filter capacitors and catch diode as close as possible
using generous component-side copper fill as a pseudo-ground plane. Then, connect this to the ground
plane through several vias.
4. Arrange the power components so that the switching loops curl in the same direction.
5. Separate noise sensitive traces, such as the voltage feedback path, from noisy traces associated with
the power components.
6. Ensure a good low-impedance ground for the converter IC.
7. Place the supporting components for the converter IC, such as compensation and frequency selection
components as close to the converter IC as possible, but away from noisy traces and the power
components. Make their connections to the converter IC and its pseudo-ground plane as short as
SNVA304A – April 2008 – Revised May 2013
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Layout Fundamentals
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possible.
8. Place noise sensitive circuitry such as radio or modem blocks away from the DC-DC converter.
Figure 3. Top Layer
Figure 4. Bottom Layer
4
AN-1756 LM3481 Evaluation Board
SNVA304A – April 2008 – Revised May 2013
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Copyright © 2008–2013, Texas Instruments Incorporated
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