Product
Folder
Sample &
Buy
Support &
Community
Tools &
Software
Technical
Documents
LM3881
SNVS555D – JANUARY 2008 – REVISED DECEMBER 2014
LM3881 Simple Power Sequencer With Adjustable Timing
1 Features
3 Description
•
•
•
•
•
•
•
The LM3881 Simple Power Sequencer offers the
easiest method to control power up and power down
of multiple power supplies (switching or linear
regulators). By staggering the start-up sequence, it is
possible to avoid latch conditions or large inrush
currents that can affect the reliability of the system.
1
Easiest Method to Sequence Rails
Power-Up and Power-Down Control
Tiny Footprint
Low Quiescent Current of 80 µA
Input Voltage Range of 2.7 V to 5.5 V
Output Invert Feature
Timing Controlled by Small Value External
Capacitor
Available in VSSOP-8 package, the Simple
Sequencer contains a precision enable pin and three
open-drain output flags. When the LM3881 is
enabled, the three output flags will sequentially
release, after individual time delays, thus permitting
the connected power supplies to start up. The output
flags will follow a reverse sequence during power
down to avoid latch conditions. Time delays are
defined using an external capacitor and the output
flag states can be inverted by the user.
2 Applications
•
•
•
•
•
•
Security Cameras
Servers
Networking Elements
FPGA Sequencing
Microprocessor and Microcontroller Sequencing
Multiple Supply Sequencing
Device Information(1)
PART NUMBER
LM3881
PACKAGE
VSSOP (8)
BODY SIZE (NOM)
3.00 mm x 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Typical System Application
DEVICE 1
Input
Supply
LM3881
EN
VCC
Enable
EN
DEVICE 2
FLAG1
FLAG2
Invert
INV
EN
FLAG3
GND
DEVICE 3
EN
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM3881
SNVS555D – JANUARY 2008 – REVISED DECEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
6
Absolute Maximum Ratings ......................................
Handling Ratings ......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 8
7.4 Device Functional Modes........................................ 13
8
Application and Implementation ........................ 15
8.1 Application Information............................................ 15
8.2 Typical Application ................................................. 15
9 Power Supply Recommendations...................... 18
10 Layout................................................................... 18
10.1 Layout Guidelines ................................................. 18
10.2 Layout Example .................................................... 18
11 Device and Documentation Support ................. 20
11.1
11.2
11.3
11.4
Device Support......................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
20
20
20
20
12 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (April 2013) to Revision D
•
Added Handling Rating table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section ............................................................... 4
Changes from Revision B (April 2013) to Revision C
•
2
Page
Page
Changed layout of National Data Sheet to TI format ........................................................................................................... 13
Submit Documentation Feedback
Copyright © 2008–2014, Texas Instruments Incorporated
Product Folder Links: LM3881
LM3881
www.ti.com
SNVS555D – JANUARY 2008 – REVISED DECEMBER 2014
5 Pin Configuration and Functions
VSSOP Package
8-Pin DGK
Top View
VCC
EN
GND
INV
1
8
2
7
FLAG1
LM3881
3
6
5
4
FLAG2
FLAG3
TADJ
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
VCC
1
I
Input Supply
EN
2
I
Precision Enable
GND
3
–
Ground
INV
4
I
Output Logic Invert
TADJ
5
O
Timer Adjust
FLAG3
6
O
Open-Drain Output 3
FLAG2
7
O
Open-Drain Output 2
FLAG1
8
O
Open-Drain Output 1
Submit Documentation Feedback
Copyright © 2008–2014, Texas Instruments Incorporated
Product Folder Links: LM3881
3
LM3881
SNVS555D – JANUARY 2008 – REVISED DECEMBER 2014
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted)
(1) (2)
MIN
MAX
UNIT
–0.3
6.0
V
Junction Temperature
150
°C
Lead Temperature (Soldering, 5 s)
260
°C
VCC, EN, INV, TADJ, FLAG1, FLAG2,
FLAG3 to GND
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
6.2 Handling Ratings
Tstg
Storage temperature range
V(ESD)
(1)
Electrostatic discharge
MIN
MAX
UNIT
–65
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
2
kV
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
2.7
5.5
EN, INV, TADJ, FLAG1, FLAG2, FLAG3 to GND
–0.3
VCC + 0.3
V
Junction Temperature
–40
125
°C
VCC to GND
UNIT
V
6.4 Thermal Information
LM3881
THERMAL METRIC (1)
DGK
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
224.5
RθJC(top)
Junction-to-case (top) thermal resistance
107.6
RθJB
Junction-to-board thermal resistance
145.3
ψJT
Junction-to-top characterization parameter
31.8
ψJB
Junction-to-board characterization parameter
143.7
(1)
4
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Submit Documentation Feedback
Copyright © 2008–2014, Texas Instruments Incorporated
Product Folder Links: LM3881
LM3881
www.ti.com
SNVS555D – JANUARY 2008 – REVISED DECEMBER 2014
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted). Minimum and Maximum limits are ensured through test,
design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C and are provided for
reference purposes only. TJ = –40°C to +125°C, VCC = 3.3 V, unless otherwise specified.
PARAMETER
IQ
TEST CONDITIONS
MIN (1)
Operating Quiescent Current
TYP (2)
MAX (1)
80
110
µA
0.001
1
µA
0.4
V
UNIT
OPEN-DRAIN FLAGS
IFLAG
FLAGx Leakage
Current
VFLAGx = 3.3 V
VOL
FLAGx Output
Voltage Low
IFLAGx = 1.2 mA
TIME DELAYS
ITADJ_SRC
TADJ Source Current
4
12
20
µA
ITADJ_SNK
TADJ Sink Current
4
12
20
µA
VHTH
High Threshold Level
1.0
1.22
1.4
V
VLTH
Low Threshold Level
0.3
0.5
0.7
TCLK
Clock Cycle
TD1, TD4
Flag Time Delay
TD2, TD3,
TD5, TD6
Flag Time Delay
CADJ = 10 nF
1.2
9
V
ms
10
8
Clock cycles
Clock cycles
ENABLE PIN
VEN
EN Pin Threshold
IEN
EN Pin Pullup Current VEN = 0 V
1.0
1.22
1.5
7
V
µA
INV PIN
VIH_INV
Invert Pin VIH
VIL_INV
Invert Pin VIL
(1)
(2)
90% VCC
V
10%
VCC
V
Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation using Statistical
Quality Control (SQC) methods. The limits are used to calculate TI's Average Outgoing Quality Level (AOQL).
Typical numbers are at 25°C and represent the most likely parametric norm.
Submit Documentation Feedback
Copyright © 2008–2014, Texas Instruments Incorporated
Product Folder Links: LM3881
5
LM3881
SNVS555D – JANUARY 2008 – REVISED DECEMBER 2014
www.ti.com
6.6 Typical Characteristics
80.4
82
80.2
80
IQ (PA)
IQ (PA)
VCC = 3.3 V unless otherwise specified.
80.0
79.8
79.6
2.5
78
76
3.0
3.5
4.0
4.5
5.0
74
-50
5.5
-25
9.56
1.230
9.55
1.225
9.54
1.220
9.52
1.210
9.51
0
25
50
50
75
100
125
9.53
1.215
-25
25
Figure 2. Quiescent Current vs Temperature
1.235
TD (ms)
VEN (V)
Figure 1. Quiescent Current vs VCC
1.205
-50
0
TEMPERATURE (°C)
VCC (V)
75
100
9.50
2.5
125
3
3.5
4
4.5
5
5.5
VIN (V)
TEMPERATURE (°C)
Figure 3. Enable Threshold vs Temperature
Figure 4. Time Delay vs VIN (CADJ = 10 nF Nominal)
9.75
1
9.70
0.8
VFLAG (V)
TD (ms)
9.65
9.60
0.6
0.4
9.55
0.2
9.50
9.45
-50
-25
0
25
50
75
100
0
125
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
TEMPERATURE (°C)
VIN (V)
Figure 5. Time Delay vs Temperature (CADJ = 10 nF Nominal)
6
Figure 6. VFLAG vs VIN (INV Low, RFLAG = 100 kΩ)
Submit Documentation Feedback
Copyright © 2008–2014, Texas Instruments Incorporated
Product Folder Links: LM3881
LM3881
www.ti.com
SNVS555D – JANUARY 2008 – REVISED DECEMBER 2014
Typical Characteristics (continued)
VCC = 3.3 V unless otherwise specified.
1
0.8
VFLAG (V)
VCC = 3.3V
0.6
VCC = 5V
0.4
0.2
0
0
1
2
3
4
5
IFLAG (mA)
Figure 7. FLAG Voltage vs Current
Submit Documentation Feedback
Copyright © 2008–2014, Texas Instruments Incorporated
Product Folder Links: LM3881
7
LM3881
SNVS555D – JANUARY 2008 – REVISED DECEMBER 2014
www.ti.com
7 Detailed Description
7.1 Overview
The LM3881 Simple Power Sequencer provides a simple solution for sequencing multiple rails in a controlled
manner. An established clock signal facilitates control of the power up and power down of three open-drain FET
output flags. These flags permit connection to shutdown or enable pins of linear regulators and/or switching
regulators to control the operation of the power supplies. This allows design of a complete power system without
the concern of large inrush currents or latch-up conditions that can occur during an uncontrolled startup. An
invert (INV) pin reverses the logic of the output flags. This pin should be tied to a logic output high or low and not
allowed to remain open circuit. The following discussion assumes the INV pin is held low such that the flag
output is active high.
7.2 Functional Block Diagram
VCC
FLAG1
7 PA
EN
+
TD1
-
TD2
Timing
Delay
Generation
1.22V
FLAG2
TD3
TD4
Sequence
Control
TD5
TD6
Clock
FLAG3
TADJ
GND
INV
7.3 Feature Description
7.3.1 Adjustable Timing
A small external timing capacitor is connected to the TADJ pin that establishes the clock waveform. This
capacitor is linearly charged/discharged by a fixed current source/sink, denoted ITADJ_SRC / ITADJ_SNK, of
magnitude 12 µA between predefined voltage threshold levels, denoted VLTH and VHTH, to generate the timing
waveform as shown in Figure 8.
8
Submit Documentation Feedback
Copyright © 2008–2014, Texas Instruments Incorporated
Product Folder Links: LM3881
LM3881
www.ti.com
SNVS555D – JANUARY 2008 – REVISED DECEMBER 2014
Feature Description (continued)
High Threshold Level,
VHTH = 1.22V
TADJ
Low Threshold Level,
VLTH = 0.5V
TCLK
Figure 8. TADJ Pin Timing Waveform
Thus, the clock cycle duration is directly proportional to the timing capacitor value. Considering the TADJ voltage
threshold levels and the charge/discharge current magnitude, it can be shown that the timing capacitor-clock
period relationship is typically 120 µs/nF. For example, a 10-nF capacitor sets up a clock period of 1.2 ms.
The timing sequence of the LM3881 is controlled by the enable (EN) pin. Upon power up, all the flags are held
low until the precision enable pin exceeds its threshold. After the EN pin is asserted, the power-up sequence will
commence and the open-drain flags will be sequentially released.
An internal counter will delay the first flag (FLAG1) from rising until a fixed time period, denoted by TD1 in
Figure 9, elapses. This corresponds to at least nine, maximum 10, clock cycles depending on where EN is
asserted relative to the clock signal. Upon release of the first flag, another timer will begin to delay the release of
the second flag (FLAG2). This time delay, denoted TD2, corresponds to exactly eight clock periods. Similarly,
FLAG3 is released after time delay TD3, again eight clock cycles, has expired. Accordingly, a TADJ capacitor of
10 nF generates typical time delays TD2 and TD3 of 9.6 ms and TD1 of from 10.8 ms to 12.0 ms.
The power-down sequence is the same as power up, but in reverse order. When the EN pin is deasserted, a
timer will begin that delays the third flag (FLAG3) from pulling low. The second and first flag will then follow in a
sequential manner after their appropriate time delays. These time delays, denoted TD4, TD5, TD6, are equal to
TD1, TD2, TD3, respectively.
For robustness, the pulldown FET associated with each flag is designed such that it can sustain a short circuit to
VCC.
EN
FLAG1
FLAG2
FLAG3
TADJ
TD1
TD2
TD3
9 Clock
Cycles
8 Clock
Cycles
8 Clock
Cycles
Figure 9. Power-Up Sequence, INV Low
Submit Documentation Feedback
Copyright © 2008–2014, Texas Instruments Incorporated
Product Folder Links: LM3881
9
LM3881
SNVS555D – JANUARY 2008 – REVISED DECEMBER 2014
www.ti.com
Feature Description (continued)
EN
FLAG1
FLAG2
FLAG3
TADJ
TD1
TD2
TD3
9 Clock
Cycles
8 Clock
Cycles
8 Clock
Cycles
Figure 10. Power-Up Sequence, INV High
EN
FLAG1
FLAG2
FLAG3
TADJ
TD4
TD5
TD6
9 Clock
Cycles
8 Clock
Cycles
8 Clock
Cycles
Figure 11. Power-Down Sequence, INV Low
10
Submit Documentation Feedback
Copyright © 2008–2014, Texas Instruments Incorporated
Product Folder Links: LM3881
LM3881
www.ti.com
SNVS555D – JANUARY 2008 – REVISED DECEMBER 2014
Feature Description (continued)
EN
FLAG1
FLAG2
FLAG3
TADJ
TD4
TD5
TD6
9 Clock
Cycles
8 Clock
Cycles
8 Clock
Cycles
Figure 12. Power-Down Sequence, INV High
7.3.2 Enable Circuit
The enable circuit is designed with an internal comparator, referenced to a bandgap voltage (1.22 V), to provide
a precision threshold. This allows the timing to be set externally using a capacitor as shown in Figure 13.
Alternatively, sequencing can be based on a certain event such as a line voltage reaching 90% of its nominal
value by employing a resistor divider from VCC to Enable.
7 PA
EN
1.22V
+
-
Enable
CEN
Figure 13. Precision Enable Circuit
Using the internal pullup current source to charge the external capacitor CEN, the time delay while the enable
voltage reaches the required threshold, assuming EN is charging from 0V, can be calculated by the equation as
follows.
Tenable_delay =
1.22V x CEN
7 PA
(1)
Submit Documentation Feedback
Copyright © 2008–2014, Texas Instruments Incorporated
Product Folder Links: LM3881
11
LM3881
SNVS555D – JANUARY 2008 – REVISED DECEMBER 2014
www.ti.com
Feature Description (continued)
EN
1.22V
0V
Tenable delay
Figure 14. Enable Delay Timing
A resistor divider can also be used to enable the LM3881 based on exceeding a certain VCC supply voltage
threshold. Take care when sizing the resistor divider to include the effects of the internal EN pullup current
source. The supply voltage for which EN is asserted is given by
§ REN1 · - 7 PA (R llR )
EN1
EN2
VCCENABLE = 1.22V ¨1 +
¸
© REN2¹
(2)
Input Supply
(2.7V - 5.5V)
LM3881
REN1
VCC
EN
FLAG1
FLAG2
INV
FLAG3
REN2
TADJ
CADJ
GND
Figure 15. Enable Based On Input Supply Level
One of the features of the EN pin is that it provides glitch free operation. The timer will start counting at a rising
threshold, but will always reset if the EN pin is deasserted before the first output flag is released. This is
illustrated in Figure 16, assuming INV is low.
EN
FLAG1
TD1
Figure 16. Enable Glitch Timing, INV Low
12
Submit Documentation Feedback
Copyright © 2008–2014, Texas Instruments Incorporated
Product Folder Links: LM3881
LM3881
www.ti.com
SNVS555D – JANUARY 2008 – REVISED DECEMBER 2014
Feature Description (continued)
If the EN pin remains high for the entire power up sequence, then the part will operate as shown in the standard
timing diagrams. However, if the EN signal is deasserted before the power-up sequence completes, the part will
enter a controlled shutdown. This allows the system to initiate a controlled power sequence, preventing any latch
conditions to occur. Figure 17 describes the flag sequence if the EN pin is deasserted after FLAG1 releases, but
before the entire power-up sequence is completed. INV is assumed low.
EN
FLAG1
FLAG2
FLAG3
TADJ
TD4
TD1
9 Clock
Cycles
< 8 Clock
Cycles
9 Clock
Cycles
EN
FLAG1
FLAG2
FLAG3
TADJ
TD1
TD2
9 Clock
Cycles
8 Clock
Cycles
< 8 Clock
Cycles
TD4
TD5
9 Clock
Cycles
8 Clock
Cycles
Figure 17. Incomplete Sequence Timing, INV Low
7.4 Device Functional Modes
7.4.1 Power Up with EN Pin
The timing sequence of the Simple Power Sequencer is controlled entirely by the enable (EN) pin. Upon power
up, all the flags are held low until this precision enable is pulled high. After the EN pin is asserted, the power-up
sequence will commence.
Submit Documentation Feedback
Copyright © 2008–2014, Texas Instruments Incorporated
Product Folder Links: LM3881
13
LM3881
SNVS555D – JANUARY 2008 – REVISED DECEMBER 2014
www.ti.com
Device Functional Modes (continued)
7.4.2 Power Down with EN Pin
When EN pin is deasserted, the power down sequence will commence. A timer will begin that delays the third
flag (FLAG3) from pulling low. The second and first flag will then follow in a sequential manner after their
appropriate delays.
7.4.3 Noninverted Output Mode
When the INV pin is tied to a logic output low, the logic mode of the output flags is active high. This mode is
useful to sequence power supplies which have an active high enable input.
7.4.4 Inverted Output Mode
When the INV pin is tied to a logic output high, the logic mode of the output flags is active low. This mode is
useful to sequence power supplies which have an active low enable input.
14
Submit Documentation Feedback
Copyright © 2008–2014, Texas Instruments Incorporated
Product Folder Links: LM3881
LM3881
www.ti.com
SNVS555D – JANUARY 2008 – REVISED DECEMBER 2014
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 Open-Drain Flags Pullup
The Simple Power Sequencer contains three open-drain output flags which need to be pulled up for proper
operation. 100-kΩ resistors can be used as pullup resistors.
8.1.2 Enable the Device
See Enable Circuit.
8.1.3 Timing Adjust
See Adjustable Timing.
8.2 Typical Application
8.2.1 Simple Sequencing of Three Power Supplies
The Simple Power Sequencer is used to implement a power-up (1 - 2 - 3) and power-down (3 - 2 - 1) sequence
of three power supplies.
Figure 18. Typical Application Circuit
Submit Documentation Feedback
Copyright © 2008–2014, Texas Instruments Incorporated
Product Folder Links: LM3881
15
LM3881
SNVS555D – JANUARY 2008 – REVISED DECEMBER 2014
www.ti.com
Typical Application (continued)
8.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 1 as the input parameters.
Table 1. Design Parameters
Design Parameter
Example Value
Input Supply voltage range
2.7 V to 5.5 V
Flag Output voltage, EN high
Input Supply
Flag Output voltage, EN low
0V
Flag Timing Delay, TD1
10.8 ms - 12.0 ms
Flag Timing Delay, TD2 and TD3
9.6 ms
Power-Up Sequence
1-2-3
Power-Down Sequence
3-2-1
8.2.1.2 Detailed Design Procedure
Table 2. Evaluation Board Bill of Materials
Ref Des
Description
Case Size
Manufacturer
Manufacturer P/N
U1
LM3881 Sequencer
MSOP-8
Texas Instruments
LM388
R1
100 kΩ
0603
Vishay Dale
CRCW06031003F-e3
R2
100 kΩ
0603
Vishay Dale
CRCW06031003F-e3
R3
100 kΩ
0603
Vishay Dale
CRCW06031003F-e3
CADJ
10 nF ±10% X7R 16 V
0603
Murata
GRM188R71C103KA01
A timing capacitor of CADJ = 10 nF generates typical time delays TD2 and TD3 of 9.6 ms and TD1 of between
10.8 ms and 12.0 ms. The INV pin is tied to GND so that the output flags are active high. See Adjustable Timing
for calculating the value for CADJ.
8.2.1.3 Application Curves
Figure 19. Power-Up Sequence, CADJ = 10 nF
16
Figure 20. Power-Down Sequence, CADJ = 10 nF
Submit Documentation Feedback
Copyright © 2008–2014, Texas Instruments Incorporated
Product Folder Links: LM3881
LM3881
www.ti.com
SNVS555D – JANUARY 2008 – REVISED DECEMBER 2014
Figure 21. Power-Up Sequence, TADJ Open
Figure 22. Power-Down Sequence, TADJ Open
8.2.2 Sequencing Using Independent Flag Supply
For applications requiring a flag output voltage that is different from the VCC, a separate Flag Supply may be
used to pullup the open-drain outputs of the Simple Power Sequencer. This is useful when interfacing the flag
outputs with inputs that require a different voltage than VCC. The designer must ensure the Flag Supply voltage
is within the range specified in the Recommended Operating Conditions.
Figure 23. Sequencing Using Independent Flag Supply
Submit Documentation Feedback
Copyright © 2008–2014, Texas Instruments Incorporated
Product Folder Links: LM3881
17
LM3881
SNVS555D – JANUARY 2008 – REVISED DECEMBER 2014
www.ti.com
9 Power Supply Recommendations
The VCC pin should be located as close as possible to the input supply (2.7V - 5.5V). An input capacitor is not
required but is recommended when noise might be present on the VCC pin. A 0.1 μF ceramic capacitor may be
used to bypass this noise.
10 Layout
10.1 Layout Guidelines
•
•
Pullup resistors should be connected between the flag output pins and a positive input supply, usually VCC.
An independent flag supply may also be used. These resistors should be placed as close as possible to the
Simple Power Sequencer and the flag supply. Minimal trace length is recommended to make the connections.
A typical value for the pullup resistors is 100kΩ.
For very tight sequencing requirements, minimal and equal trace lengths should be used to connect the flag
outputs to the desired inputs. This will reduce any propagation delay and timing errors between the flag
outputs along the line.
10.2 Layout Example
Figure 24 and Figure 25 are layout examples for the LM3881. These examples are taken from the LM3881EVAL.
An optional component, assigned reference designator R4, is placed on the bottom side of the PCB to facilitate
connection of INV to GND.
Figure 24. LM3881 Top
18
Submit Documentation Feedback
Copyright © 2008–2014, Texas Instruments Incorporated
Product Folder Links: LM3881
LM3881
www.ti.com
SNVS555D – JANUARY 2008 – REVISED DECEMBER 2014
Layout Example (continued)
Figure 25. LM3881 Bottom
Submit Documentation Feedback
Copyright © 2008–2014, Texas Instruments Incorporated
Product Folder Links: LM3881
19
LM3881
SNVS555D – JANUARY 2008 – REVISED DECEMBER 2014
www.ti.com
11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Trademarks
All trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
20
Submit Documentation Feedback
Copyright © 2008–2014, Texas Instruments Incorporated
Product Folder Links: LM3881
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM3881MM/NOPB
ACTIVE
VSSOP
DGK
8
1000
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
STBB
LM3881MME/NOPB
ACTIVE
VSSOP
DGK
8
250
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
STBB
LM3881MMX/NOPB
ACTIVE
VSSOP
DGK
8
3500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
STBB
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
工商网监
湘ICP备2023018690号
