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LM5066I
SNVS950C – APRIL 2014 – REVISED JULY 2016
LM5066I 10 to 80 V, Hotswap Controller With I/V/P Monitoring and PMBus™ Interface
1 Features
3 Description
•
•
•
•
•
•
•
•
•
LM5066I provides robust protection and precision
monitoring for 10- to 80-V systems. Programmable
UV, OV, ILIMIT, and fast-short circuit protection allow
for customized protection for any application.
Programmable FET SOA protection sets the
maximum power the FET is allowed to dissipate
under any condition. The programmable fault timer
(tFAULT) is set to avoid nuisance trips, ensure start-up,
and limit the duration of over load events.
1
•
•
•
•
•
10- to 80-V Operation
100-V Continuous Absolute Max
26 mV or 50 mV ILIM Threshold (±10%)
Programmable FET SOA Protection
Programable UV, OV, tFAULT Thresholds
External FET Temperature Sensing
Failed FET Detection
I2C / SMBus Interface
PMBus™ and Node Manager 2.0 and 3.0
Compliant Command Structure
Precision V IN, VOUT, IIN, PIN, VAUX Monitoring
– V (±1.25%); I (±1.75%); P (±2.5%)
Supports Energy Monitoring via Read_EIN
Command
Programable I/V/P Averaging Interval
12-bit ADC with 1-kHz Sampling Rate
–40°C < TJ < 125°C Operation
In addition to circuit protection, the LM5066I supplies
real-time power, voltage, current, temperature, and
fault data to the system management host through
the I2C / SMBus interface. PMBus compliant
command structure makes it easy to program the
device. Precision telemetry enables intelligent power
management
functions
such
as
efficiency
optimization and early fault detection. LM5066I also
supports advanced features such as I/V/P averaging
and peak power measurment to improve system
diagnostics.
LM5066I is pin-to-pin compatible with the LM5066
and offers improved telemetry accuracy and supports
the Read_Ein command to monitor energy. See
Table 1 for a detailed comparison.
2 Applications
•
•
•
•
•
48-V Servers
Base Station Power Distribution
Networking Routers and Switchers
PLC Power Management
24- to 28-V Industrial Systems
Device Information(1)
PART NUMBER
LM5066I
PACKAGE
BODY SIZE (NOM)
9.70 × 4.40 mm2
PWP (28)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
SPACE
Simplified Schematic
VOUT
RSNS
D1
Z1
R1
GATE OUT DIODE
FB
SENSE
VIN_K
VIN
SMBus
Interface
R4
AGND
GND
R5
VDD
R6
UVLO/EN
OVLO
R2
COUT
Q1
R3
48-V Bus
LM5066I
PGD
ADR2
ADR1
ADR0
CL
VDD
SMBA
RETRY
SDAO
VAUX
SDAI
SCL
VDD VREF PWR TIMER
1 PF
1 PF
RPWR
Card to Card Communication
CIN
LM5066I in a Plug-in Card
Q2
VIN
PMBus Hotswap
Manages Inrush,
Faults, and
Monitoring
48 V
12 V
DC/DC
Load 1
Load 2
I/V/P info
via PMBus
Regulate Loads to
Micro
Controller Optimize Efficiency
Plug-in Card
CTIMER
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5066I
SNVS950C – APRIL 2014 – REVISED JULY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
5
7.1
7.2
7.3
7.4
7.5
7.6
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics........................................... 7
SMBus Communications Timing Requirements and
Definitions ................................................................ 10
7.7 Switching Characteristics ........................................ 11
7.8 Typical Characteristics ............................................ 12
8
Detailed Description ............................................ 14
8.1
8.2
8.3
8.4
8.5
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
14
15
15
18
21
Application and Implementation ........................ 43
9.1 Application Information............................................ 43
9.2 Typical Application ................................................. 43
10 Power Supply Recommendations ..................... 60
11 Layout................................................................... 61
11.1 Layout Guidelines ................................................. 61
11.2 Layout Example .................................................... 61
12 Device and Documentation Support ................. 63
12.1 Trademarks ........................................................... 63
12.2 Electrostatic Discharge Caution ............................ 63
12.3 Glossary ................................................................ 63
13 Mechanical, Packaging, and Orderable
Information ........................................................... 63
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (March 2015) to Revision C
•
Page
Changed VGATEZ MIN value from "15 V" to "12 V" ................................................................................................................. 7
Changes from Revision A (May 2014) to Revision B
Page
•
Added Absolute Maximum Ratings table. ............................................................................................................................. 5
•
Changed title of Handling Ratings table to ESD Ratings table ............................................................................................. 5
Changes from Original (April 2014) to Revision A
•
2
Page
Added new sections ............................................................................................................................................................... 1
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SNVS950C – APRIL 2014 – REVISED JULY 2016
5 Device Comparison Table
Table 1 summarizes the differences between the LM5066 and the LM5066I. Note that the current monitoring
accuracy of the LM5066I is much better at the ILIM = 26 mV setting, but is comparable at the 50-mV setting. For
many applications with lower power, using the LM5066 at the 50-mV setting is a great option. However, for
higher power applications upgrading to LM5066I and using the ILIM = 26 mV setting will lead to significant power
savings (approximately 24 mV × ILOAD). In addition, the higher accuracy and energy monitoring capability can
enable further improvements in system efficiency, which is critical in high power applications.
Table 1. LM5066 vs LM5066I
KEY PARAMETERS
LM5066
LM5066I
Voltage monitoring
±2.7%
±1.25%
Current monitoring (ILIM = 26 mV)
±4.25%
±1.75%
Power monitoring (ILIM = 26 mV)
±4.5%
±.2.5%
Current monitoring (ILIM = 50 mV)
±3%
±3.5%
Power monitoring (ILIM = 50 mV)
±4.5%
±4.5%
No
Yes
Supports Energy Monitoring via
Read_EIN command
6 Pin Configuration and Functions
PWP Package
28-Pin
Top View
OUT
1
28
PGD
GATE
2
27
NC
SENSE
3
26
PWR
VIN_K
4
25
TIMER
VIN
5
24
RETRY
NC
6
23
FB
UVLO/EN
7
22
CL
OVLO
8
21
VDD
AGND
9
20
ADR0
GND
10
19
ADR1
SDAI
11
18
ADR2
SDAO
12
17
VAUX
SCL
13
16
DIODE
SMBA
14
15
VREF
Solder exposed pad to ground.
Pin Functions
PIN
NAME
NO.
Exposed Pad
Pad
DESCRIPTION
Exposed pad of TSSOP package
Solder to the ground plane to reduce thermal resistance
OUT
1
Output feedback
Connect to the output rail (external MOSFET source). Internally used to determine the MOSFET VDS voltage for
power limiting and to monitor the output voltage.
GATE
2
Gate drive output
Connect to the external MOSFET's gate.
SENSE
3
Current sense input
The voltage across the current sense resistor (RSNS) is measured from VIN_K to this pin. If the voltage across RSNS
reaches overcurrent threshold the load current is limited and the fault timer activates.
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Pin Functions (continued)
PIN
NAME
DESCRIPTION
NO.
VIN_K
4
Positive supply Kelvin pin
The input voltage is measured on this pin.
VIN
5
Positive supply input
This pin is the input supply connection for the device.
N/C
6
No connection
UVLO/EN
7
Undervoltage lockout
An external resistor divider from the system input voltage sets the undervoltage turn-on threshold. An internal 20-µA
current source provides hysteresis. The enable threshold at the pin is nominally 2.48 V. This pin can also be used
for remote shutdown control.
OVLO
8
Overvoltage lockout
An external resistor divider from the system input voltage sets the overvoltage turn-off threshold. An internal 21-µA
current source provides hysteresis. The disable threshold at the pin is 2.46 V.
AGND
9
Circuit ground
Analog device ground. Connect to GND at the pin.
GND
10
Circuit ground
SDAI
11
SMBus data input pin
Data input pin for SMBus. Connect to SDAO if the application does not require unidirectional isolation devices.
SDAO
12
SMBus data output pin
Data output pin for SMBus. Connect to SDAI if the application does not require unidirectional isolation devices.
SCL
13
SMBus clock
Clock pin for SMBus
SMBA
14
SMBus alert line
Alert pin for SMBus, active low
VREF
15
Internal reference
Internally generated precision reference used for analog-to-digital conversion. Connect a 1-µF capacitor on this pin
to ground for bypassing.
DIODE
16
External diode
Connect this to a diode-configured MMBT3904 NPN transistor for temperature monitoring.
VAUX
17
Auxiliary voltage input
Auxiliary pin allows voltage telemetry from an external source. Full-scale input of 2.97 V.
ADR2
18
SMBUS address line 2
Tri-state address line. Should be connected to GND, VDD, or left floating.
ADR1
19
SMBUS address line 1
Tri-state address line. Should be connected to GND, VDD, or left floating.
ADR0
20
SMBUS address line 0
Tri-state address line. Should be connected to GND, VDD, or left floating.
VDD
21
Internal sub-regulator output
Internally sub-regulated 4.85-V bias supply. Connect a 1-µF capacitor on this pin to ground for bypassing.
CL
22
Current limit range
Connect this pin to GND or leave floating to set the nominal over-current threshold at 50 mV. Connecting CL to
VDD sets the overcurrent threshold to be 26 mV.
FB
23
Power Good feedback
An external resistor divider from the output sets the output voltage at which the PGD pin switches. The threshold at
the pin is nominally 2.46 V. An internal 20-µA current source provides hysteresis.
RETRY
24
Fault retry input
This pin configures the power up fault retry behavior. When this pin is connected to GND or left floating, the device
will continually try to engage power during a fault. If the pin is connected to VDD, the device will latch off during a
fault.
TIMER
25
Timing capacitor
An external capacitor connected to this pin sets insertion time delay, fault timeout period, and restart timing.
PWR
26
Power limit set
An external resistor connected to this pin, in conjunction with the current sense resistor (RSNS), sets the maximum
power dissipation allowed in the external series pass MOSFET.
N/C
27
No connection
4
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SNVS950C – APRIL 2014 – REVISED JULY 2016
Pin Functions (continued)
PIN
NAME
PGD
DESCRIPTION
NO.
28
Power Good indicator
An open-drain output. This output is high when the voltage at the FB pin is above VFBTH (nominally 2.46 V) and the
input supply is within its undervoltage and overvoltage thresholds. Connect to the output rail (external MOSFET
source) or any other voltage to be monitored.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted)
(1)
VIN, VIN_K, GATE, UVLO/EN, SENSE, PGD to GND
Input voltage
(2)
MIN
MAX
–0.3
100
OVLO, FB, TIMER, PWR to GND
–0.3
7
OUT to GND
–0.3
100
SCL, SDAI, SDAO, CL, ADR0, ADR1, ADR2, VDD, VAUX, DIODE, RETRY to GND
–0.3
6
SENSE to VIN_K, VIN to VIN_K, AGND to GND
–0.3
0.3
Junction temperature
Storage temperature, Tstg
(1)
(2)
–65
UNIT
V
150
°C
150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The GATE pin voltage is typically 13.6 V above VIN when the LM5066I is enabled. Therefore, the Absolute Maximum Rating for VIN
applies only when the LM5066I is disabled, or for a momentary surge to that voltage because the Absolute Maximum Rating for the
GATE pin is also 100 V.
7.2 ESD Ratings
VESD
(1)
(2)
(3)
(1)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins except GATE (2)
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (3)
VALUE
UNIT
± 2000
V
±500
V
The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. 2-kV rating for all pins except GATE
which is rated for 1 kV.
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN, SENSE, OUT voltage
Junction temperature
NOM
MAX
UNIT
10
80
V
–40
125
°C
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7.4 Thermal Information
LM5066I
THERMAL METRIC (1)
PWP
UNIT
28 PINS
Junction-to-ambient thermal resistance (2)
RθJA
35.6
(3)
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance (4)
16.8
ψJT
Junction-to-top characterization parameter (5)
0.5
ψJB
Junction-to-board characterization parameter (6)
16.7
RθJC(bot)
Junction-to-case (bottom) thermal resistance (7)
2.9
(1)
(2)
(3)
(4)
(5)
(6)
(7)
6
19.9
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
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SNVS950C – APRIL 2014 – REVISED JULY 2016
7.5 Electrical Characteristics
Unless otherwise stated, the following conditions apply: VVIN = 48 V, –40°C < TJ < 125°C, VUVLO = 3 V , VOVLO = 0 V, RPWR=
20 kΩ. See (1).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT (VIN PIN)
IIN-EN
Input current, enabled
VUVLO = 3 V and VOVLO = 2 V
5.6
7
PORIT
Power-on reset threshold at VVIN to trigger insertion
timer
mA
VVIN increasing
7.8
9.0
V
POREN
Power-on reset threshold at VVIN to enable all
functions
VVIN increasing
8.6
9.9
V
PORHYS
POREN hysteresis
VVIN decreasing
100
mV
VDD REGULATOR (VDD PIN)
VDD
VDDILIM
VVDD current limit
VDDPOR
VVDD voltage reset threshold
IVDD = 0 mA
4.60
4.90
5.15
IVDD = 10 mA
4.60
4.85
5.15
V
–50
–30
–15
mA
VVDD rising
4.1
V
V
UVLO/EN, OVLO PINS
UVLOTH
UVLO threshold
VUVLO falling
2.41
2.48
2.55
V
UVLOHYS
UVLO hysteresis current
VUVLO = 1 V
16
20
24
µA
UVLOBIAS
UVLO bias current
VUVLO = 3 V
1
µA
OVLOTH
OVLO threshold
VOVLO rising
2.39
2.46
2.53
V
OVLOHYS
OVLO hysteresis current
VOVLO= 1 V
–24
–21
–16
µA
OVLOBIAS
OVLO bias current
VOVLO = 1 V
1
µA
400
mV
1
µA
POWER GOOD (PGD PIN)
PGDVOL
Output low voltage
ISINK = 2 mA
PGDIOH
Off leakage current
VPGD = 80 V
FBTH
FB threshold
VUVLO = 3 V and VOVLO = 2 V
FBHYS
FB hysteresis current
FBLEAK
Off leakage current
100
FB PIN
2.41
2.46
2.52
V
–25
–20
–15
µA
1
µA
VFB = 2.3 V
POWER LIMIT (PWR PIN)
Power limit sense voltage (VVIN_K – VSENSE)
VSENSE – VOUT = 48 V, RPWR = 60 kΩ
7.4
9.4
11.4
mV
VSENSE – VOUT = 48 V, RPWR = 20 kΩ
1.5
3.5
5.7
mV
VSENSE – VOUT = 48 V, RPWR = 20 kΩ,
TJ = 0°C to 85°C
1.85
3.5
5.02
mV
VSENSE – VOUT = 24 V, RPWR = 60 kΩ
15
18.75
22.5
mV
VSENSE – VOUT = 24 V, RPWR = 20 kΩ
5
7.23
10
mV
IPWR
PWR pin current
VPWR = 2.5 V
-20
µA
RSAT(PWR)
PWR pin impedance when disabled
VUVLO = 2 V
120
Ω
GATE CONTROL (GATE PIN)
Source current
Normal operation
–40
–20
–7.5
µA
Fault sink current
VUVLO = 2 V
3.4
4.2
5.3
mA
POR circuit breaker sink current
VVIN_K – VSENSE = 60 mV or VVIN < PORIT,
VGATE = 5 V, OUT = 0 V,
CB/CL ratio bit = 0, CL = 1
90
160
230
mA
IGATE
VGATEZ
Reverse-bias voltage of GATE to OUT Zener diode,
VGATE– VOUT
IZ = –100 µA
12
16.5
18
V
VGATECP
Peak charge pump voltage in normal operation
(VIN = VOUT)
VGATE– VOUT
11
13
15
V
IOUT-EN
OUT bias current, enabled
VIN = VOUT, normal operation
60
80
100
µA
IOUT-DIS
OUT bias current, disabled
–65
–50
–35
µA
OUT PIN
(1)
(2)
(2)
Disabled, OUT = 0 V, VVIN_K = VSENSE
Current out of a pin is indicated as a negative value.
OUT bias current (disabled) due to leakage current through an internal 1-MΩ resistance from SENSE to VOUT.
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Electrical Characteristics (continued)
Unless otherwise stated, the following conditions apply: VVIN = 48 V, –40°C < TJ < 125°C, VUVLO = 3 V , VOVLO = 0 V, RPWR=
20 kΩ. See (1).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
CL = VDD
23.4
26
28.6
CL = GND
45
50
55
Enabled, SENSE = OUT
20
25
35
UNIT
CURRENT LIMIT
VCL
Current limit threshold voltage
(VVIN_K – VSENSE)
ISENSE
SENSE input current
Disabled, OUT = 0 V
66
mV
µA
Enabled, OUT = 0 V
190
220
250
CB/CL ratio bit = 0, ILIM = 50 mV
1.64
1.94
2.23
CB/CL ratio bit = 1, ILIM = 50 mV
3.28
3.87
4.45
CB/CL ratio bit = 0, ILIM = 26 mV
1.5
1.88
2.3
CB/CL ratio bit = 1, ILIM = 26 mV
3.1
3.75
4.45
CB/CL ratio bit = 0, ILIM = 50 mV
76
96
116
CB/CL ratio bit = 1, ILIM = 50 mV
155
193
235
CB/CL ratio bit = 0, ILIM = 26 mV
38
48
58
CB/CL ratio bit = 1, ILIM = 26 mV
76
96
116
3.74
3.9
4.07
V
1
1.2
1.4
V
–3.3
µA
CIRCUIT BREAKER
RTCB
VCB
Circuit breaker to current limit ratio:
(VVIN_K – VSENSE)CB/VCL
Circuit breaker threshold voltage: (VVIN_K – VSENSE)
V/V
mV
TIMER (TIMER PIN)
VTMRH
VTMRL
Upper threshold
Lower threshold
Restart cycles
End of eighth cycle re-enable threshold
Insertion time current
ITIMER
–5.9
Sink current, end of insertion time
Fault detection current
TIMER pin = 2 V
Fault sink current
DCFAULT
0.3
–4.8
V
0.9
1.5
2.1
mA
–90
–75
–60
µA
1.7
2.5
3.2
µA
3.02
V
Fault restart duty cycle
0.5%
INTERNAL REFERENCE
VREF
Reference voltage
2.93
2.97
ADC AND MUX
Resolution
INL
Integral non-linearity
ADC only
tACQUIRE
Acquisition + conversion time
Any channel
tRR
Acquisition round robin time
Cycle all channels
12
Bits
±4
LSB
100
µs
1
ms
TELEMETRY ACCURACY
IINFSR
Current input full-scale range
IINLSB
Current input LSB
VAUXFSR
VAUX input full-scale range
VAUXLSB
VAUX input LSB
VINFSR
Input voltage full-scale range
VINLSB
Input voltage LSB
VOUTFSR
Output voltage full-scale range
VOUTLSB
Output voltage LSB
IINACC
8
Input current absolute accuracy
CL = GND
50
CL = VDD
26
54.4
58
mV
27.0
29
mV
CL = GND
13.30
CL = VDD
6.70
2.93
2.97
µV
µV
3.01
725
86
88.9
91
21.7
86
88.9
V
mV
91
21.7
V
mV
VVIN_K – VSENSE = 22 mV (80% IINFSR),
CL = VDD
–1.75
%
+1.75
VVIN_K – VSENSE = 5 mV (19% IINFSR),
CL = VDD
–6.0
%
+6.0
VVIN_K – VSENSE = 44 mV (80% IINFSR),
CL = GND
–3.5
%
+3.5
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Electrical Characteristics (continued)
Unless otherwise stated, the following conditions apply: VVIN = 48 V, –40°C < TJ < 125°C, VUVLO = 3 V , VOVLO = 0 V, RPWR=
20 kΩ. See (1).
PARAMETER
VACC
VIN, VOUT absolute accuracy
VAUX absolute accuracy
PINACC
Input power accuracy
TEST CONDITIONS
VVIN, VVOUT = 48, 80 V
VVIN, VVOUT = 10 V
MIN
TYP
MAX
–1.25
%
+1.25
–2.5
%
+2.5
–1.25
%
+1.25
VVIN = 48 V, VVIN_K – VSENSE = 22 mV
(80% IINFSR), CL = VDD
–2.5
%
+2.5
VVIN = 48 V, VVIN_K – VSENSE = 5 mV
(19% IINFSR), CL = VDD
–6.5
%
+6.5
VVIN = 48V , VVIN_K – VSENSE= 44 mV
(80% IINFSR), CL = GND
–4.5
%
+4.5
2
10
VAUX = 2.8 V
UNIT
REMOTE DIODE TEMPERATURE SENSOR
TACC
IDIODE
Temperature accuracy using local diode
TA = 25°C to 85°C
Remote diode resolution
External diode current source
9
°C
bits
High level
250
Low level
9.4
µA
25.9
µA
Diode current ratio
325
µA
PMBus PIN THRESHOLDS (SMBA, SDA, SCL)
VIL
Data, clock input low voltage
VIH
Data, clock input high voltage
VOL
Data output low voltage
ISINK = 3 mA
ILEAK
Input leakage current
SDAI,SMBA,SCL = 5 V
0.9
V
2.1
5.5
V
0
0.4
V
1
µA
CONFIGURATION PIN THRESHOLDS (CL, RETRY)
VIH
Threshold voltage
ILEAK
Input leakage current
3
CL, RETRY = 5 V
V
5
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7.6 SMBus Communications Timing Requirements and Definitions
MIN
MAX
UNIT
ƒSMB
SMBus operating frequency
PARAMETER
10
400
kHz
tBUF
Bus free time between stop and start condition
1.3
µs
tHD:STA
Hold time after (repeated) start condition. After this period, the first clock is generated.
0.6
µs
tSU:STA
Repeated start condition setup time
0.6
µs
tSU:STO
Stop condition setup time
0.6
µs
tHD:DAT
Data hold time
85
ns
tSU:DAT
Data setup time
100
tTIMEOUT
Clock low time-out (1)
25
tLOW
Clock low period
1.5
(2)
tHIGH
Clock high period
tLOW:SEXT
Cumulative clock low extend time (slave device) (3)
tLOW:MEXT
Cumulative low extend time (master device) (4)
tF
Clock or data fall time (5)
tR
(1)
(2)
(3)
(4)
(5)
Clock or data rise time
ns
35
µs
0.6
(5)
ms
µs
25
ms
10
ms
20
300
ns
20
300
ns
Devices participating in a transfer will timeout when any clock low exceeds the value of tTIMEOUT,MIN of 25 ms. Devices that have
detected a timeout condition must reset the communication no later than tTIMEOUT,MAX of 35 ms. The maximum value must be adhered
to by both a master and a slave as it incorporates the cumulative stretch limit for both a master (10 ms) and a slave (25 ms).
tHIGH MAX provides a simple method for devices to detect bus idle conditions.
tLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from the initial start to the stop. If a
slave exceeds this time, it is expected to release both its clock and data lines and reset itself.
tLOW:MEXT is the cumulative time a master device is allowed to extend its clock cycles within each byte of a message as defined from
start-to-ack, ack-to-ack, or ack-to-stop.
Rise and fall time is defined as follows: tR = ( VILMAX – 0.15) to (VIHMIN + 0.15); tF = 0.9 VDD to (VILMAX – 0.15)
tR
SCL
tF
tLOW
VIH
VIL
tHIGH
tHD;STA
tHD;DAT
tSU;STA
tSU;STO
tSU;DAT
SDA
VIH
VIL
tBUF
P
S
S
P
Figure 1. SMBus Timing Diagram
10
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7.7 Switching Characteristics
Unless otherwise stated, the following conditions apply: VVIN = 48 V, –40°C < TJ < 125°C, VUVLO = 3 V , VOVLO = 0 V, RPWR=
20 kΩ.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Delay to GATE high
7
9.6
12.2
µs
Delay to GATE low
6
8.5
11
Delay to GATE high
7
9.6
12.2
Delay to GATE low
6
8.5
11
Delay to PGD high
5
7.6
10
Delay to PGD low
7
9.2
12.5
VIN-SENSE stepped from 0 to 80 mV; CL =
GND
30
50
VIN-SENSE stepped from 0 to 150 mV, time
to GATE low, no load
0.36
0.8
UVLO/EN, OVLO PINS
UVLODEL
UVLO delay
OVLODEL
OVLO delay
µs
FB PIN
FBDEL
FB Delay
µs
CURRENT LIMIT
tCL
Response time
µs
CIRCUIT BREAKER
tCB
Response time
µs
TIMER (TIMER PIN)
tFAULT_DELAY
Fault to GATE low delay
TIMER pin reaches the upper threshold
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7.8 Typical Characteristics
Unless otherwise specified, the following conditions apply: TJ = 25°C, VIN = 48 V. All graphs show junction temperature.
300
6
5
VIN = 10V
VIN = 48V
VIN = 80V
4
±50
±25
0
25
50
75
100
TJ - Junction Temperature (ƒC)
125
ISNS - Sense Current (µA)
IIN-EN - Input Current, Enabled (mA)
7
250
200
150
VOUT = 48V
VOUT = 0V
100
50
0
±50
150
±25
0
100
125
150
C002
5.0
IGATE - Fault Sink Current (mA)
IGATE - Normal Operation (µA)
75
Figure 3. Sense Current vs VOUT and TJ
Figure 2. Input Current vs VIN and TJ
±10
±15
±20
±25
4.5
4.0
3.5
3.0
±30
±50
±25
0
25
50
75
100
125
TJ - Junction Temperature (ƒC)
150
±50
±25
0
25
50
75
100
125
TJ - Junction Temperature (ƒC)
C003
Figure 4. Gate Sourcing Current vs TJ
150
C004
Figure 5. Gate Sinking Current vs TJ
14.0
250
VGATE - Normal Operation (V)
IGATE - Circuit Breaker Sink Current (mA)
50
Device Enabled
SPACE
225
200
175
150
125
100
13.5
13.0
12.5
12.0
±50
±25
0
25
50
75
100
125
TJ - Junction Temperature (ƒC)
150
±50
C005
POR event or CB triggered
±25
0
25
50
75
100
TJ - Junction Temperature (ƒC)
125
150
C006
SPACE
Figure 6. Gate Sinking Current vs TJ
12
25
TJ - Junction Temperature (ƒC)
C001
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Figure 7. Gate Voltage vs TJ
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Typical Characteristics (continued)
Unless otherwise specified, the following conditions apply: TJ = 25°C, VIN = 48 V. All graphs show junction temperature.
3.0
UVLOTH - UVLO Threshold (V)
VGATE - Gate Zener Voltage (V)
18.0
17.5
17.0
16.5
2.8
2.6
2.4
2.2
2.0
16.0
±50
±25
0
25
50
75
100
125
±50
150
TJ - Junction Temperature (ƒC)
±25
0
25
75
100
125
150
C008
SPACE
Inject 100 µA into gate node. Measure GATE-SOURCE
Figure 9. UVLO/EN Threshold vs TJ
Figure 8. Gate Clamping Voltage vs TJ
3.0
3.0
2.8
2.8
FBTH - FB Threshold (V)
OVLOTH - OVLO Threshold (V)
50
TJ - Junction Temperature (ƒC)
C007
2.6
2.4
2.2
2.0
2.6
2.4
2.2
2.0
±50
±25
0
25
50
75
100
125
TJ - Junction Temperature (ƒC)
150
±50
±25
Figure 10. OVLO Threshold vs TJ
0
25
50
75
100
125
TJ - Junction Temperature (ƒC)
C009
150
C010
Figure 11. Power Good Feedback Threshold vs TJ
VCL - Current Limit Threshold (mV)
60
55
50
45
40
35
CL = VDD
CL = GND
30
25
20
±50
±25
0
25
50
75
100
TJ - Junction Temperature (ƒC)
125
150
C011
Figure 12. Current Limit Threshold vs TJ
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8 Detailed Description
8.1 Overview
The inline protection functionality of the LM5066I is designed to control the in-rush current to the load after
insertion of a circuit card into a live backplane or other “hot” power source, thereby limiting the voltage sag
on the backplane’s supply voltage and the dV/dt of the voltage applied to the load. The effects on other
circuits in the system are minimized by preventing possible unintended resets. When the circuit card is
removed, a controlled shutdown can be implemented using the LM5066I.
In addition to a programmable current limit, the LM5066I monitors and limits the maximum power dissipation
in the series-pass device to maintain operation within the device safe operating area (SOA). Either current
limiting or power limiting for an extended period of time results in the shutdown of the series-pass device. In
this event, the LM5066I can latch off or repetitively retry based on the hardware setting of the RETRY pin.
When started, the number of retries can be set to none, 1, 2, 4, 8, 16, or infinite. The circuit breaker function
quickly switches off the series-pass device upon detection of a severe overcurrent condition. Programmable
undervoltage lockout (UVLO) and overvoltage lockout (OVLO) circuits shut down the LM5066I when the
system input voltage is outside the desired operating range.
The telemetry capability of the LM5066I provides intelligent monitoring of the input voltage, output voltage,
input current, input power, temperature, and an auxiliary input. The LM5066I also provides a peak capture of
the input power and programmable hardware averaging of the input voltage, current, power, and output
voltage. Warning thresholds which trigger the SMBA pin may be programmed for input and output voltage,
current, power, and temperature through the PMBus interface. Additionally, the LM5066I is capable of
detecting damage to the external MOSFET, Q1.
14
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PGD
FB
OUT
VIN
VIN_K
SENSE
8.2 Functional Block Diagram
LM5066I
20 PA
VDD
REG
VDD
2.46 V
CB
UV
OV
12 bit
ADC
S/ H
Current
Limit
Sense
VAUX
Diode
Temp
Sense
SDAO
20 PA
VDS
GATE
CONTROL
GATE
4.2 mA
160
mA
16.5 V
OUT
Current Limit /
Power Limit
Control
Power Limit
Threshold
48/96/193 mV
Snapshot
Circuit Breaker
Threshold
MEASUREMENT/
FAULT REGISTORS
SCL
SDAI
IDS
CHARGE
PUMP
26/50
mV
Current Limit
Threshold
2.97
VRef
DIODE
1/30
1 M:
VREF
AMUX
1/30
4.8 PA
Insertion
Timer
75 PA
Fault
Timer
20 PA
TIMER
21PA
SMBUS
INTERFACE
TELEMETRY
STATE
MACHINE
ov
2.46 V
TIMER AND GATE
LOGIC CONTROL
uv
SMBA
1.5 mA
End
Insertion
Time
2.5 PA
Fault
Discharge
3.9 V
2.48 V
1.2 V
ADDRESS
DECODER
0.3 V
20 PA
ADR0
UVLO/EN
OVLO
PWR
Insertion Timer
POR
AGND
7.8V
VIN
GND
RETRY
8.6 V
VIN
ADR2
Enable
POR
CL
ADR1
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8.3 Feature Description
8.3.1 Current Limit
The current limit threshold is reached when the voltage across the sense resistor RSNS (VIN_K to SENSE)
exceeds the ILIM threshold (26 mV if CL = VDD and 50 mV if CL = GND). In the current limiting condition, the
GATE voltage is controlled to limit the current in MOSFET Q1. While the current limit circuit is active, the fault
timer is active as described in the Fault Timer and Restart section. If the load current falls below the current limit
threshold before the end of the Fault Timeout Period, the LM5066I resumes usual operation. If the current limit
condition persists for longer than the Fault Timeout Period set by CT, the IIN OC Fault bit in the STATUS_INPUT
(7Ch) register, the INPUT bit in the STATUS_WORD (79h) register, and IIN_OC/PFET_OP_FAULT bit in the
DIAGNOSTIC_WORD (E1h) register is toggled high and SMBA pin is asserted. SMBA toggling can be disabled
using the ALERT_MASK (D8h) register. For proper operation, the RSNS resistor value should be no higher than
200 mΩ. Higher values may create instability in the current limit control loop. The current limit threshold pin value
may be overridden by setting appropriate bits in the DEVICE_SETUP register (D9h).
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Feature Description (continued)
8.3.2 Circuit Breaker
If the load current increases rapidly (for example, the load is short circuited), the current in the sense resistor
(RS) may exceed the current limit threshold before the current limit control loop is able to respond. If the current
exceeds 1.94x or 3.87x (CL = GND) the current limit threshold, Q1 is quickly switched off by the 160-mA
pulldown current at the GATE pin and a Fault Timeout Period begins. When the voltage across RSNS falls below
the circuit breaker (CB) threshold, the 160-mA pulldown current at the GATE pin is switched off, and the gate
voltage of Q1 is then determined by the current limit or the power limit functions. If the TIMER pin reaches 3.9 V
before the current limiting or power limiting condition ceases, Q1 is switched off by the 4.2-mA pulldown current
at the GATE pin as described in the Fault Timer and Restart section. A circuit breaker event causes the CIRCUIT
BREAKER FAULT bit in the STATUS_OTHER (7Fh), STATUS_MFR_SPECIFIC (80h), and
DIAGNOSTIC_WORD (E1h) registers to be toggled high and SMBA pin are asserted unless this feature is
disabled using the ALERT_MASK (D8h) register. The circuit breaker pin configuration may be overridden by
setting appropriate bits in the DEVICE_SETUP (D9h) register.
8.3.3 Power Limit
An important feature of the LM5066I is the MOSFET power limiting. The Power Limit function can be used to
maintain the maximum power dissipation of MOSFET Q1 within the device SOA rating. The LM5066I determines
the power dissipation in Q1 by monitoring its drain-source voltage (SENSE to OUT), and the drain current
through the RSNS (VIN_K to SENSE). The product of the current and voltage is compared to the power limit
threshold programmed by the resistor at the PWR pin. If the power dissipation reaches the limiting threshold, the
GATE voltage is modulated to regulate the current in Q1. While the power limiting circuit is active, the fault timer
is active as described in the Fault Timer and Restart section. If the power limit condition persists for longer than
the Fault Timeout Period set by the timer capacitor, CT, the IIN OC Fault bit in the STATUS_INPUT (7Ch)
register, the INPUT bit in the STATUS_WORD (79h) register, and the IIN_OC/PFET_OP_FAULT bit in the
DIAGNOSTIC_WORD (E1h) register is toggled high and SMBA pin is asserted unless this feature is disabled
using the ALERT_MASK (D8h) register.
8.3.4 UVLO
The series-pass MOSFET (Q1) is enabled when the input supply voltage (VIN) is within the operating range
defined by the programmable UVLO and OVLO levels. Typically the UVLO level at VIN is set with a resistor
divider. Referring to the Functional Block Diagram when VIN is below the UVLO level, the internal 20-µA current
source at UVLO is enabled, the current source at OVLO is off, and Q1 is held off by the 4.2-mA pulldown current
at the GATE pin. As VIN is increased, raising the voltage at UVLO above its threshold the 20 µA current source at
UVLO is switched off, increasing the voltage at UVLO, providing hysteresis for this threshold. With the UVLO/EN
pin above its threshold, Q1 is switched on by the 20-µA current source at the GATE pin if the insertion time delay
has expired.
See the Application and Implementation section for a procedure to calculate the values of the threshold setting
resistors. The minimum possible UVLO level at VIN can be set by connecting the UVLO/EN pin to VIN. In this
case, Q1 is enabled after the insertion time when the voltage at VIN reaches the POR threshold. After power-up,
an UVLO condition causes the INPUT bit in the STATUS_WORD (79h) register, the VIN_UV_FAULT bit in the
STATUS_INPUT (7Ch) register, and the VIN_UNDERVOLTAGE_FAULT bit in the DIAGNOSTIC_WORD (E1h)
registers to be toggled high and SMBA pin is pulled low unless this feature is disabled using the ALERT_MASK
(D8h) register.
8.3.5 OVLO
The series-pass MOSFET (Q1) is enabled when the input supply voltage (VIN) is within the operating range
defined by the programmable UVLO and OVLO levels. If VIN raises the OVLO pin voltage above its threshold, Q1
is switched off by the 4.2-mA pulldown current at the GATE pin, denying power to the load. When the OVLO pin
is above its threshold, the internal 21-µA current source at OVLO is switched on, raising the voltage at OVLO to
provide threshold hysteresis. When VIN is reduced below the OVLO level Q1 is re-enabled. An OVLO condition
toggles the VIN_OV_FAULT bit in the STATUS_INPUT (7Ch) register, the INPUT bit in the STATUS_WORD
(79h) register and the VIN_OVERVOLTAGE_FAULT bit in the DIAGNOSTIC_WORD (E1h) register. The SMBA
pin is pulled low unless this feature is disabled using the ALERT_MASK (D8h) register.
See the Application and Implementation section for a procedure to calculate the threshold setting resistor values.
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Feature Description (continued)
8.3.6 Power Good Pin
The Power Good indicator pin (PGD) is connected to the drain of an internal N-channel MOSFET capable of
sustaining 80 V in the off-state, and transients up to 100 V. An external pullup resistor is required at PGD to an
appropriate voltage to indicate the status to downstream circuitry. The off-state voltage at the PGD pin can be
higher or lower than the voltages at VIN and OUT. PGD is switched high when the voltage at the FB pin exceeds
the PGD threshold voltage. Typically, the output voltage threshold is set with a resistor divider from output to
feedback, although the monitored voltage need not be the output voltage. Any other voltage can be monitored as
long as the voltage at the FB pin does not exceed its maximum rating. Referring to the Functional Block
Diagram, when the voltage at the FB pin is below its threshold, the 20-µA current source at FB is disabled. As
the output voltage increases, taking FB above its threshold, the current source is enabled, sourcing current out of
the pin, raising the voltage at FB to provide threshold hysteresis. The PGD output is forced low when either the
UVLO/EN pin is below its threshold or the OVLO pin is above its threshold. The status of the PGD pin can be
read through the PMBus interface in either the STATUS_WORD (79h) or DIAGNOSTIC_WORD (E1h) registers.
8.3.7 VDD Sub-Regulator
The LM5066I contains an internal linear sub-regulator, which steps down the input voltage to generate a 4.9-V
rail used for powering low voltage circuitry. The VDD sub-regulator should be used as the pullup supply for the
CL, RETRY, ADR2, ADR1, and ADR0 pins if they are to be tied high. It may also be used as the pullup supply
for the PGD and the SMBus signals (SDA, SCL, and SMBA). The VDD sub-regulator is not designed to drive
high currents and should not be loaded with other integrated circuits. The VDD pin is current limited to 30 mA in
order to protect the LM5066I in the event of a short. The sub-regulator requires a ceramic bypass capacitance
having a value of 1 µF or greater to be placed as close to the VDD pin as the PCB layout allows.
8.3.8 Remote Temperature Sensing
The LM5066I is designed to measure temperature remotely using an MMBT3904 NPN transistor. The base and
collector of the MMBT3904 should be connected to the DIODE pin and the emitter to the LM5066I ground. Place
the MMBT3904 near the device that requires temperature sensing. If the temperature of the hot swap pass
MOSFET, Q1, is to be measured, the MMBT3904 should be placed as close to Q1 as the layout allows. The
temperature is measured by means of a change in the diode voltage in response to a step in current supplied by
the DIODE pin. The DIODE pin sources a constant 9.4 µA, but pulses 250 µA once every millisecond to measure
the diode temperature. Take care in the PCB layout to keep the parasitic resistance between the DIODE pin and
the MMBT3904 low so as not to degrade the measurement. In addition it is recommended to make a Kelvin
connection from the emitter of the MMBT3904 to the GND of the part to ensure an accurate measurement.
Additionally, a small 1000-pF bypass capacitor should be placed in parallel with the MMBT3904 to reduce the
effects of noise. The temperature can be read using the READ_TEMPERATURE_1 PMBus command (8Dh). By
default, the temperature fault and warning thresholds of the LM5066I are set to 256°C and are effectively
disabled. These thresholds can be reprogrammed through the PMBus interface using the OT_WARN_LIMIT
(51h) and OT_FAULT_LIMIT (4Fh) commands. If the temperature measurement and protection capability of the
LM5066I are not used, the DIODE pin should be grounded.
Erroneous temperature measurements may result when the device input voltage is below the minimum operating
voltage (10 V), due to VREF dropping out below the nominal voltage (2.97 V). At higher ambient temperatures,
this measurement could read a value higher than the OT_FAULT_LIMIT, and trigger a fault, disabling Q1. In this
case, the faults should be removed and the device reset by writing a 0h, followed by an 80h to the OPERATION
(03h) register.
8.3.9 Damaged MOSFET Detection
The LM5066I is able to detect whether the external MOSFET, Q1, is damaged under certain conditions. If the
voltage across the sense resistor exceeds 4 mV while the GATE voltage is low or the internal logic indicates that
the GATE should be low, the EXT_MOSFET_SHORTED bit in the STATUS_MFR_SPECIFIC (80h) and
DIAGNOSTIC_WORD (E1h) registers are toggled high and the SMBA pin is asserted unless this feature is
disabled using the ALERT_MASK register (D8h). This method effectively determines whether Q1 is shorted
because of damage present between the drain and gate and/or drain and source.
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8.4 Device Functional Modes
8.4.1 Power-Up Sequence
The VIN operating range of the LM5066I is 10 to 80 V, with a transient capability to 100 V. Referring to the and
Figure 13, as the voltage at VIN initially increases, the external N-channel MOSFET (Q1) is held off by an internal
160-mA pulldown current at the GATE pin. The strong pulldown current at the GATE pin prevents an inadvertent
turn-on as the gate-to-drain (Miller) capacitance of the MOSFET is charged. Additionally, the TIMER pin is
initially held at ground. When the VIN voltage reaches the POR threshold the insertion time begins. During the
insertion time, the capacitor at the TIMER pin (CT) is charged by a 4.8-µA current source, and Q1 is held off by a
4.2-mA pulldown current at the GATE pin regardless of the input voltage. The insertion time delay allows ringing
and transients at VIN to settle before Q1 is enabled. The insertion time ends when the TIMER pin voltage reaches
3.9 V. CT is then quickly discharged by an internal 1.5-mA pulldown current. The GATE pin then switches on Q1
when VIN exceeds the UVLO threshold. If VIN is above the UVLO threshold at the end of the insertion time, Q1
the GATE pin charge pump sources 20 µA to charge the gate capacitance of Q1. The maximum voltage from the
gate to source of the Q1 is limited by an internal 16.5-V Zener diode.
As the voltage at the OUT pin increases, the LM5066I monitors the drain current and power dissipation of
MOSFET Q1. In-rush current limiting or power limiting circuits, or both, actively control the current delivered to the
load. During the in-rush limiting interval (t2 in Figure 13), an internal 75-µA fault timer current source charges CT.
If Q1’s power dissipation and the input current reduce below their respective limiting thresholds before the TIMER
pin reaches 3.9 V, the 75-µA current source is switched off, and CT is discharged by the internal 2.5-µA current
sink (t3 in Figure 13). The in-rush limiting no longer engages unless a current-limit condition occurs.
If the TIMER pin voltage reaches 3.9 V before in-rush current limiting or power limiting ceases during t2, a fault is
declared and Q1 is turned off. See the Fault Timer and Restart section for a complete description of the fault
mode.
The LM5066I asserts the SMBA pin after the input voltage has exceeded its POR threshold to indicate that the
volatile memory and device settings are in their default state. The CONFIG_PRESET bit within the
STATUS_MFR_SPECIFIC register (80h) indicates default configuration of warning thresholds and device
operation and remains high until a CLEAR_FAULTS command is received.
VIN
UVLO
VIN
POR
3.9 V
4.8 PA
75 PA
2.5 PA
TIMER
GATE
160 mA
pull-down
4.2 mA pull-down
20 PA source
ILIMIT
Load
Current
2.46 V
FB
PGD
t1
Insertion Time
t2
In rush
Limiting
t3
Normal Operation
Figure 13. Power-Up Sequence (Current Limit Only)
18
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Device Functional Modes (continued)
8.4.2 Gate Control
A charge pump provides the voltage at the GATE pin to enhance the N-channel MOSFET’s gate (Q1). During
normal operating conditions (t3 in Figure 13), the gate of Q1 is held charged by an internal 20-µA current source.
The charge pump peak voltage is roughly 13.5 V, which forces a VGS across Q1 of 13.5 V under normal
operation. When the system voltage is initially applied, the GATE pin is held low by a 160-mA pulldown current.
This helps prevent an inadvertent turn-on of Q1 through its drain-gate capacitance as the applied system voltage
increases.
During the insertion time (t1 in Figure 13) the GATE pin is held low by a 4.2-mA pulldown current. This maintains
Q1 in the off-state until the end of t1, regardless of the voltage at VIN or UVLO. Following the insertion time,
during t2 in Figure 13 the gate voltage of Q1 is modulated to keep the current or power dissipation level from
exceeding the programmed levels. While in the current or power limiting mode, the TIMER pin capacitor is
charging. If the current and power limiting cease before the TIMER pin reaches 3.9 V, the TIMER pin capacitor
then discharges, and the circuit begins normal operation. If the in-rush limiting condition persists such that the
TIMER pin reached 3.9 V during t2, the GATE pin is then pulled low by the 4.2-mA pulldown current. The GATE
pin is then held low until either a power-up sequence is initiated (RETRY pin to VDD), or an automatic retry is
attempted (RETRY pin to GROUND or floating). See the Fault Timer and Restart section. If the system input
voltage falls below the UVLO threshold, or rises above the OVLO threshold, the GATE pin is pulled low by the
4.2-mA pulldown current to switch off Q1.
8.4.3 Fault Timer and Restart
When the current limit or power limit threshold is reached during turn-on, or as a result of a fault condition, the
gate-to-source voltage of Q1 is modulated to regulate the load current and power dissipation in Q1. When either
limiting function is active, a 75-µA fault timer current source charges the external capacitor (CT) at the TIMER pin
as shown in Figure 13 (fault timeout period). If the fault condition subsides during the fault timeout period before
the TIMER pin reaches 3.9 V, the LM5066I returns to the normal operating mode and CT is discharged by the
1.5-mA current sink. If the TIMER pin reaches 3.9 V during the fault timeout period, Q1 is switched off by a 4.2mA pulldown current at the GATE pin. The subsequent restart procedure then depends on the selected retry
configuration.
If the RETRY pin is high, the LM5066I latches the GATE pin low at the end of the fault timeout period. CT is then
discharged to ground by the 2.5-µA fault current sink. The GATE pin is held low by the 4.2-mA pulldown current
until a power-up sequence is externally initiated by cycling the input voltage (VIN), or momentarily pulling the
UVLO/EN pin below its threshold with an open-collector or open-drain device as shown in Figure 14. The voltage
at the TIMER pin must be
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