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LM5066
SNVS655I – JUNE 2011 – REVISED JANUARY 2016
LM5066 10 to 80 V, Hotswap Controller With I/V/P Monitoring and PMBus™ Interface
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
LM5066 provides robust protection and precision
monitoring for 10- to 80-V systems. Programmable
UV, OV, ILIMIT, and fast-short circuit protection allow
for customized protection for any application.
Programmable FET SOA protection sets the
maximum power the FET is allowed to dissipate
under any condition. The programmable fault timer
(tFAULT) is set to avoid nuisance trips, ensure start-up,
and limit the duration of over load events.
1
•
•
•
•
10- to 80-V Operation
100-V Continuous Absolute Max
26 mV (±12%) or 50 mV (±6%) ILIM Threshold
Programmable FET SOA Protection
Programable UV, OV, tFAULT Thresholds
External FET Temperature Sensing
Failed FET Detection
I2C / SMBus Interface
PMBus™ Compliant Command Structure
Precision V IN, VOUT, IIN, PIN, VAUX Monitoring
– V (±2.7%); I (±3%); P (±4.5%)
Programable I/V/P Averaging Interval
12-bit ADC with 1-kHz Sampling Rate
–40°C < TJ < 125°C Operation
Pin-to-Pin Compatible with LM5066I
In addition to circuit protection, the LM5066 supplies
real-time power, voltage, current, temperature, and
fault data to the system management host through
the I2C / SMBus interface. PMBus compliant
command structure makes it easy to program the
device. Precision telemetry enables intelligent power
management
functions
such
as
efficiency
optimization and early fault detection. LM5066 also
supports advanced features such as I/V/P averaging
and peak power measurment to improve system
diagnostics.
2 Applications
•
•
•
•
•
LM5066I is pin-to-pin compatible with the LM5066
and offers improved telemetry accuracy and supports
the Read_Ein command to monitor energy. See
Table 1 for a detailed comparison.
48-V Servers
Base Station Power Distribution
Networking Routers and Switchers
PLC Power Management
24- to 28-V Industrial Systems
Device Information(1)
PART NUMBER
LM5066
PACKAGE
BODY SIZE (NOM)
9.70 × 4.40 mm2
PWP (28)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
SPACE
Simplified Schematic
VOUT
RSNS
D1
Z1
R1
Q1
R3
SENSE
VIN_K
VIN
GATE OUT DIODE
FB
SMBus
Interface
R4
AGND
GND
LM5066
PGD
ADR2
ADR1
ADR0
CL
SMBA
RETRY
SDAO
VAUX
SDAI
SCL
VDD VREF PWR TIMER
1 PF
R5
VDD
R6
UVLO/EN
OVLO
R2
48-V Bus
1 PF
RPWR
COUT
Card to Card Communication
CIN
LM5066 in a Plug-in Card
Q2
VIN
PMBus Hotswap
Manages Inrush,
Faults, and
Monitoring
48 V
12 V
DC/DC
Load 1
Load 2
I/V/P info
via PMBus
Regulate Loads to
Micro
Controller Optimize Efficiency
Plug-in Card
CTIMER
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM5066
SNVS655I – JUNE 2011 – REVISED JANUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
5
7.1
7.2
7.3
7.4
7.5
7.6
Absolute Maximum Ratings ..................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics........................................... 7
SMBus Communications Timing Requirements and
Definitions ................................................................ 10
7.7 Switching Characteristics ........................................ 11
7.8 Typical Performance Characteristics ...................... 12
8
Detailed Description ............................................ 16
8.1
8.2
8.3
8.4
8.5
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
16
17
17
20
23
Application and Implementation ........................ 43
9.1 Application Information............................................ 43
9.2 Typical Application ................................................. 43
10 Power Supply Recommendations ..................... 54
11 Layout................................................................... 55
11.1 Layout Guidelines ................................................. 55
11.2 Layout Example .................................................... 55
12 Device and Documentation Support ................. 57
12.1 Trademarks ........................................................... 57
12.2 Electrostatic Discharge Caution ............................ 57
12.3 Glossary ................................................................ 57
13 Mechanical, Packaging, and Orderable
Information ........................................................... 57
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (July 2014) to Revision I
•
Page
Changed VGATEZ MIN value in Electrical Characteristics From: 15 V To: 12 V ..................................................................... 7
Changes from Revision G (February 2013) to Revision H
Page
•
Updated data sheet to new TI standards: added new sections and reordered document flow ............................................ 1
•
Added link to LM5066 design calculator .............................................................................................................................. 43
Changes from Revision F (February 2013) to Revision G
•
Changed layout of National Data Sheet to TI format ............................................................................................................. 1
Changes from Revision A (May 2014) to Revision B
•
2
Page
Page
Changed title of Handling Ratings table to ESD Ratings table ............................................................................................. 5
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SNVS655I – JUNE 2011 – REVISED JANUARY 2016
5 Device Comparison Table
Table 1 summarizes the differences between the LM5066 and the LM5066I. Note that the current monitoring
accuracy of the LM5066I is much better at the ILIM = 26 mV setting, but is comparable at the 50-mV setting. For
many applications with lower power, using the LM5066 at the 50-mV setting is a great option. However, for
higher power applications upgrading to LM5066I and using the ILIM = 26 mV setting will lead to significant power
savings (approximately 24 mV × ILOAD). In addition, the higher accuracy and energy monitoring capability can
enable further improvements in system efficiency, which is critical in high power applications.
Table 1. LM5066 vs LM5066I
KEY PARAMETERS
LM5066
LM5066I
Voltage monitoring
±2.7%
±1.25%
Current monitoring (ILIM = 26 mV)
±4.25%
±1.75%
Power monitoring (ILIM = 26 mV)
±4.5%
±.2.5%
Current monitoring (ILIM = 50 mV)
±3%
±3.5%
Power monitoring (ILIM = 50 mV)
±4.5%
±4.5%
No
Yes
Supports Energy Monitoring via
Read_EIN command
6 Pin Configuration and Functions
PWP Package
28-Pin
Top View
OUT
1
28
PGD
GATE
2
27
NC
SENSE
3
26
PWR
VIN_K
4
25
TIMER
VIN
5
24
RETRY
NC
6
23
FB
UVLO/EN
7
22
CL
OVLO
8
21
VDD
AGND
9
20
ADR0
GND
10
19
ADR1
SDAI
11
18
ADR2
SDAO
12
17
VAUX
SCL
13
16
DIODE
SMBA
14
15
VREF
Solder exposed pad to ground.
Pin Functions
PIN
NAME
NO.
Exposed Pad
Pad
DESCRIPTION
Exposed pad of TSSOP package
Solder to the ground plane to reduce thermal resistance
OUT
1
Output feedback
Connect to the output rail (external MOSFET source). Internally used to determine the MOSFET VDS voltage for
power limiting and to monitor the output voltage.
GATE
2
Gate drive output
Connect to the external MOSFET's gate.
SENSE
3
Current sense input
The voltage across the current sense resistor (RSNS) is measured from VIN_K to this pin. If the voltage across RSNS
reaches overcurrent threshold the load current is limited and the fault timer activates.
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Pin Functions (continued)
PIN
NAME
DESCRIPTION
NO.
VIN_K
4
Positive supply Kelvin pin
The input voltage is measured on this pin.
VIN
5
Positive supply input
This pin is the input supply connection for the device.
N/C
6
No connection
UVLO/EN
7
Undervoltage lockout
An external resistor divider from the system input voltage sets the undervoltage turn-on threshold. An internal 20-µA
current source provides hysteresis. The enable threshold at the pin is nominally 2.48 V. This pin can also be used
for remote shutdown control.
OVLO
8
Overvoltage lockout
An external resistor divider from the system input voltage sets the overvoltage turn-off threshold. An internal 21-µA
current source provides hysteresis. The disable threshold at the pin is 2.46 V.
AGND
9
Circuit ground
Analog device ground. Connect to GND at the pin.
GND
10
Circuit ground
SDAI
11
SMBus data input pin
Data input pin for SMBus. Connect to SDAO if the application does not require unidirectional isolation devices.
SDAO
12
SMBus data output pin
Data output pin for SMBus. Connect to SDAI if the application does not require unidirectional isolation devices.
SCL
13
SMBus clock
Clock pin for SMBus
SMBA
14
SMBus alert line
Alert pin for SMBus, active low
VREF
15
Internal reference
Internally generated precision reference used for analog-to-digital conversion. Connect a 1-µF capacitor on this pin
to ground for bypassing.
DIODE
16
External diode
Connect this to a diode-configured MMBT3904 NPN transistor for temperature monitoring.
VAUX
17
Auxiliary voltage input
Auxiliary pin allows voltage telemetry from an external source. Full-scale input of 2.97 V.
ADR2
18
SMBUS address line 2
Tri-state address line. Should be connected to GND, VDD, or left floating.
ADR1
19
SMBUS address line 1
Tri-state address line. Should be connected to GND, VDD, or left floating.
ADR0
20
SMBUS address line 0
Tri-state address line. Should be connected to GND, VDD, or left floating.
VDD
21
Internal sub-regulator output
Internally sub-regulated 4.85-V bias supply. Connect a 1-µF capacitor on this pin to ground for bypassing.
CL
22
Current limit range
Connect this pin to GND or leave floating to set the nominal over-current threshold at 50 mV. Connecting CL to
VDD sets the overcurrent threshold to be 26 mV.
FB
23
Power Good feedback
An external resistor divider from the output sets the output voltage at which the PGD pin switches. The threshold at
the pin is nominally 2.46 V. An internal 20-µA current source provides hysteresis.
RETRY
24
Fault retry input
This pin configures the power up fault retry behavior. When this pin is connected to GND or left floating, the device
will continually try to engage power during a fault. If the pin is connected to VDD, the device will latch off during a
fault.
TIMER
25
Timing capacitor
An external capacitor connected to this pin sets insertion time delay, fault timeout period, and restart timing.
PWR
26
Power limit set
An external resistor connected to this pin, in conjunction with the current sense resistor (RSNS), sets the maximum
power dissipation allowed in the external series pass MOSFET.
N/C
27
No connection
4
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Pin Functions (continued)
PIN
NAME
PGD
DESCRIPTION
NO.
28
Power Good indicator
An open-drain output. This output is high when the voltage at the FB pin is above VFBTH (nominally 2.46 V) and the
input supply is within its undervoltage and overvoltage thresholds. Connect to the output rail (external MOSFET
source) or any other voltage to be monitored.
7 Specifications
7.1 Absolute Maximum Ratings
(1)
over operating free-air temperature (unless otherwise noted)
Input voltage
MIN
MAX
VIN, VIN_K, GATE, UVLO/EN, SENSE, PGD to GND
–0.3
100
OVLO, FB, TIMER, PWR to GND
–0.3
7
OUT to GND
–0.3
100
–1
100
OUT to GND (1-ms transient)
SCL, SDAI, SDAO, CL, ADR0, ADR1, ADR2, VDD, VAUX, DIODE, RETRY to GND
–0.3
6
SENSE to VIN_K, VIN to VIN_K, AGND to GND
–0.3
0.3
Junction temperature
Storage temperature, Tstg
(1)
–65
UNIT
V
150
°C
150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VESD
(1)
(2)
(3)
(1)
Electrostatic
discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins except GATE
(2)
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (3)
VALUE
UNIT
± 2000
V
±500
V
The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. 2-kV rating for all pins except GATE
which is rated for 1 kV.
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VIN, SENSE, OUT voltage
Junction temperature
NOM
MAX
UNIT
10
80
V
–40
125
°C
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7.4 Thermal Information
LM5066
THERMAL METRIC (1)
PWP
UNIT
28 PINS
Junction-to-ambient thermal resistance (2)
RθJA
35.6
(3)
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance (4)
16.8
ψJT
Junction-to-top characterization parameter (5)
0.5
ψJB
Junction-to-board characterization parameter (6)
16.7
RθJC(bot)
Junction-to-case (bottom) thermal resistance (7)
2.9
(1)
(2)
(3)
(4)
(5)
(6)
(7)
6
19.9
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining RθJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
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7.5 Electrical Characteristics
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C
to +125°C unless otherwise stated. Minimum and maximum limits are ensured through test, design, or statistical correlation.
Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless
otherwise stated the following conditions apply: VIN = 48 V. See (1) and (2).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT (VIN PIN)
IIN-EN
Input current, enabled
VUVLO = 3 V and VOVLO = 2 V
7.2
9.5
mA
PORIT
Power-on reset threshold at VIN to
trigger insertion timer
VIN increasing
7.8
9.0
V
POREN
Power-on reset threshold at VIN to
enable all functions
VIN increasing
8.6
9.9
V
PORHYS
POREN hysteresis
VIN decreasing
120
mV
VDD REGULATOR (VDD PIN)
VDD
IVDD = 0 mA
4.60
IVDD = 10 mA
VDDILIM
VDD current limit
VDDPOR
VDD voltage reset threshold
4.90
5.15
V
4.85
–25
VDD rising
–30
V
–42
mA
4.1
V
UVLO/EN, OVLO PINS
UVLOTH
UVLO threshold
VUVLO falling
2.41
2.48
2.55
V
UVLOHYS
UVLO hysteresis current
UVLO = 1 V
13
20
26
µA
UVLOBIAS
UVLO bias current
UVLO = 3 V
1
µA
OVLOTH
OVLO threshold
VOVLO rising
2.39
2.46
2.53
V
OVLOHYS
OVLO hysteresis current
OVLO = 1 V
–26
–21
–13
µA
OVLOBIAS
OVLO bias current
OVLO = 1 V
1
µA
110
mV
1
µA
POWER GOOD (PGD PIN)
PGDVOL
Output low voltage
ISINK = 2 mA
PGDIOH
Off leakage current
VPGD = 80 V
FBTH
FB threshold
VUVLO = 3 V and VOVLO = 2 V
FBHYS
FB hysteresis current
FBLEAK
Off leakage current
60
FB PIN
2.41
2.46
2.52
V
–25
–20
–15
µA
1
µA
22.5
mV
VFB = 2.3 V
POWER LIMIT (PWR PIN)
PWRLIM
Power limit sense voltage (VIN-SENSE)
SENSE-OUT = 48 V, RPWR = 121 kΩ
16.5
SENSE-OUT = 24 V, RPWR = 75 kΩ
19.5
23
mV
IPWR
PWR pin current
VPWR = 2.5 V
–20
µA
RSAT(PWR)
PWR pin impedance when disabled
UVLO = 2 V
135
Ω
GATE CONTROL (GATE PIN)
IGATE
Source current
Normal Operation
–26
Fault sink current
UVLO = 2 V
3.4
POR circuit breaker sink current
VIN – SENSE = 150 mV or VIN < PORIT,
VGATE = 5 V
50
VGATEZ
Reverse-bias voltage of GATE to OUT
zener diode
GATE – OUT
12
16.5
VGATECP
Peak charge pump voltage in normal
operation (VIN = VOUT)
GATE – OUT
(1)
(2)
–20
–10
µA
4.2
5.3
mA
115
180
mA
18
V
13.6
V
Current out of a pin is indicated as a negative value.
All electrical characteristics having room temperature limits are tested during production at TA = 25°C. All hot and cold limits are
specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
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Electrical Characteristics (continued)
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C
to +125°C unless otherwise stated. Minimum and maximum limits are ensured through test, design, or statistical correlation.
Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless
otherwise stated the following conditions apply: VIN = 48 V. See (1) and (2).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUT PIN
IOUT-EN
OUT bias current, enabled
IOUT-DIS
OUT bias current, disabled
OUT = VIN, Normal operation
(3)
Disabled, OUT = 0 V, SENSE = VIN
78
µA
–50
µA
CURRENT LIMIT
VCL
ISENSE
Current limit threshold voltage
(VIN – VSENSE)
CL = VDD
23
26
29
CL = GND
47
50
53
SENSE input current
Enabled, SENSE = OUT
25
Disabled, OUT = 0 V
66
Enabled, OUT = 0 V
220
mV
µA
CIRCUIT BREAKER
RTCB
Circuit breaker to current limit ratio: (VIN
-VSENSE)CB/VCL
CB/CL ratio bit = 0, ILim = 50 mV
1.64
1.94
2.23
CB/CL ratio bit = 1, ILim = 50 mV
3.28
3.87
4.45
CB/CL ratio bit = 0, ILim = 26 mV
1.88
CB/CL ratio bit = 1, ILim = 26 mV
VCB
Circuit breaker threshold voltage:
(VIN – VSENSE)
V/V
3.75
CB/CL ratio bit = 0, ILim = 50 mV
80
96
110
CB/CL ratio bit = 1, ILim = 50 mV
164
193
222
mV
CB/CL ratio bit = 0, ILim = 26 mV
39
48
57
CB/CL ratio bit = 1, ILim = 26 mV
79
96
113
3.74
3.9
4.07
V
0.98
1.1
1.24
V
TIMER (TIMER PIN)
VTMRH
Upper threshold
VTMRL
Lower threshold
ITIMER
Insertion time current
DCFAULT
Restart cycles
End of eighth cycle
0.3
V
Re-enable threshold
0.3
V
–5.9
–4.8
–3.3
µA
Sink current, end of insertion time
TIMER pin = 2 V
1.0
1.5
2.0
mA
Fault detection current
–95
–75
–50
µA
Fault sink current
1.7
2.5
3.2
µA
Fault restart duty cycle
0.5
%
INTERNAL REFERENCE
VREF
Reference voltage
2.93
2.97
3.02
V
ADC AND MUX
Resolution
INL
Integral non-linearity
ADC only
tACQUIRE
Acquisition + Conversion time
Any channel
tRR
Acquisition round robin time
Cycle all channels
(3)
8
12
Bits
±4
LSB
100
µs
1
ms
OUT bias current (disabled) due to leakage current through an internal 1 MΩ resistance from SENSE to VOUT.
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Electrical Characteristics (continued)
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C
to +125°C unless otherwise stated. Minimum and maximum limits are ensured through test, design, or statistical correlation.
Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless
otherwise stated the following conditions apply: VIN = 48 V. See (1) and (2).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TELEMETRY ACCURACY
IINFSR
IINLSB
Current input full-scale range
Current input LSB
CL = GND
75.8
mV
CL = VDD
38.2
mV
CL = GND
18.5
µV
CL = VDD
9.3
µV
2.97
V
µV
VAUXFSR
VAUX input full-scale range
VAUXLSB
VAUX input LSB
725
VINFSR
Input voltage full-scale range
89.3
V
VINLSB
Input voltage LSB
21.8
mV
IINACC
Input current accuracy
VIN – SENSE = 50 mV, CL = GND
–3.0
+3.0
%
VIN – SENSE = 25 mV, CL = VDD
-4.25
4.25
%
VACC
VAUX, VIN, VOUT
VIN, VOUT = 48 V
VAUX = 2.8V
–2.7
+2.7
%
PINACC
Input power accuracy
VIN = 48 V, VIN – SENSE = 50mV,
CL = VDD
–4.5
+4.5
%
REMOTE DIODE TEMPERATURE SENSOR
TACC
Temperature accuracy using local diode
TA = 25°C to 85°C
2
Remote diode resolution
IDIODE
External diode current source
10
9
High level
250
Low level
9.4
Diode current ratio
°C
bits
325
µA
µA
25.9
PMBus PIN THRESHOLDS (SMBA, SDA, SCL)
VIL
Data, clock input low voltage
VIH
Data, clock input high voltage
VOL
Data output low voltage
ISINK = 3 mA
ILEAK
Input leakage current
SDAI, SMBA,SCL = 5 V
0.9
V
2.1
5.5
V
0
0.4
V
1
µA
CONFIGURATION PIN THRESHOLDS (CL, RETRY)
VIH
Threshold voltage
ILEAK
Input leakage current
3
CL, RETRY = 5 V
V
5
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7.6 SMBus Communications Timing Requirements and Definitions
MIN
MAX
UNIT
ƒSMB
SMBus operating frequency
PARAMETER
10
400
kHz
tBUF
Bus free time between stop and start condition
1.3
µs
tHD:STA
Hold time after (repeated) start condition. After this period, the first clock is generated.
0.6
µs
tSU:STA
Repeated start condition setup time
0.6
µs
tSU:STO
Stop condition setup time
0.6
µs
tHD:DAT
Data hold time
85
ns
tSU:DAT
Data setup time
100
tTIMEOUT
Clock low time-out (1)
25
tLOW
Clock low period
1.5
(2)
tHIGH
Clock high period
tLOW:SEXT
Cumulative clock low extend time (slave device) (3)
tLOW:MEXT
Cumulative low extend time (master device) (4)
tF
Clock or data fall time (5)
tR
(1)
(2)
(3)
(4)
(5)
Clock or data rise time
ns
35
µs
0.6
(5)
ms
µs
25
ms
10
ms
20
300
ns
20
300
ns
Devices participating in a transfer will timeout when any clock low exceeds the value of tTIMEOUT,MIN of 25 ms. Devices that have
detected a timeout condition must reset the communication no later than tTIMEOUT,MAX of 35 ms. The maximum value must be adhered
to by both a master and a slave as it incorporates the cumulative stretch limit for both a master (10 ms) and a slave (25 ms).
tHIGH MAX provides a simple method for devices to detect bus idle conditions.
tLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from the initial start to the stop. If a
slave exceeds this time, it is expected to release both its clock and data lines and reset itself.
tLOW:MEXT is the cumulative time a master device is allowed to extend its clock cycles within each byte of a message as defined from
start-to-ack, ack-to-ack, or ack-to-stop.
Rise and fall time is defined as follows: tR = ( VILMAX – 0.15) to (VIHMIN + 0.15); tF = 0.9 VDD to (VILMAX – 0.15)
tR
SCL
tF
tLOW
VIH
VIL
tHIGH
tHD;STA
tHD;DAT
tSU;STA
tSU;STO
tSU;DAT
SDA
VIH
VIL
tBUF
P
S
S
P
Figure 1. SMBus Timing Diagram
10
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7.7 Switching Characteristics
Unless otherwise stated, the following conditions apply: VVIN = 48 V, –40°C < TJ < 125°C, VUVLO = 3 V , VOVLO = 0 V, RPWR=
20 kΩ.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
UVLO/EN, OVLO PINS
UVLODEL
UVLO delay
OVLODEL
OVLO delay
Delay to GATE high
9
Delay to GATE low
13
Delay to GATE high
13
Delay to GATE low
10
Delay to PGD high
7.6
Delay to PGD low
9.2
VIN-SENSE stepped from 0 to 80 mV; CL =
GND
45
VIN-SENSE stepped from 0 to 150 mV, time
to GATE low, no load
0.42
µs
µs
FB PIN
FBDEL
FB Delay
µs
CURRENT LIMIT
tCL
Response time
µs
CIRCUIT BREAKER
tCB
Response time
0.83
µs
TIMER (TIMER PIN)
tFAULT_DELAY
Fault to GATE low delay
TIMER pin reaches the upper threshold
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7.8 Typical Performance Characteristics
Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 48 V. All graphs show junction temperature.
30
Sense Pin Current - Enabled (µA)
8.0
VIN Input Current (mA)
7.5
7.0
6.5
6.0
5.5
VIN =10V
VIN=48V
VIN=80V
5.0
±50
0
±25
25
50
75
100
125
29
28
27
26
25
24
23
VIN = 48V
22
150
TJ - Junction Temperature (ƒC)
±50
Figure 2. VIN Pin Current
50
75
100
150
C002
Figure 3. Sense Pin Current (Enabled)
120
90
60
VIN = 10V
VIN = 48V
VIN = 80V
30
0
±20
VIN = 10V
VIN=48V
VIN=80V
±40
±60
±80
±100
±50
±25
0
25
50
75
100
125
TJ - Junction Temperature (°C)
150
±50
0
±25
25
50
75
100
125
TJ - Junction Temperature (°C)
C003
Figure 4. Out Pin Current (Enabled)
150
C004
Figure 5. Out Pin Current (Disabled)
17.0
Gate Pin Source Current (µA)
±18
16.8
16.6
16.4
16.2
±19
±19
±20
VIN = 10V to 80V
VIN = 48V
16.0
±20
±50
±25
0
25
50
75
100
TJ - Junction Temperature (ƒC)
125
150
±50
C005
Figure 6. Gate Zener Reverse Bias Voltage (VGATE – VOUT)
12
125
0
Output Pin Current - Disabled (µA)
Output Pin Current - Enabled (µA)
25
TJ - Junction Temperature (ƒC)
150
Gate Pin Voltage (V)
0
±25
C001
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0
25
50
75
100
TJ - Junction Temperature (ƒC)
125
150
C006
Figure 7. Gate Pin Source Current
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Typical Performance Characteristics (continued)
Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 48 V. All graphs show junction temperature.
30
VSNS at Power Limit Threshold (mV)
Gate Pin Sink Current (mA)
5
5
4
4
VIN = 48V
3
20
15
10
5
VIN = 24V
VIN = 48V
VIN = 80V
0
±50
±25
0
25
50
75
100
125
TJ - Junction Temperature (ƒC)
150
±50
±25
0
25
50
75
100
125
150
TJ - Junction Temperature (ƒC)
C007
Figure 8. Gate Pin Sink Current
C008
Figure 9. VSNS At Power Limit Threshold RPWR = 75 kΩ
20.8
UVLO Hystersis Current (µA)
2.50
UVLO Threshold (V)
25
2.48
2.46
2.44
VIN = 10V
20.7
20.6
20.5
VIN = 10V to 80V
VIN = 48V , 80V
20.4
2.42
±50
±25
0
25
50
75
100
125
TJ - Junction Temperature (ƒC)
150
±50
±25
0
25
50
75
100
125
TJ - Junction Temperature (ƒC)
C009
Figure 10. UVLO Threshold
150
C010
Figure 11. UVLO Hysteresis Current
2.48
±23
FB Hysteresis (µA)
FB Threshold (V)
±24
2.46
2.44
±24
±25
±25
±26
9,1 «
2.42
±50
±25
0
25
50
75
100
TJ - Junction Temperature (ƒC)
125
150
Vin = 48V
±26
±50
C011
Figure 12. FB Threshold
±25
0
25
50
75
100
125
TJ - Junction Temperature (ƒC)
150
C012
Figure 13. FB Hysteresis Current
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Typical Performance Characteristics (continued)
2.48
±18
2.47
±20
OVLO Hystersis (µA)
OVLO THRESHOLD (V)
Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 48 V. All graphs show junction temperature.
2.46
2.45
±22
±24
VIN = 10V to 80V
Vin = 10V to 80V
2.44
±26
±50
±25
0
25
50
75
100
125
TJ - Junction Temperature (ƒC)
150
±50
CIRCUIT BREAKER THRESHOLD (mV)
CURRENT LIMIT THRESHOLD (mV)
45
40
CL = VDD
CL = GND
30
25
20
±25
0
25
50
75
25
50
75
100
125
150
C014
Figure 15. OVLO Hysteresis Current
50
±50
0
TJ - Junction Temperature (ƒC)
Figure 14. OVLO Threshold
55
35
±25
C013
100
125
TJ - Junction Temperature (ƒC)
220
200
180
CL = VDD, CB/CL BIT = LOW
160
CL = GND, CB/CL BIT = LOW
140
CL = GND, CB/CL BIT = HIGH
120
100
80
60
40
150
±50
±25
0
25
50
75
100
125
TJ - Junction Temperature (ƒC)
C015
Figure 16. Current Limit Threshold
150
C016
Figure 17. Circuit Breaker Threshold
2.965
0.5
IIN ERROR ( % of FSR)
0.4
VREF (V)
2.960
2.955
2.950
VIN = 48V
2.945
0.3
0.2
0.1
0.0
-0.1
-0.2
-0.3
-0.4
VIN = 48V
-0.5
±50
±25
0
25
50
75
100
TJ - Junction Temperature (ƒC)
125
150
±50
C017
Figure 18. Reference Voltage
14
±25
0
25
50
75
100
125
TJ - Junction Temperature (ƒC)
150
C018
Figure 19. IIN Measurement Accuracy
(VIN – Sense = 50 mV)
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Typical Performance Characteristics (continued)
Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 48 V. All graphs show junction temperature.
300
1.0
Rs = 3mŸ
250
0.6
0.4
PMOSFETILIM) (W)
PIN ERROR (% of FSR)
0.8
0.2
0.0
-0.2
-0.4
-0.6
Rs = 5mŸ
Rs = 10mŸ
200
Rs = 20mŸ
150
100
50
-0.8
VIN = 48V
0
-1.0
±50
±25
0
25
50
75
100
TJ - Junction Temperature (ƒC)
125
150
0
Figure 20. Pin Measurement Accuracy (VIN – Sense = 50
mV)
25
50
75
100
125
RPWR (kŸ)
C019
150
C020
Figure 21. MOSFET Power Dissipation Limit vs RPWR And RS
(VIN = 48 V)
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8 Detailed Description
8.1 Overview
The inline protection functionality of the LM5066 is designed to control the in-rush current to the load after
insertion of a circuit card into a live backplane or other “hot” power source, thereby limiting the voltage sag
on the backplane’s supply voltage and the dV/dt of the voltage applied to the load. The effects on other
circuits in the system are minimized by preventing possible unintended resets. When the circuit card is
removed, a controlled shutdown can be implemented using the LM5066.
In addition to a programmable current limit, the LM5066 monitors and limits the maximum power dissipation
in the series-pass device to maintain operation within the device safe operating area (SOA). Either current
limiting or power limiting for an extended period of time results in the shutdown of the series-pass device. In
this event, the LM5066 can latch off or repetitively retry based on the hardware setting of the RETRY pin.
When started, the number of retries can be set to none, 1, 2, 4, 8, 16, or infinite. The circuit breaker function
quickly switches off the series-pass device upon detection of a severe overcurrent condition. Programmable
undervoltage lockout (UVLO) and overvoltage lockout (OVLO) circuits shut down the LM5066 when the
system input voltage is outside the desired operating range.
The telemetry capability of the LM5066 provides intelligent monitoring of the input voltage, output voltage,
input current, input power, temperature, and an auxiliary input. The LM5066 also provides a peak capture of
the input power and programmable hardware averaging of the input voltage, current, power, and output
voltage. Warning thresholds which trigger the SMBA pin may be programmed for input and output voltage,
current, power, and temperature through the PMBus interface. Additionally, the LM5066 is capable of
detecting damage to the external MOSFET, Q1.
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PGD
FB
OUT
VIN
VIN_K
SENSE
8.2 Functional Block Diagram
LM5066
20 PA
VDD
REG
VDD
2.46 V
CB
UV
OV
12 bit
ADC
S/ H
Current
Limit
Sense
VAUX
Diode
Temp
Sense
SDAO
20 PA
VDS
GATE
CONTROL
GATE
4.2 mA
115
mA
16.5 V
OUT
Current Limit /
Power Limit
Control
Power Limit
Threshold
48/96/193 mV
Snapshot
Circuit Breaker
Threshold
MEASUREMENT/
FAULT REGISTORS
SCL
SDAI
IDS
CHARGE
PUMP
26/50
mV
Current Limit
Threshold
2.97
VRef
DIODE
1/30
1 M:
VREF
AMUX
1/30
4.8 PA
Insertion
Timer
75 PA
Fault
Timer
20 PA
TIMER
21PA
SMBUS
INTERFACE
TELEMETRY
STATE
MACHINE
ov
2.46 V
TIMER AND GATE
LOGIC CONTROL
uv
SMBA
1.5 mA
End
Insertion
Time
2.5 PA
Fault
Discharge
3.9 V
2.48 V
1.1 V
ADDRESS
DECODER
0.3 V
20 PA
ADR0
UVLO/EN
OVLO
PWR
Insertion Timer
POR
AGND
7.8V
VIN
GND
RETRY
8.6 V
VIN
ADR2
Enable
POR
CL
ADR1
8.3 Feature Description
8.3.1 Current Limit
The current limit threshold is reached when the voltage across the sense resistor RSNS (VIN_K to SENSE)
exceeds the ILIM threshold (26 mV if CL = VDD and 50 mV if CL = GND). In the current limiting condition, the
GATE voltage is controlled to limit the current in MOSFET Q1. While the current limit circuit is active, the fault
timer is active as described in the Fault Timer and Restart section. If the load current falls below the current limit
threshold before the end of the Fault Timeout Period, the LM5066 resumes usual operation. If the current limit
condition persists for longer than the Fault Timeout Period set by CT, the IIN OC Fault bit in the STATUS_INPUT
(7Ch) register, the INPUT bit in the STATUS_WORD (79h) register, and IIN_OC/PFET_OP_FAULT bit in the
DIAGNOSTIC_WORD (E1h) register is toggled high and SMBA pin is asserted. SMBA toggling can be disabled
using the ALERT_MASK (D8h) register. For proper operation, the RSNS resistor value should be no higher than
200 mΩ. Higher values may create instability in the current limit control loop. The current limit threshold pin value
may be overridden by setting appropriate bits in the DEVICE_SETUP register (D9h).
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Feature Description (continued)
8.3.2 Circuit Breaker
If the load current increases rapidly (for example, the load is short circuited), the current in the sense resistor
(RS) may exceed the current limit threshold before the current limit control loop is able to respond. If the current
exceeds 1.94x or 3.87x (CL = GND) the current limit threshold, Q1 is quickly switched off by the 160-mA
pulldown current at the GATE pin and a Fault Timeout Period begins. When the voltage across RSNS falls below
the circuit breaker (CB) threshold, the 115-mA pulldown current at the GATE pin is switched off, and the gate
voltage of Q1 is then determined by the current limit or the power limit functions. If the TIMER pin reaches 3.9 V
before the current limiting or power limiting condition ceases, Q1 is switched off by the 4.2-mA pulldown current
at the GATE pin as described in the Fault Timer and Restart section. A circuit breaker event causes the CIRCUIT
BREAKER FAULT bit in the STATUS_OTHER (7Fh), STATUS_MFR_SPECIFIC (80h), and
DIAGNOSTIC_WORD (E1h) registers to be toggled high and SMBA pin are asserted unless this feature is
disabled using the ALERT_MASK (D8h) register. The circuit breaker pin configuration may be overridden by
setting appropriate bits in the DEVICE_SETUP (D9h) register.
8.3.3 Power Limit
An important feature of the LM5066 is the MOSFET power limiting. The Power Limit function can be used to
maintain the maximum power dissipation of MOSFET Q1 within the device SOA rating. The LM5066 determines
the power dissipation in Q1 by monitoring its drain-source voltage (SENSE to OUT), and the drain current
through the RSNS (VIN_K to SENSE). The product of the current and voltage is compared to the power limit
threshold programmed by the resistor at the PWR pin. If the power dissipation reaches the limiting threshold, the
GATE voltage is modulated to regulate the current in Q1. While the power limiting circuit is active, the fault timer
is active as described in the Fault Timer and Restart section. If the power limit condition persists for longer than
the Fault Timeout Period set by the timer capacitor, CT, the IIN OC Fault bit in the STATUS_INPUT (7Ch)
register, the INPUT bit in the STATUS_WORD (79h) register, and the IIN_OC/PFET_OP_FAULT bit in the
DIAGNOSTIC_WORD (E1h) register is toggled high and SMBA pin is asserted unless this feature is disabled
using the ALERT_MASK (D8h) register.
8.3.4 UVLO
The series-pass MOSFET (Q1) is enabled when the input supply voltage (VIN) is within the operating range
defined by the programmable UVLO and OVLO levels. Typically the UVLO level at VIN is set with a resistor
divider. Referring to the Functional Block Diagram when VIN is below the UVLO level, the internal 20-µA current
source at UVLO is enabled, the current source at OVLO is off, and Q1 is held off by the 4.2-mA pulldown current
at the GATE pin. As VIN is increased, raising the voltage at UVLO above its threshold the 20 µA current source at
UVLO is switched off, increasing the voltage at UVLO, providing hysteresis for this threshold. With the UVLO/EN
pin above its threshold, Q1 is switched on by the 20-µA current source at the GATE pin if the insertion time delay
has expired.
See the Application and Implementation section for a procedure to calculate the values of the threshold setting
resistors. The minimum possible UVLO level at VIN can be set by connecting the UVLO/EN pin to VIN. In this
case, Q1 is enabled after the insertion time when the voltage at VIN reaches the POR threshold. After power-up,
an UVLO condition causes the INPUT bit in the STATUS_WORD (79h) register, the VIN_UV_FAULT bit in the
STATUS_INPUT (7Ch) register, and the VIN_UNDERVOLTAGE_FAULT bit in the DIAGNOSTIC_WORD (E1h)
registers to be toggled high and SMBA pin is pulled low unless this feature is disabled using the ALERT_MASK
(D8h) register.
8.3.5 OVLO
The series-pass MOSFET (Q1) is enabled when the input supply voltage (VIN) is within the operating range
defined by the programmable UVLO and OVLO levels. If VIN raises the OVLO pin voltage above its threshold, Q1
is switched off by the 4.2-mA pulldown current at the GATE pin, denying power to the load. When the OVLO pin
is above its threshold, the internal 21-µA current source at OVLO is switched on, raising the voltage at OVLO to
provide threshold hysteresis. When VIN is reduced below the OVLO level Q1 is re-enabled. An OVLO condition
toggles the VIN_OV_FAULT bit in the STATUS_INPUT (7Ch) register, the INPUT bit in the STATUS_WORD
(79h) register and the VIN_OVERVOLTAGE_FAULT bit in the DIAGNOSTIC_WORD (E1h) register. The SMBA
pin is pulled low unless this feature is disabled using the ALERT_MASK (D8h) register.
See the Application and Implementation section for a procedure to calculate the threshold setting resistor values.
18
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Feature Description (continued)
8.3.6 Power Good Pin
The Power Good indicator pin (PGD) is connected to the drain of an internal N-channel MOSFET capable of
sustaining 80 V in the off-state, and transients up to 100 V. An external pullup resistor is required at PGD to an
appropriate voltage to indicate the status to downstream circuitry. The off-state voltage at the PGD pin can be
higher or lower than the voltages at VIN and OUT. PGD is switched high when the voltage at the FB pin exceeds
the PGD threshold voltage. Typically, the output voltage threshold is set with a resistor divider from output to
feedback, although the monitored voltage need not be the output voltage. Any other voltage can be monitored as
long as the voltage at the FB pin does not exceed its maximum rating. Referring to the Functional Block
Diagram, when the voltage at the FB pin is below its threshold, the 20-µA current source at FB is disabled. As
the output voltage increases, taking FB above its threshold, the current source is enabled, sourcing current out of
the pin, raising the voltage at FB to provide threshold hysteresis. The PGD output is forced low when either the
UVLO/EN pin is below its threshold or the OVLO pin is above its threshold. The status of the PGD pin can be
read through the PMBus interface in either the STATUS_WORD (79h) or DIAGNOSTIC_WORD (E1h) registers.
8.3.7 VDD Sub-Regulator
The LM5066 contains an internal linear sub-regulator, which steps down the input voltage to generate a 4.9-V rail
used for powering low voltage circuitry. The VDD sub-regulator should be used as the pullup supply for the CL,
RETRY, ADR2, ADR1, and ADR0 pins if they are to be tied high. It may also be used as the pullup supply for the
PGD and the SMBus signals (SDA, SCL, and SMBA). The VDD sub-regulator is not designed to drive high
currents and should not be loaded with other integrated circuits. The VDD pin is current limited to 30 mA in order
to protect the LM5066 in the event of a short. The sub-regulator requires a ceramic bypass capacitance having a
value of 1 µF or greater to be placed as close to the VDD pin as the PCB layout allows.
8.3.8 Remote Temperature Sensing
The LM5066 is designed to measure temperature remotely using an MMBT3904 NPN transistor. The base and
collector of the MMBT3904 should be connected to the DIODE pin and the emitter to the LM5066 ground. Place
the MMBT3904 near the device that requires temperature sensing. If the temperature of the hot swap pass
MOSFET, Q1, is to be measured, the MMBT3904 should be placed as close to Q1 as the layout allows. The
temperature is measured by means of a change in the diode voltage in response to a step in current supplied by
the DIODE pin. The DIODE pin sources a constant 9.4 µA, but pulses 250 µA once every millisecond to measure
the diode temperature. Take care in the PCB layout to keep the parasitic resistance between the DIODE pin and
the MMBT3904 low so as not to degrade the measurement. In addition it is recommended to make a Kelvin
connection from the emitter of the MMBT3904 to the GND of the part to ensure an accurate measurement.
Additionally, a small 1000-pF bypass capacitor should be placed in parallel with the MMBT3904 to reduce the
effects of noise. The temperature can be read using the READ_TEMPERATURE_1 PMBus command (8Dh). The
default limits of the LM5066 causes SMBA pin to be pulled low if the measured temperature exceeds 125°C and
disables Q1 if the temperature exceeds 150°C. These thresholds can be reprogrammed through the PMBus
interface using the OT_WARN_LIMIT (51h) and OT_FAULT_LIMIT (4Fh) commands. If the temperature
measurement and protection capability of the LM5066 are not used, the DIODE pin should be grounded.
Erroneous temperature measurements may result when the device input voltage is below the minimum operating
voltage (10 V), due to VREF dropping out below the nominal voltage (2.97 V). At higher ambient temperatures,
this measurement could read a value higher than the OT_FAULT_LIMIT, and trigger a fault, disabling Q1. In this
case, the faults should be removed and the device reset by writing a 0h, followed by an 80h to the OPERATION
(03h) register.
8.3.9 Damaged MOSFET Detection
The LM5066 is able to detect whether the external MOSFET, Q1, is damaged under certain conditions. If the
voltage across the sense resistor exceeds 4 mV while the GATE voltage is low or the internal logic indicates that
the GATE should be low, the EXT_MOSFET_SHORTED bit in the STATUS_MFR_SPECIFIC (80h) and
DIAGNOSTIC_WORD (E1h) registers are toggled high and the SMBA pin is asserted unless this feature is
disabled using the ALERT_MASK register (D8h). This method effectively determines whether Q1 is shorted
because of damage present between the drain and gate and/or drain and source.
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8.4 Device Functional Modes
8.4.1 Power-Up Sequence
The VIN operating range of the LM5066 is 10 to 80 V, with a transient capability to 100 V. Referring to the and
Figure 22, as the voltage at VIN initially increases, the external N-channel MOSFET (Q1) is held off by an internal
115-mA pulldown current at the GATE pin. The strong pulldown current at the GATE pin prevents an inadvertent
turn-on as the gate-to-drain (Miller) capacitance of the MOSFET is charged. Additionally, the TIMER pin is
initially held at ground. When the VIN voltage reaches the POR threshold the insertion time begins. During the
insertion time, the capacitor at the TIMER pin (CT) is charged by a 4.8-µA current source, and Q1 is held off by a
4.2-mA pulldown current at the GATE pin regardless of the input voltage. The insertion time delay allows ringing
and transients at VIN to settle before Q1 is enabled. The insertion time ends when the TIMER pin voltage reaches
3.9 V. CT is then quickly discharged by an internal 1.5-mA pulldown current. The GATE pin then switches on Q1
when VIN exceeds the UVLO threshold. If VIN is above the UVLO threshold at the end of the insertion time, Q1
the GATE pin charge pump sources 20 µA to charge the gate capacitance of Q1. The maximum voltage from the
gate to source of the Q1 is limited by an internal 16.5-V Zener diode.
As the voltage at the OUT pin increases, the LM5066 monitors the drain current and power dissipation of
MOSFET Q1. In-rush current limiting or power limiting circuits, or both, actively control the current delivered to the
load. During the in-rush limiting interval (t2 in Figure 22), an internal 75-µA fault timer current source charges CT.
If Q1’s power dissipation and the input current reduce below their respective limiting thresholds before the TIMER
pin reaches 3.9 V, the 75-µA current source is switched off, and CT is discharged by the internal 2.5-µA current
sink (t3 in Figure 22). The in-rush limiting no longer engages unless a current-limit condition occurs.
If the TIMER pin voltage reaches 3.9 V before in-rush current limiting or power limiting ceases during t2, a fault is
declared and Q1 is turned off. See the Fault Timer and Restart section for a complete description of the fault
mode.
The LM5066 asserts the SMBA pin after the input voltage has exceeded its POR threshold to indicate that the
volatile memory and device settings are in their default state. The CONFIG_PRESET bit within the
STATUS_MFR_SPECIFIC register (80h) indicates default configuration of warning thresholds and device
operation and remains high until a CLEAR_FAULTS command is received.
VIN
UVLO
VIN
POR
3.9 V
4.8 PA
75 PA
2.5 PA
TIMER
GATE
115 mA
pull-down
4.2 mA pull-down
20 PA source
ILIMIT
Load
Current
2.46V
FB
PGD
t1
Insertion Time
t2
In rush
Limiting
t3
Normal Operation
Figure 22. Power-Up Sequence (Current Limit Only)
20
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Device Functional Modes (continued)
8.4.2 Gate Control
A charge pump provides the voltage at the GATE pin to enhance the N-channel MOSFET’s gate (Q1). During
normal operating conditions (t3 in Figure 22), the gate of Q1 is held charged by an internal 20-µA current source.
The charge pump peak voltage is roughly 13.5 V, which forces a VGS across Q1 of 13.5 V under normal
operation. When the system voltage is initially applied, the GATE pin is held low by a 115-mA pulldown current.
This helps prevent an inadvertent turn-on of Q1 through its drain-gate capacitance as the applied system voltage
increases.
During the insertion time (t1 in Figure 22) the GATE pin is held low by a 4.2-mA pulldown current. This maintains
Q1 in the off-state until the end of t1, regardless of the voltage at VIN or UVLO. Following the insertion time,
during t2 in Figure 22 the gate voltage of Q1 is modulated to keep the current or power dissipation level from
exceeding the programmed levels. While in the current or power limiting mode, the TIMER pin capacitor is
charging. If the current and power limiting cease before the TIMER pin reaches 3.9 V, the TIMER pin capacitor
then discharges, and the circuit begins normal operation. If the in-rush limiting condition persists such that the
TIMER pin reached 3.9 V during t2, the GATE pin is then pulled low by the 4.2-mA pulldown current. The GATE
pin is then held low until either a power-up sequence is initiated (RETRY pin to VDD), or an automatic retry is
attempted (RETRY pin to GROUND or floating). See the Fault Timer and Restart section. If the system input
voltage falls below the UVLO threshold, or rises above the OVLO threshold, the GATE pin is pulled low by the
4.2-mA pulldown current to switch off Q1.
8.4.3 Fault Timer and Restart
When the current limit or power limit threshold is reached during turn-on, or as a result of a fault condition, the
gate-to-source voltage of Q1 is modulated to regulate the load current and power dissipation in Q1. When either
limiting function is active, a 75-µA fault timer current source charges the external capacitor (CT) at the TIMER pin
as shown in Figure 22 (fault timeout period). If the fault condition subsides during the fault timeout period before
the TIMER pin reaches 3.9 V, the LM5066 returns to the normal operating mode and CT is discharged by the 1.5mA current sink. If the TIMER pin reaches 3.9 V during the fault timeout period, Q1 is switched off by a 4.2-mA
pulldown current at the GATE pin. The subsequent restart procedure then depends on the selected retry
configuration.
If the RETRY pin is high, the LM5066 latches the GATE pin low at the end of the fault timeout period. CT is then
discharged to ground by the 2.5-µA fault current sink. The GATE pin is held low by the 4.2-mA pulldown current
until a power-up sequence is externally initiated by cycling the input voltage (VIN), or momentarily pulling the
UVLO/EN pin below its threshold with an open-collector or open-drain device as shown in Figure 23. The voltage
at the TIMER pin must be PLIM, so the hotswap starts in power limit and transitions
into current limit. In that case, the maximum start time can be computed as in Equation 14.
t start,max =
2
COUT é VIN,MAX PLIM ù 220mF é (60V)2 120W ù
´ê
+ 2 ú=
´ê
+
ú = 3.38ms
2
2
2
êë PLIM
ILIM úû
ëê 120W (13A) ûú
(14)
Note that the above start-time is based on typical current limit and power limit values. To ensure that the timer
never times out during start-up, TI recommends to set the fault time (tflt) to be 2 × tstart,max or 6.76 ms. This
accounts for the variation in power limit, timer current, and timer capacitance. Thus, CTIMER can be computed as
follows:
t flt u itimer 6.76 ms u 75 PA
CTIMER
130 nF
v timer
3.9 V
(15)
The next largest standards capacitor value for CTIMER is chosen as 150 nF. After CTIMER is chosen, the actual
programmed fault time can be computed as follows:
CTIMER u v timer 150 nF u 3.9 V
t flt
7.8 ms
itimer
75 PA
(16)
9.2.1.2.5 Check MOSFET SOA
When the power limit and fault timer are chosen, it is critical to check that the FET stays within its SOA during all
test conditions. During a hot-short the circuit breaker trips and the LM5066 restarts into power limit until the timer
runs out. In the worst case, the MOSFET’s VDS equals VIN,MAX, IDS equals PLIM / VIN,MAX and the stress event
lasts for tflt. For this design example, the MOSFET has 60 V, 2 A across it for 7.8 ms.
Based on the SOA of the PSMN4R8-100BSE, it can handle 60 V, 30 A for 1 ms and it can handle 60 V, 6 A for
10 ms. For 7.8 ms, the SOA can be extrapolated by approximating SOA versus time as a power function as
shown below:
a u tm
ISOA t
m
a
§ 30 A ·
ln ¨
¸
© 6A ¹
§ 1 ms ·
ln ¨
¸
© 10 ms ¹
ln ISOA t1 / ISOA t 2
ln t1 / t 2
ISOA t1
t1m
ISOA 7.8 ms
30 A
(1 ms)
0.7
0.7
30 A u (ms)0.7
30 A u (ms)0.7 u (7.8 ms)
0.7
7.12 A
(17)
Note that the SOA of a MOSFET is specified at a case temperature of 25°C, while the case temperature can be
much hotter during a hot-short. The SOA should be de-rated based on TC,MAX using Equation 18:
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ISOA 7.8 ms, TC,MAX
ISOA 7.8 ms, 25qC u
TJ,ABSMAX
TJ,ABSMAX
TC,MAX
25qC
7.12 A u
175qC 114qC
175qC 25qC
2.85 A
(18)
Based on this calculation, the MOSFET can handle 2.85 A, 60 V for 7.8 ms at elevated case temperature, but is
only required to handle 2 A during a hot-short. Thus, there is good margin and the design is robust. In general, TI
recommends that the MOSFET can handle 1.3× more than what is required during a hot-short. This provides
margin to account for the variance of the power limit and fault time.
9.2.1.2.6 Set UVLO and OVLO Thresholds
By programming the UVLO and OVLO thresholds, the LM5066 enables the series-pass device (Q1) when the
input supply voltage (VIN) is within the desired operational range. If VIN is below the UVLO threshold or above the
OVLO threshold, Q1 is switched off, denying power to the load. Hysteresis is provided for each threshold.
9.2.1.2.6.1 Option A
The configuration shown in Figure 30 requires three resistors (R1 to R3) to set the thresholds.
VIN
VIN
20 PA
R1
UVLO/EN 2.48 V
R2
2.46 V
TIMER AND
GATE
LOGIC CONTROL
OVLO
R3
GND
21 PA
Figure 30. UVLO And OVLO Thresholds Set By R1-R3
The procedure to calculate the resistor values is as follows:
• Choose the upper UVLO threshold (VUVH) and the lower UVLO threshold (VUVL).
• Choose the upper OVLO threshold (VOVH).
• The lower OVLO threshold (VOVL) cannot be chosen in advance in this case, but is determined after the
values for R1 to R3 are determined. If VOVL must be accurately defined in addition to the other three
thresholds, see Option B. The resistors are calculated as follows:
- VUVL VUV(HYS)
V
=
R1 = UVH
20mA
20mA
(19)
R3 =
R1´ VUVL ´ 2.46V
VOVH ´ (VUVL - 2.48V )
(20)
2.48V ´ R1
R2 =
- R3
VUVL - 2.48V
(21)
The lower OVLO threshold is calculated from:
é
æ æ 2.46V ö
öù
VOVL = ê(R1 + R2 )´ ç ç
- 21 mA ÷ ú + 2.46V
÷
è è R3 ø
ø ûú
ëê
(22)
When the R1 to R3 resistor values are known, the threshold voltages and hysteresis are calculated from the
following:
æ 2.48V
ö
VUVH = 2.48V + R1´ ç
+ 20 mA ÷
R2
R3
+
è
ø
(23)
VUVL =
2.48V ´ (R1 + R2 + R3 )
R2 + R3
(24)
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VUV(HYS) = R1´ 20 mA
VOVH =
VOVL
(25)
2.46V ´ (R1 + R2 + R3 )
R3
æ 2.46V
ö
=ç
- 21 mA ÷ ´ (R1 + R2 ) + 2.46V
è R3
ø
(26)
(27)
VOV(HYS) = (R1 + R2 )´ 21 mA
(28)
9.2.1.2.6.2 Option B
If all four thresholds must be accurately defined, the configuration in Figure 31 can be used.
VIN
VIN
20 PA
R1
UVLO/EN
2.48 V
R2
R3
OVLO
2.46 V
TIMER AND
GATE
LOGIC CONTROL
R4
GND
21 PA
Figure 31. Programming the Four Thresholds
The four resistor values are calculated as follows:
• Choose the upper and lower UVLO thresholds (VUVH) and (VUVL).
- VUVL VUV(HYS)
V
=
R1 = UVH
20 mA
20 mA
2.48V ´ R1
R2 =
VUVL - 2.48V
•
•
(30)
Choose the upper and lower OVLO threshold (VOVH) and (VOVL).
V
- VOVL
R3 = OVH
21 mA
R4 =
2.46V ´ R3
V
( OVH - 2.46V )
(31)
(32)
When the R1 to R4 resistor values are known, the threshold voltages and hysteresis are calculated from the
following:
é
æ 2.48V
öù
VUVH = 2.48V + êR1´ ç
+ 20 mA ÷ ú
è R2
øû
ë
(33)
VUVL =
2.48V ´ (R1 + R2 )
R2
VUV(HYS) = R1´ 20 mA
VOVH =
VOVL
48
(29)
(34)
(35)
2.46V ´ (R3 + R4 )
R4
é
æ 2.46V
öù
= 2.46V + êR3 ´ ç
- 21 mA ÷ ú
è R4
øû
ë
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(36)
(37)
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9.2.1.2.6.3 Option C
The minimum UVLO level is obtained by connecting the UVLO/EN pin to VIN as shown in Figure 32. Q1 is
switched on when the VIN voltage reaches the POREN threshold (≊8.6 V). The OVLO thresholds are set using
R3, R4. Their values are calculated using the procedure in Option B.
VIN
VIN
20 PA
10 k
UVLO/EN 2.48 V
R3
2.46 V
R4
TIMER AND
GATE
LOGIC CONTROL
OVLO
GND
21 PA
Figure 32. UVLO = POREN
9.2.1.2.6.4 Option D
The OVLO function can be disabled by grounding the OVLO pin. The UVLO thresholds are set as described in
Option B or Option C.
For this design example, option B was used and the following options were targeted: VUVH = 38 V, VUVL = 35 V,
VOVH = 65 V, and VOVL = 63 V. The VUVH and VOVL were chosen to be 5% below or above the input voltage range
of 40 to 60 V to allow for some tolerance in the thresholds of the part. R1, R2, R3, and R4 are computed using
the following equations:
- VUVL 38 V - 35 V
V
=
= 150kW
R1 = UVH
20µA
20µA
2.48 V ´ R1
2.48 V ´ 150kW
=
= 11.44kW
R2 =
V
2.48
V
( UVL
) (35V - 2.48 V )
VOVH - VOVL 65 V - 63 V
=
= 95.24kW
21µA
21µA
2.46 V ´ R3
2.46 V ´ 95.24kW
=
= 3.75kW
R4 =
(VOVH - 2.46 V ) (65V - 2.46 V )
R3 =
(38)
Nearest available 1% resistors should be chosen. Set R1 = 150 kΩ, R2 = 11.5 kΩ, R3 = 95.3 kΩ, and R4 = 3.74
kΩ.
9.2.1.2.7 Power Good Pin
The Power Good indicator pin (PGD) is connected to the drain of an internal N-channel MOSFET capable of
sustaining 80 V in the off-state and transients up to 100 V. An external pullup resistor is required at PGD to an
appropriate voltage to indicate the status to downstream circuitry. The off-state voltage at the PGD pin can be
higher or lower than the voltages at VIN and OUT. PGD is switched high when the voltage at the FB pin exceeds
the PGD threshold voltage. Typically, the output voltage threshold is set with a resistor divider from output to
feedback, although the monitored voltage need not be the output voltage. Any other voltage can be monitored as
long as the voltage at the FB pin does not exceed its maximum rating. Referring to the Functional Block
Diagram, when the voltage at the FB pin is below its threshold, the 20-µA current source at FB is disabled. As
the output voltage increases, taking FB above its threshold, the current source is enabled, sourcing current out of
the pin, raising the voltage at FB to provide threshold hysteresis. The PGD output is forced low when either the
UVLO/EN pin is below its threshold or the OVLO pin is above its threshold. The status of the PGD pin can be
read through the PMBus interface in either the STATUS_WORD (79h) or DIAGNOSTIC_WORD (E1h) registers.
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When the voltage at the FB pin increases above its threshold, the internal pulldown acting on the PGD pin is
disabled allowing PGD to rise to VPGD through the pullup resistor, RPG, as shown in Figure 34. The pullup voltage
(VPGD) can be as high as 80 V, and can be higher or lower than the voltages at VIN and OUT. VDD is a
convenient choice for VPGD as it allows interface to low voltage logic and avoids glitching on PGD during powerup. If a delay is required at PGD, suggested circuits are shown in Figure 35. In Figure 35(A), capacitor CPG adds
delay to the rising edge, but not to the falling edge. In Figure 35(B), the rising edge is delayed by RPG1 + RPG2
and CPG, while the falling edge is delayed a lesser amount by RPG2 and CPG. Adding a diode across RPG2
(Figure 35(C)) allows for equal delays at the two edges, or a short delay at the rising edge and a long delay at
the falling edge.
Q1
VPGD
VOUT
OUT
GATE
RPG
R5
2.46 V
PGD
FB
Power Good
R6
GND
20 PA
PGD
UV
OV
GND
Figure 33. Programming the PGD Threshold
VPGD
Figure 34. Power Good Output
VPGD
VPGD
RPG1
RPG1
RPG1
PGD
PGD
Power
Good
RPG2
RPG2
CPG
CPG
GND
GND
A) Delay at Rising Edge Only
PGD
Power
Good
B) Long Delay at Rising Edge,
Short Delay at Falling Edge
Power
Good
CPG
GND
C) Short Delay at Rising Edge and
Long Delay at Falling Edge or
Equal Delays
Figure 35. Adding Delay to the Power Good Output Pin
TI recommends to set the PG threshold 5% below the minimum input voltage to ensure that the PG is asserted
under all input voltage conditions. For this example, PGDH of 38 V and PGDL of 35 V is targeted. R5 and R6 are
computed using the following equations:
V
- VPGDL 38 V - 35 V
R5 = PGDH
=
= 150kW
20µA
20µA
(39)
R6 =
2.46 V ´ R5
2.46 V ´ 150kW
=
= 10.38kW
(VPGDH - 2.46 V ) (38V - 2.46 V )
(40)
Nearest available 1% resistors should be chosen. Set R5 = 150 kΩ and R6 = 10.5 kΩ.
9.2.1.2.8 Input and Output Protection
Proper operation of the LM5066 hot swap circuit requires a voltage clamping element present on the supply side
of the connector into which the hot swap circuit is plugged in. A TVS is ideal, as depicted in . The TVS is
necessary to absorb the voltage transient generated whenever the hot swap circuit shuts off the load current.
This effect is the most severe during a hot-short when a large current is suddenly interrupted when the FET
shutts off. The TVS should be chosen to have minimal leakage current at VIN,MAX and to clamp the voltage to
under 100V during hot-short events. For many high power applications 5.0SMDJ60A is a good choice.
50
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If the load powered by the LM5066 hot swap circuit has inductive characteristics, a Schottky diode is required
across the LM5066’s output, along with some load capacitance. The capacitance and the diode are necessary to
limit the negative excursion at the OUT pin when the load current is shut off.
RSNS
VIN
Q1
+48 V
LIVE
POWER
SOURCE
VIN VIN_K
SENSE
VOUT
OUT
D1
CL
Inductive
Load
LM5066
Z1
AGND GND
GND
PLUG-IN BOARD
Figure 36. Output Diode Required for Inductive Loads
9.2.1.2.9 Final Schematic and Component Values
Figure 28 shows the schematic used to implement the requirements described in the previous section. In
addition, Table 47 provides the final component values that were used to meet the design requirements for a 48V, 10-A hotswap design. The application curves in the next section are based on these component values.
Table 47. Final Component Values (48-V, 10-A Design)
COMPONENT
VALUE
RSNS
2 mΩ
R1
150 kΩ
R2
11.5 kΩ
R3
95.3 kΩ
R4
3.74 kΩ
R5
150 kΩ
R6
10.5 kΩ
RPWR
21 kΩ
Q1
PSMN4R8-100BSEJ
Q2
MMBT3904
D1
B380-13-F
Z1
5.0SMDJ60A
CTIMER
150 nF
Optional dv/dt circuit
DNP
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9.2.1.3 Application Curves
VIN = 48V
Figure 37. Insertion Delay
Figure 38. Start-Up
VIN = 40V
52
VIN = 60V
Figure 39. Start-Up
Figure 40. Start-Up
Figure 41. Start-Up into Short Circuit
Figure 42. Under-Voltage
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Figure 43. Over-Voltage
Figure 44. Gradual Over-Current
Figure 45. Loadstep
Figure 46. Hotshort on Output (Zoomed Out)
Figure 47. Hotshort on Output (Zoomed In)
Figure 48. Auto-retry
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10 Power Supply Recommendations
In general, the LM5066 behavior is more reliable if it is supplied from a very regulated power supply. However,
high-frequency transients on a backplane are not uncommon due to adjacent card insertions or faults. If this is
expected in the end system, TI recommends to place a 1-µF ceramic capacitor to ground close to the source of
the hotswap MOSFET. This reduces the common mode seen by VIN_K and SENSE. Additional filtering may be
necessary to avoid nuisance trips.
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11 Layout
11.1 Layout Guidelines
The following guidelines should be followed when designing the PC board for the LM5066:
1. Place the LM5066 close to the board’s input connector to minimize trace inductance from the connector to
the MOSFET.
2. Place a TVS, Z1, directly adjacent to the VIN and GND pins of the LM5066 to help minimize voltage
transients which may occur on the input supply line. The TVS should be chosen such that the peak VIN is just
lower the TVS reverse-bias voltage. Transients of 20 V or greater over the nominal input voltage can easily
occur when the load current is shut off. A small capacitor may be sufficient for low current sense applications
(I < 2 A). TI recommends to test the VIN input voltage transient performance of the circuit by current limiting
or shorting the load and measuring the peak input voltage transient.
3. Place a 1-µF ceramic capacitor as close as possible to VREF pin.
4. Place a 1-µF ceramic capacitor as close as possible to VDD pin.
5. The sense resistor (RSNS) should be placed close to the LM5066. A trace should connect the VIN pad and Q1
pad of the sense resistor to VIN_K and SENSE pins, respectively. Connect RSNS using the Kelvin techniques
as shown in Figure 50.
6. The high current path from the board’s input to the load (through Q1), and the return path, should be parallel
and close to each other to minimize loop inductance.
7. The AGND and GND connections should be connected at the pins of the device. The ground connections for
the various components around the LM5066 should be connected directly to each other, and to the
LM5066’s GND and AGND pin connection, and then connected to the system ground at one point. Do not
connect the various component grounds to each other through the high current ground line.
8. Provide adequate thermal sinking for the series pass device (Q1) to help reduce stresses during turn-on and
turn-off.
9. The board’s edge connector can be designed such that the LM5066 detects through the UVLO/EN pin that
the board is being removed, and responds by turning off the load before the supply voltage is disconnected.
For example, in , the voltage at the UVLO/EN pin goes to ground before VIN is removed from the LM5066 as
a result of the shorter edge connector pin. When the board is inserted into the edge connector, the system
voltage is applied to the LM5066’s VIN pin before the UVLO voltage is taken high, thereby allowing the
LM5066 to turn on the output in a controlled fashion.
11.2 Layout Example
GND
VIN
To
Load
RS
Q1
Z1/C1
R1
R2
R3
OUT
GATE
SENSE
VIN_K
VIN
UVLO/EN
OVLO
AGND
GND
SDAI
SDAO
SCL
SMBA
PGD
PWR
TIMER
RETRY
FB
CL
VDD
ADR0
ADR1
ADR2
VAUX
DIODE
VREF
LM5066
CARD EDGE
CONNECTOR
MMBT3904
PLUG-IN CARD
Figure 49. Recommended Board Connector Design
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Layout Example (continued)
HIGH CURRENT PATH
FROM SYSTEM
INPUT VOLTAGE
TO DRAIN OF
SENSE
RESISTOR
MOSFET Q1
RS
VIN
VIN_K
SENSE
Figure 50. Sense Resistor Connections
56
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12 Device and Documentation Support
12.1 Trademarks
PMBus is a trademark of SMIF, Inc.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: LM5066
57
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
LM5066PMH/NOPB
ACTIVE
HTSSOP
PWP
28
48
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 125
LM5066PMH
LM5066PMHE/NOPB
ACTIVE
HTSSOP
PWP
28
250
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 125
LM5066PMH
LM5066PMHX/NOPB
ACTIVE
HTSSOP
PWP
28
2500
RoHS & Green
SN
Level-3-260C-168 HR
-40 to 125
LM5066PMH
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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