LM5157-Q1, LM51571-Q1
SNVSBK8A – OCTOBER 2020 – REVISED MARCH 2021
LM5157x-Q1 2.2-MHz Wide VIN 50-V Boost/SEPIC/Flyback Converter with Dual
Random Spread Spectrum
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
Battery-powered wide input boost, SEPIC, flyback
converter
Automotive voltage stabilizer in SEPIC
Automotive start-stop application
Automotive emergency call application/backup
battery booster
High voltage LiDAR power supply
Automotive LED bias supply
Multiple-output flyback without optocoupler
Holdup capacitor charger
Audio amplifier power supply
Piezo driver/motor driver bias supply
•
•
•
•
•
•
•
•
•
3 Description
The LM5157x-Q1 device is a wide input range, nonsynchronous boost converter with integrated 50-V,
6.5-A (LM5157-Q1) or 50-V, 4.33-A (LM51571-Q1)
power switch.
The device can be used in boost, SEPIC, and flyback
topologies. The device can start up from a single-cell
battery with a minimum of 2.9 V. It can operate with
the input supply voltage as low as 1.5 V if the BIAS
pin is greater than 2.9 V.
Device Information
PART NUMBER
LM5157-Q1
LM51571-Q1
(1)
PACKAGE(1)
BODY SIZE (NOM)
WQFN (16)
3.00 mm × 3.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
VLOAD
VSUPP LY
BIAS VCC
UVLO
SW
Option al
•
AEC-Q100 qualified for automotive applications
– Temperature grade 1: –40°C to +125°C TA
Functional Safety-Capable
– Documentation available to aid functional safety
system design
Suited for wide operating range for car battery
applications
– 2.9-V to 45-V input operating range
– 48-V maximum output (50-V abs max)
– Minimum boost supply voltage of 1.5 V when
BIAS ≥ 2.9 V
– Input transient protection up to 50 V
– Minimized battery drain
• Low shutdown current (IQ ≤ 2.6 µA)
• Low operating current (IQ ≤ 700 µA)
Small solution size and low cost
– Maximum switching frequency up to 2.2 MHz
– 16-pin QFN package (3 mm × 3 mm) with
wettable flanks
– Integrated error amplifier allows primary-side
regulation without optocoupler (flyback)
– Minimized undershoot during cranking (startstop application)
– Accurate current limit (see the Device
Comparison Table)
EMI mitigation
– Selectable dual random spread spectrum
– Lead-less package
Higher efficiency with low-power dissipation
– 45-mΩ RDSON switch
– Fast switching, small switching loss
Avoid AM band interference and crosstalk
– Optional clock synchronization
– Dynamically programmable wide switching
frequency from 100 kHz to 2.2 MHz
Integrated protection features
– Constant current limiting over input voltage
– Selectable hiccup mode overload protection
– Programmable line UVLO
– OVP protection
– Thermal shutdown
Accurate ±1% accuracy feedback reference
Adjustable soft start
PGOOD indicator
Create a custom design using the LM5157x-Q1
with the WEBENCH® Power Designer
FB
RT
COMP
SS
PGO OD
PGND AGND MODE
Typical SEPIC Application
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
LM5157-Q1, LM51571-Q1
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 3
6 Device Comparison Table...............................................4
7 Pin Configuration and Functions...................................5
8 Specifications.................................................................. 7
8.1 Absolute Maximum Ratings ....................................... 7
8.2 ESD Ratings .............................................................. 7
8.3 Recommended Operating Conditions ........................8
8.4 Thermal Information ...................................................8
8.5 Electrical Characteristics ............................................8
8.6 Typical Characteristics.............................................. 11
9 Detailed Description......................................................14
9.1 Overview................................................................... 14
9.2 Functional Block Diagram......................................... 15
9.3 Feature Description...................................................15
9.4 Device Functional Modes..........................................27
10 Application and Implementation................................ 28
10.1 Application Information........................................... 28
10.2 Typical Application.................................................. 28
10.3 System Examples................................................... 31
11 Power Supply Recommendations..............................35
12 Layout...........................................................................36
12.1 Layout Guidelines................................................... 36
12.2 Layout Examples.................................................... 37
13 Device and Documentation Support..........................38
13.1 Device Support....................................................... 38
13.2 Documentation Support.......................................... 38
13.3 Receiving Notification of Documentation Updates..38
13.4 Support Resources................................................. 39
13.5 Trademarks............................................................. 39
13.6 Electrostatic Discharge Caution..............................39
13.7 Glossary..................................................................39
14 Mechanical, Packaging, and Orderable
Information.................................................................... 40
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (October 2020) to Revision A (March 2021)
Page
• Changed the LM51571-Q1 device status from Advance Information to Production Data.................................. 1
2
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5 Description (continued)
The BIAS pin operates up to 45 V (50-V absolute maximum) for automotive load dump. The switching frequency
is dynamically programmable with an external resistor from 100 kHz to 2.2 MHz. Switching at 2.2 MHz minimizes
AM band interference and allows for a small solution size and fast transient response. To reduce the EMI of the
power supply, the device provides a selectable Dual Random Spread Spectrum, which reduces the EMI over a
wide frequency range.
The device features an accurate peak current limit over the input voltage, which avoids overdesigning the power
inductor. Low operating current and pulse-skipping operation improve efficiency at light loads.
The device has built-in protection features such as overvoltage protection, line UVLO, thermal shutdown, and
selectable hiccup mode overload protection. Additional features include low shutdown IQ, programmable soft
start, precision reference, power-good indicator, and external clock synchronization.
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6 Device Comparison Table
4
DEVICE OPTION
MINIMUM PEAK CURRENT LIMIT
LM5157-Q1
6.5 A
LM51571-Q1
4.33 A
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MAXIMUM SW VOLTAGE
48 V (50-V abs max)
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PGND
1
VCC
2
PGND
NC
SW
SW
7 Pin Configuration and Functions
16
15
14
13
12 SW
11 MODE
EP
9
5
6
7
8
COMP
4
AGND
PGOOD
10 SS
EN/UVLO/SYNC
3
RT
BIAS
FB
Figure 7-1. 16-Pin WQFN With Wettable Flanks RTE Package (Top View)
Table 7-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NO.
NAME
1, 16
PGND
P
Power ground pin. Source connection of the internal N-channel power MOSFET
2
VCC
P
Output of the internal VCC regulator and supply voltage input of the internal MOSFET driver.
Connect a 5-Ω resistor in series with a 1-µF ceramic bypass capacitor from this pin to PGND.
3
BIAS
P
Supply voltage input to the VCC regulator. Connect a bypass capacitor from this pin to PGND.
4
PGOOD
O
Power-good indicator. An open-drain output that goes low if FB is below the undervoltage threshold
(VUVTH). Connect a pullup resistor to the system voltage rail.
5
RT
I
Switching frequency setting pin. The switching frequency is programmed by a single resistor
between RT and AGND.
Enable pin. The converter shuts down when the pin is less than the enable threshold (VEN).
6
UVLO/
SYNC/EN
I
Undervoltage lockout programming pin. The converter start-up and shutdown levels can be
programmed by connecting this pin to the supply voltage through a voltage divider. If a
programmable UVLO is used, connect the low-side UVLO resistor to AGND. This pin must not be left
floating. Connect to the BIAS pin if not used.
External synchronization clock input pin. The internal clock can be synchronized to an external clock
by applying a negative pulse signal into the pin.
7
AGND
G
Analog ground pin. Connect to the analog ground plane through a wide and short path.
8
COMP
O
Output of the internal transconductance error amplifier. Connect the loop compensation components
between this pin and AGND.
9
FB
I
Inverting input of the error amplifier. Connect a voltage divider to set output voltage in boost, SEPIC,
or primary-side regulated flyback topologies. Connect the low-side feedback resistor close to AGND.
10
SS
I
Soft-start time programming pin. An external capacitor and an internal current source set the ramp
rate of the internal error amplifier reference during soft start. Connect the ground connection of the
capacitor to AGND.
MODE = 0 V or connect to AGND during initial power up. Hiccup mode protection is disabled and
spread spectrum is disabled.
11
MODE
I
MODE = 370 mV or connect a 37.4-kΩ resistor between this pin and AGND during initial power up.
Hiccup mode protection is enabled and spread spectrum is enabled.
MODE = 620 mV or connect a 62.0-kΩ resistor between this pin and AGND during initial power up.
Hiccup mode protection is enabled and spread spectrum is disabled.
MODE > 1 V or connect a 100-kΩ resistor between this pin and AGND during initial power up.
Hiccup mode protection is disabled and spread spectrum is enabled.
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Table 7-1. Pin Functions (continued)
PIN
NO.
TYPE(1)
DESCRIPTION
12, 13,
14
SW
15
NC
—
No internal electrical contact. Optionally connect to PGND for improved thermal conductivity.
—
EP
—
Exposed pad of the package. The exposed pad must be connected to AGND and the large ground
copper plane to decrease thermal resistance.
(1)
6
NAME
Switch pin. Drain connection of the internal N-channel power MOSFET
G = Ground, I = Input, O = Output, P = Power
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8 Specifications
8.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range(1)
MIN
Input
Output
MAX
BIAS to AGND
–0.3
50
UVLO to AGND
–0.3
VBIAS + 0.3
SS, RT to AGND(2)
–0.3
3.8
FB to AGND
–0.3
4.0
MODE to AGND
–0.3
3.8
PGND to AGND
–0.3
0.3
VCC to AGND
–0.3
5.8(3)
PGOOD to AGND(4)
–0.3
18
AGND(5)
–0.3
SW to AGND (DC)
–0.3
SW to AGND (6 ns transient)
–4.0
COMP to
V
–40
150
Storage temperature, Tstg
–55
150
(2)
(3)
(4)
(5)
(6)
V
50
Junction temperature, TJ (6)
(1)
UNIT
°C
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
This pin is not specified to have an external voltage applied.
Operating lifetime is de-rated when the pin voltage is greater than 5.5 V.
The maximum current sink is limited to 1 mA when VPGOOD > VBIAS.
This pin has an internal max voltage clamp which can handle up to 1.6 mA.
High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
8.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic
discharge
Human-body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 2
Charged-device model (CDM), per AEC Q100-011
CDM ESD Classification Level C4B
UNIT
±2000
All pins
±500
Corner pins
±750
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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8.3 Recommended Operating Conditions
Over the recommended operating junction temperature range(1)
MIN
VSUPPLY
Boost converter input (when BIAS ≥ 2.9 V)
NOM
MAX
UNIT
1.5
45
V
VSUPPLY
48(2)
V
2.9
45
V
VLOAD
Boost converter output
VBIAS
BIAS input(3)
VUVLO
UVLO input
0
45
V
VFB
FB input
0
4.0
V
0
note(4)
ISW
Switch current
fSW
Typical switching frequency
100
2200
kHz
fSYNC
Synchronization pulse frequency
100
2200
kHz
TJ
Operating junction temperature(5)
–40
150
°C
(1)
(2)
(3)
(4)
(5)
See
A
Recommended Operating Conditions are conditions under the device is intended to be functional. For specifications and test
conditions, see the Electrical Characteristics.
Boost converter output can be up to 48 V, but the SW pin voltage should be less than or equal to 50 V during transient.
BIAS pin operating range is from 2.9 V to 45 V when VCC is supplied from the internal VCC regulator. When the VCC pin is directly
connected to the BIAS pin, the device requires minimum 2.85 V at the BIAS pin to start up, and the BIAS pin operating range is from
2.75 V to 5.5 V after starting up.
Maximum switch currrent is limited by pre-programmed peak current limit (ILIM) , and is ensured when TJ < TTSD
High junction temperatures degrade operating lifetimes. Operating lifetime is de-rated for junction temperatures greater than 125°C.
8.4 Thermal Information
LM5157x-Q1
THERMAL
METRIC(1)
RTE(QFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance (LM5157EVM-BST)
32.7
°C/W
RθJA
Junction-to-ambient thermal resistance
45.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
45.3
°C/W
RθJB
Junction-to-board thermal resistance
20.0
°C/W
ΨJT
Junction-to-top characterization parameter (LM5157EVM-BST)
0.6
°C/W
ΨJT
Junction-to-top characterization parameter
0.8
°C/W
ΨJB
Junction-to-board characterization parameter (LM5157EVM-BST)
14.8
°C/W
ΨJB
Junction-to-board characterization parameter
20.0
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
6.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8.5 Electrical Characteristics
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over TJ = –40°C to 150°C. Unless otherwise
stated, VBIAS = 12 V, RT = 9.09 kΩ
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
ISHUTDOWN(BIAS) BIAS shutdown current
VBIAS = 12 V, VUVLO = 0 V
2.6
5
μA
IOPERATING(BIAS) BIAS operating current
VBIAS = 12 V, VUVLO = 2.0 V, VFB = VREF,
RT = 220 kΩ
700
775
μA
VCC REGULATOR
VVCC-REG
VCC regulation
VBIAS = 8 V, IVCC = 18 mA
4.66
4.9
5.14
V
VVCC-
VCC UVLO threshold
VCC rising
2.75
2.8
2.85
V
VCC UVLO hysteresis
VCC falling
UVLO(RISING)
8
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V
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8.5 Electrical Characteristics (continued)
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over TJ = –40°C to 150°C. Unless otherwise
stated, VBIAS = 12 V, RT = 9.09 kΩ
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ENABLE
VEN(RISING)
Enable threshold
EN rising
0.4
0.52
0.7
V
VEN(FALLING)
Enable threshold
EN falling
0.33
0.49
0.63
V
VEN(HYS)
Enable hysteresis
EN falling
VUVLO(RISING)
UVLO/SYNC threshold
UVLO rising
1.425
1.5
1.575
V
VUVLO(FALLING)
UVLO/SYNC threshold
UVLO falling
1.370
1.45
1.520
V
VUVLO(HYS)
UVLO/SYNC threshold hysteresis
UVLO falling
IUVLO
UVLO hysteresis current
VUVLO = 1.6 V
0.03
V
UVLO/SYNC
0.05
4
5
V
6
μA
11
μA
MODE, SPREAD SPECTRUM
FSW modulation (upper limit)
7.8%
FSW modulation (lower limit)
–7.8%
SS
ISS
Soft-start current
9
SS pulldown switch RDSON
10
50
Ω
PULSE WIDTH MODULATION
fsw1
Switching frequency
RT = 220 kΩ
85
100
115
kHz
fsw2
Switching frequency
RT = 49.3 kΩ
388
440
492
kHz
fsw3
Switching frequency
RT = 9.09 kΩ
1980
2200
2420
kHz
tON(MIN)
Minimum on time
RT = 9.09 kΩ
DMAX1
Maximum duty cycle limit
RT = 9.09 kΩ
80%
85%
90%
DMAX2
Maximum duty cycle limit
RT = 220 kΩ
90%
93%
96%
80
RT regulation voltage
ns
0.5
V
CURRENT LIMIT
ILIM
Internal MOSFET current limit
LM5157
6.5
7.5
8.5
A
Internal MOSFET current limit
LM51571
4.33
5
5.67
A
HICCUP MODE PROTECTION
Hiccup enable cycles
Hiccup timer reset cycles
64
Cycles
8
Cycles
ERROR AMPLIFIER
VREF
FB reference
Gm
Transconductance
ACS
0.99
1
1.01
2
COMP sourcing current
VCOMP = 1.2 V
180
COMP clamp voltage
COMP rising (VUVLO = 2.0 V)
2.5
COMP clamp voltage
COMP falling
μA
2.8
1
ΔVCOMP/ΔISW
V
mA/V
V
1.1
V
0.095
OVP
VOVTH
Overvoltage threshold
FB rising (referece to VREF)
Overvoltage threshold
FB falling (referece to VREF)
PGOOD pulldown switch RDSON
1-mA sinking
Undervoltage threshold
FB falling (referece to VREF)
Undervoltage threshold
FB rising (referece to VREF)
107%
110%
113%
105%
PGOOD
VUVTH
70
87%
90%
Ω
93%
95%
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8.5 Electrical Characteristics (continued)
Typical values correspond to TJ = 25°C. Minimum and maximum limits apply over TJ = –40°C to 150°C. Unless otherwise
stated, VBIAS = 12 V, RT = 9.09 kΩ
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VBIAS = 12 V
45
90
mΩ
VBIAS = 3.5 V
47
95
mΩ
1200
nA
POWER SWITCH
rDS(ON)
Internal MOSFET on-resistance
Leakage current
VSW = 12 V
THERMAL SHUTDOWN
TTSD
Thermal shutdown threshold
Temperature rising
Thermal shutdown hysteresis
10
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175
°C
15
°C
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8.6 Typical Characteristics
Figure 8-1. BIAS Shutdown Current vs VBIAS
Figure 8-3. BIAS Operating Current vs Temperature
Figure 8-5. VVCC vs IVCC
Figure 8-2. BIAS Shutdown Current vs
Temperature
Figure 8-4. VVCC vs VBIAS
Figure 8-6. ISS vs Temperature
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12
Figure 8-7. EN Threshold vs Temperature
Figure 8-8. UVLO Threshold vs Temperature
Figure 8-9. FB Reference vs Temperature
Figure 8-10. Frequency vs RT Resistance
Figure 8-11. Frequency vs Temperature
Figure 8-12. Current Limit Threshold vs
Temperature
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Figure 8-13. Peak Current Limit vs Duty Cycle
Figure 8-14. Internal MOSFET Drain Source Onstate Resistance vs Temperature
Figure 8-15. Minimum On Time vs Frequency
Figure 8-16. Maximum Duty Cycle Limit vs
Frequency
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9 Detailed Description
9.1 Overview
The LM5157x-Q1 device is a wide input range, non-synchronous boost converter that uses peak-current-mode
control. The device can be used in boost, SEPIC, and flyback topologies.
The device can start up from a single-cell battery with a minimum of 2.9 V. It can operate with input supply
voltage as low as 1.5 V if the BIAS pin is greater than 2.9 V. The internal VCC regulator also supports BIAS
pin operation up to 45 V (50-V absolute maximum) for automotive load dump. The switching frequency is
dynamically programmable with an external resistor from 100 kHz to 2.2 MHz. Switching at 2.2 MHz minimizes
AM band interference and allows for a small solution size and fast transient response. To reduce the EMI of the
power supply, the device provides an optional dual random spread spectrum, which reduces the EMI over a wide
frequency span.
The device features an accurate current limit over the input voltage range. Low operating current and pulse
skipping operation improve efficiency at light loads.
The device also has built-in protection features such as overvoltage protection, line UVLO, and thermal
shutdown. Selectable hiccup mode overload protection protects the converter during prolonged current limit
conditions. Additional features include the following:
•
•
•
•
•
14
Low shutdown IQ
Programmable soft start
Precision reference
Power good indicator
External clock synchronization
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9.2 Functional Block Diagram
VSUPP LY
D1
LM
VLOAD
CIN
COUT
R FBT
RLOAD
FB
VUVTH
IUVL O
RUVL OT
±
TSD
Ready
+
EN
/UVLO
/SYNC
Clock_ Syn c
VCC
VCC
Regula tor
SS
VCC_EN
Hiccup
Mode
C/L Comparator
ICS
+
ISS
FB
±
VCC_EN
ILIM
VREF
AGND
OVP
VOVTH
+
VEN
RFBB
BIAS
SYNC
Detector
±
SW
FB
+
VUVL O
CSS
BIAS
±
VCC_OK
VSUPP LY
RUVL OB
PGO OD
+
RVCC
VCC
UVLO
VCC_OK
CVCC
±
S
Q
PWM
1.1V+VSLOPE Comparator
+
VCS +
R
Q
+
+
±
±
Gm
Clock_ Syn c
COMP
ICS
Gai n
= A CS
MODE
Sele ction
Clock Gen erator
Spr ead Spectrum
AGND
RT
MODE
VCS
PGND
RT
RCOMP
CCOMP
9.3 Feature Description
9.3.1 Line Undervoltage Lockout (UVLO/SYNC/EN Pin)
The device has a dual-level EN/UVLO circuit. During power on, if the BIAS pin voltage is greater than 2.7 V
and the UVLO pin voltage is between the enable threshold (VEN) and the UVLO threshold (VUVLO) for more
than 1.5 µs (see Section 9.3.6 for more details), the device starts up and an internal configuration starts. The
device typically requires a 90-µs internal start-up delay before entering standby mode. In standby mode, the
VCC regulator and RT regulator are operational, the SS pin is grounded, and there is no switching at the SW pin.
IUVLO
VSUPPLY
VUVLO
RUVLOT
RUVLOB
±
RUN
+
EN
/UVLO
/SYNC
+
VCC_EN
VEN
±
Figure 9-1. Line UVLO and Enable
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When the UVLO pin voltage is above the UVLO threshold, the device enters run mode. In run mode, a
soft-start sequence starts if the VCC voltage is greater than VCC UV threshold (VVCC-UVLO). UVLO hysteresis is
accomplished with an internal 50-mV voltage hysteresis and an additional 5-μA current source that is switched
on or off. When the UVLO pin voltage exceeds the UVLO threshold, the UVLO hysteresis current source
is enabled to quickly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the UVLO
threshold, the current source is disabled, causing the voltage at the UVLO pin to fall quickly. When the UVLO pin
voltage is less than the enable threshold (VEN), the device enters shutdown mode after a 40-µs (typical) delay
with all functions disabled.
> 3 cycles
90-µs (typical)
internal start-up delay
BIAS
= VSUPPLY
2.7 V
VUVLO
VEN
UVLO
VVCC-UVLO
Shutdown
VCC
SS
VREF
1.5 µs
SS is grounded
with 2 cycles
delay
UVLO should be greater than
VEN more than 1.5 µs to start-up
SW
TSS
SS VLOAD
=
1V
VLOAD(TARGET)
VLOAD
Figure 9-2. Boost Start-Up Waveforms Case 1: Start-Up by VCC UVLO, UVLO Toggle After Start-Up
16
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> 40us(typical)
90-µs (typical)
internal start-up delay
BIAS
= VSUPPLY
90us (typical)
internal start-up delay
2.7 V
VUVLO
VEN
UVLO
VVCC-UVLO
Shutdown
VREF
VCC
1.5 µs
SS is grounded
with 2 cycles
delay
UVLO should be greater than
0.55 V more than 1.5 µs to start-up
SS
SW
TSS
SS VLOAD
=
1V
VLOAD(TARGET)
VLOAD
Figure 9-3. Boost Start-Up Waveforms Case 2: Start-Up by VCC UVLO, EN Toggle After Start-Up
The external UVLO resistor divider must be designed so that the voltage at the UVLO pin is greater than 1.5
V (typical) when the input voltage is in the desired operating range. The values of RUVLOT and RUVLOB can be
calculated as shown in Equation 1 and Equation 2.
VSUPPLY(ON) u
RUVLOT
VUVLO(FALLING)
VUVLO(RISING)
VSUPPLY(OFF)
IUVLO
(1)
where
•
•
VSUPPLY(ON) is the desired start-up voltage of the converter
VSUPPLY(OFF) is the desired turn-off voltage of the converter
RUVLOB
VUVLO(RISING) u RUVLOT
VSUPPLY(ON)
VUVLO(RISING)
(2)
A UVLO capacitor (C UVLO) is required in case the input voltage drops below the VSUPPLY(OFF) momentarily during
start-up or during a severe load transient at the low input voltage. If the required UVLO capacitor is large, an
additional series UVLO resistor (RUVLOS) can be used to quickly raise the voltage at the UVLO pin when the
5-μA hysteresis current turns on.
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IUVLO
VSUPPLY
VUVLO
RUVLOT
RUVLOS
±
RUN
+
RUVLOB
CUVLO
EN/UVLO/SYNC
Figure 9-4. Line UVLO using Three UVLO Resistors
Do not leave the UVLO pin floating. Connect to the BIAS pin if not used.
9.3.2 High Voltage VCC Regulator (BIAS, VCC Pin)
The device has an internal wide input VCC regulator that is sourced from the BIAS pin. The wide input VCC
regulator allows the BIAS pin to be connected directly to supply voltages from 2.9 V to 45 V (transient protection
up to 50 V).
The VCC regulator turns on when the device is in standby or run mode. When the BIAS pin voltage is below the
VCC regulation target, the VCC output tracks the BIAS with a small dropout voltage. When the BIAS pin voltage
is greater than the VCC regulation target, the VCC regulator provides a 5-V supply (typical) for the device and
the internal N-channel MOSFET driver.
The VCC regulator sources current into the capacitor connected to the VCC pin. Connect a 5-Ω resistor in series
with a 1-µF ceramic bypass capacitor from this pin to PGND.
The minimum supply voltage after start-up can be further decreased by supplying the BIAS pin from the boost
converter output or from an external power supply as shown in Figure 9-5. Also, this configuration allows the
device to handle more power when VSUPPLY is less than 5 V. Practical minimum supply voltage after start-up is
decided by the maximum duty cycle limit (DMAX).
VLOAD
VSUPP LY
BIAS VCC
UVLO
SW
Option al
VLOAD
FB
RT
COMP
SS
PGO OD
PGND AGND MODE
Figure 9-5. Decrease the Minimum Operating Voltage After Start-Up
In flyback topology, the internal power dissipation of the device can be decreased by supplying the BIAS using
an additional transformer winding, especially in PSR flyback. In this configuration, the external BIAS supply
voltage (VAUX) must be greater than the regulation target of the external LDO, and the BIAS pin voltage must
always be greater than 2.9 V.
18
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VLOAD =1 2V
Option al
VSUPP LY
VAUX =1 2V
0.7V
FSYNC
Figure 9-13. UVLO, Standby, and Clock Synchronization (a)
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VSUPPLY
UVLO/SYNC
MCU
FSYNC
Figure 9-14. UVLO, Standby, and Clock Synchronization (b)
If the UVLO function is not required, the shutdown and clock synchronization functions can be implemented
together by using one push-pull output of the MCU. In this configuration, the device shuts down if fSYNC stays
in low logic state for longer than 40 µs (typical). The device is enabled if fSYNC stays in high logic state for
longer than 1.5 µs. The device runs at fSYNC if clock pulses are provided after the device is enabled. Also, in
this configuration, it is recommended to apply the external clock pulses after the BIAS is supplied. By limiting the
current flowing into the UVLO pin below 1 mA using a current limiting resistor, the external clock pulses can be
supplied before the BIAS is supplied (see Figure 9-15).
MCU
10
UVLO/SYNC
FSYNC
Figure 9-15. Shutdown and Clock Synchronization
Figure 9-16 shows an implementation of inverted enable using external circuit.
VSUPPLY
UVLO/SYNC
LMV431
Figure 9-16. Inverted UVLO
The external clock frequency (fSYNC) must be within +25% and –30% of fRT(TYPICAL). Since the maximum duty
cycle limit and the peak current limit with slope resistor (RSL) are affected by the clock synchronization, take
extra care when using the clock synchronization function. See Section 9.3.7 and Section 9.3.12 for more
information.
9.3.7 Current Sense and Slope Compensation
The device senses switch current which flows into the SW pin, and provides a fixed internal slope compensation
ramp, helping prevent subharmonic oscillation at high duty cycle. The internal slope compensation ramp is
added to the sensed switch current for the PWM operation, but no slope compensation ramp is added to the
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sensed inductor current for the current limit operation to provide an accurate peak current limit over the input
supply voltage (see Figure 9-17).
SW
Current Limit
Comparator
±
+
+
±
PWM
Comparator
ILIM
ICS
1.1V+VSLOPE
+
VCS
I-to-V
Gain = ACS
COMP
CHF
(optional)
RCOMP
CCOMP
Figure 9-17. Current Sensing and Slope Compensation
V
VCOMP
Slope
Compensation
Ramp
VSLOPE x D + 1.1V
ACS x ICS
Figure 9-18. Current Sensing and Slope Compensation (a) at PWM Comparator Inputs
I
ILIM
Sensed Inductor
Current (ICS)
Figure 9-19. Current Sensing (b) at Current Limit Comparator Inputs
Use Equation 6 to calculate the value of the peak slope voltage (VSLOPE).
VSLOPE
500mV u
fRT
fSYNC
(6)
where
•
fSYNC is fRT if clock synchronization is not used
According to peak current mode control theory, the slope of the compensation ramp must be greater than half
of the sensed inductor current falling slope to prevent subharmonic oscillation at high duty cycle. Therefore, the
minimum amount of slope compensation in boost topology must satisfy the following inequality:
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VLOAD
VF
VSUPPLY
LM
u ACS u Margin 500mV u fSW
(7)
where
•
VF is a forward voltage drop of D1, the external diode
Typically 82% of the sensed inductor current falling slope is known as an optimal amount of the slope
compensation. By increasing the margin to 1.6, the amount of slope compensation becomes close to the optimal
amount.
If clock synchronization is not used, the fSW frequency equals the fRT frequency. If clock synchronization is used,
the fSW frequency equals the fSYNC frequency.
9.3.8 Current Limit and Minimum On Time
The device provides cycle-by-cycle peak current limit protection that turns off the internal MOSFET when the
inductor current reaches the current limit threshold (ILIM). To avoid an unexpected hiccup mode operation during
a harsh load transient condition, it is recommended to have more margin when programming the peak-current
limit.
Boost converters have a natural pass-through path from the supply to the load through the high-side power
diode (D1). Because of this path and the minimum on-time limitation of the device, boost converters cannot
provide current limit protection when the output voltage is close to or less than the input supply voltage. The
minimum on time is is calculated as Equation 8.
t ON(MIN) |
800 u 10 15
1
4 u 10
8 u RT
6
(8)
9.3.9 Feedback and Error Amplifier (FB, COMP Pin)
The feedback resistor divider is connected to an internal transconductance error amplifier that features high
output resistance (RO = 10 MΩ) and wide bandwidth (BW = 7 MHz). The internal transconductance error
amplifier sources current which is proportional to the difference between the FB pin and the SS pin voltage or
the internal reference, whichever is lower. The internal transconductance error amplifier provides symmetrical
sourcing and sinking capability during normal operation and reduces its sinking capability when the FB is greater
than OVP threshold.
To set the output regulation target, select the feedback resistor values as shown in Equation 9.
VLOAD
§R
VREF u ¨ FBT
© RFBB
·
1¸
¹
(9)
The output of the error amplifier is connected to the COMP pin, allowing the use of a Type 2 loop compensation
network. RCOMP, CCOMP, and optional CHF loop compensation components configure the error amplifier gain and
phase characteristics to achieve a stable loop response. The absolute maximum voltage rating of the FB pin is
4.0 V. If necessary, especially during automotive load dump transient, the feedback resistor divider input can be
clamped by using an external zener diode.
The COMP pin features internal clamps. The maximum COMP clamp limits the maximum COMP pin voltage
below its absolute maximum rating even in shutdown. The minimum COMP clamp limits the minimum COMP
pin voltage to start switching as soon as possible during no load to heavy load transition. The minimum COMP
clamp is disabled when FB is connected to ground in flyback topology.
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9.3.10 Power-Good Indicator (PGOOD Pin)
The device has a power-good indicator (PGOOD) to simplify sequencing and supervision. The PGOOD switches
to a high impedance open-drain state when the FB pin voltage is greater than the feedback undervoltage
threshold (VUVTH), the VCC is greater than the VCC UVLO threshold and the UVLO/EN is greater than
the EN threshold. A 25-μs deglitch filter prevents any false pulldown of the PGOOD due to transients. The
recommended minimum pullup resistor value is 10 kΩ.
Due to the internal diode path from the PGOOD pin to the BIAS pin, the PGOOD pin voltage cannot be greater
than VBIAS + 0.3 V.
9.3.11 Hiccup Mode Overload Protection (MODE Pin)
To further protect the converter during prolonged current limit conditions, the device provides selectable hiccup
mode overload protection. This function is enabled by a single resistor (37.4 kΩ or 62.0 kΩ) between the MODE
pin and the AGND pin or by programming the MODE pin voltage (370 mV or 620 mV) during initial power
up. The internal hiccup mode fault timer of the device counts the PWM clock cycles when the cycle-by-cycle
current limiting occurs after soft start is finished. When the hiccup mode fault timer detects 64 cycles of current
limiting, an internal hiccup mode off timer forces the device to stop switching and pulls down SS. Then, the
device restarts after 32 768 cycles of hiccup mode off time. The 64 cycle hiccup mode fault timer is reset if eight
consecutive switching cycles occur without exceeding the current limit threshold. The soft-start time must be long
enough not to trigger the hiccup mode protection after the soft start is finished.
64 cycles of
current limit
32768 hiccup
mode off cycles
60 cycles of
current limit
7 normal
switching
cycles
4 cycles of
current limit
32768 hiccup
mode off cycles
Inductor Current
Time
Figure 9-20. Hiccup Mode Overload Protection
9.3.12 Maximum Duty Cycle Limit and Minimum Input Supply Voltage
The practical duty cycle is greater than the estimated due to voltage drops across the MOSFET and sense
resistor. The estimated duty cycle is calculated as shown in Equation 10.
D
1
VSUPPLY
VLOAD VF
(10)
When designing boost converters, the maximum required duty cycle must be reviewed at the minimum supply
voltage. The minimum input supply voltage that can achieve the target output voltage is limited by the maximum
duty cycle limit, and it can be estimated as follows:
VSUPPLY(MIN) | VLOAD
VF u 1 DMAX
ISUPPLY(MAX) u RDCR
ISUPPLY(MAX) u 110m u DMAX
(11)
where
•
•
ISUPPLY(MAX) is the maximum input current
RDCR is the DC resistance of the inductor
DMAX1
26
1 0.1u
fSYNC
fRT
(12)
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DMAX2
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1 100ns u fSW
(13)
The minimum input supply voltage can be further decreased by supplying fSYNC which is less than fRT. Practical
DMAX is DMAX1 or DMAX2, whichever is lower.
9.3.13 Internal MOSFET (SW Pin)
The device provides an internal switch with an rDS(ON) that is typically 45 mΩ when the BIAS pin is greater than
5 V. The rDS(ON) of the internal switch is increased when the BIAS pin is less than 5 V. The device temperature
must be checked at the minimum supply voltage especially when the BIAS pin is less than 5 V.
The dV/dT of the SW pin must be limited during the 90-µs internal start-up delay to avoid a false turn-on, which
is caused by the coupling through CDG parasitic capacitance of the internal MOSFET switch.
9.3.14 Overvoltage Protection (OVP)
The device has OVP for the output voltage. OVP is sensed at the FB pin. If the voltage at the FB pin rises above
the overvoltage threshold (VOVTH), OVP is triggered and switching stops. During OVP, the internal error amplifier
is operational, but the maximum source and sink capability is decreased to 60 µA.
9.3.15 Thermal Shutdown (TSD)
An internal thermal shutdown turns off the VCC regulator, disables switching, and pulls down the SS when
the junction temperature exceeds the thermal shutdown threshold (TTSD). After the junction temperature is
decreased by 15°C, the VCC regulator is enabled again and the device performs a soft start.
9.4 Device Functional Modes
9.4.1 Shutdown Mode
If the UVLO/EN/SYNC pin voltage is below VEN for longer than 40 µs (typical), the device goes into shutdown
mode with all functions disabled. In shutdown mode, the device decreases the BIAS pin current consumption to
below 2.6 μA (typical).
9.4.2 Standby Mode
If the UVLO/EN/SYNC pin voltage is greater than VEN and below VUVLO for longer than 1.5 µs, the device enters
standby mode with the VCC regulator operational, RT regulator operational, SS pin grounded, and no switching.
The PGOOD is activated when the VCC voltage is greater than the VCC UV threshold.
9.4.3 Run Mode
If the UVLO pin voltage is above VUVLO and the VCC voltage is sufficient, the device enters RUN mode.
9.4.3.1 Spread Spectrum Enabled
The spread spectrum function is enabled by a single resistor (37.4 kΩ ±5% or 100 kΩ ±5%) between the MODE
pin and the AGND pin or by programming the MODE pin voltage (370 mV ±10% or greater than 1.0 V) during
initial power up. To switch the spread spectrum function, EN must be grounded for more than 60 µs, or VCC
must be fully discharged.
9.4.3.2 Hiccup Mode Protection Enabled
The hiccup mode protection is enabled by a single resistor (37.4 kΩ ±5% or 62.0 kΩ ±5%) between the MODE
pin and the AGND pin or by programming the MODE pin voltage (370 mV ±10% or 620 mV ±10%) during initial
power up. To switch the hiccup mode protection function, EN should be grounded for more than 60 µs, or VCC
must be fully discharged.
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
TI provides three application notes that explain how to design boost, SEPIC, and flyback converters using the
device. These comprehensive application notes include component selections and loop response optimization.
See these application reports for more information on loop response and component selection:
•
•
•
How to Design a Boost Converter Using LM5157x
How to Design an Isolated Flyback Converter Using LM5157x
How to Design a SEPIC Converter Using LM5157x
10.2 Typical Application
Figure 10-1 shows all optional components to design a boost converter.
RSNB
CSNB
LM
VSUPP LY
VLOAD
RBIAS
CBIAS
D1
RVCC CVCC
CIN
COUT1 COUT2
RUVL OT
BIAS VCC
RUVL OS
UVLO
RUVL OB
CSS
CUVL O
SW
FB
RT
PGO OD
SS
COMP
PGND AGND MODE
RT
+
±
RFBT
RMODE
RLOAD
MCU_V CC
RFBB
CHF
RCOMP
CCOMP
Figure 10-1. Typical Boost Converter Circuit With Optional Components
10.2.1 Design Requirements
Table 10-1 shows the intended input, output, and performance parameters for this application example.
Table 10-1. Design Example Parameters
DESIGN PARAMETER
VALUE
Minimum input supply voltage (VSUPPLY(MIN))
6V
Target output voltage (VLOAD)
12 V
Maximum load current (ILOAD)
1.6 A (≈ 19.2 Watt)
Typical switching frequency (fSW)
2100 kHz
10.2.2 Detailed Design Procedure
Use the Quick Start Calculator to expedite the process of designing of a regulator for a given application.
Download these Quick Start Calculator for more information on loop response and component selection:
•
•
28
LM5157x Boost Quick Start Calculator
LM5157x Flyback Quick Start Calculator
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LM5157x SEPIC Quick Start Calculator
The device is also WEBENCH® Designer enabled. The WEBENCH software uses an iterative design procedure
and accesses comprehensive data bases of components when generating a design.
10.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
10.2.2.2 Recommended Components
Table 10-2 shows a recommended list of materials for this typical application.
Table 10-2. List of Materials
REFERENCE
DESIGNATOR
QTY.
SPECIFICATION
MANUFACTURER(1)
PART NUMBER
RT
1
RES, 9.53 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603
Vishay-Dale
CRCW06039K53FKEA
RFBT
1
RES, 49.9 k, 1%, 0.1 W, 0603
Yageo America
RC0603FR-0749K9L
RFBB
1
RES, 4.53 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603
Vishay-Dale
CRCW06034K53FKEA
LM
1
Inductor, Shielded, Composite, 1.5 μH, 14 A,
0.01052 Ω, AEC-Q200 Grade 1, SMD
Coilcraft
XEL6030-152MEB
COUT1
6
CAP, CERM, 4.7 µF, 50 V, ±10%, X7R, 1210
TDK
C3225X7R1H475K250AB
COUT2 (Bulk)
2
CAP, Aluminum Polymer, 100 µF, 50 V, ±20%, 0.025
Ω, AEC-Q200 Grade 2, D10xL10mm SMD
Chemi-Con
HHXB500ARA101MJA0G
CIN1
4
CAP, CERM, 10 µF, 50 V, ±10%, X7R, 1210
MuRata
GRM32ER71H106KA12L
CIN2 (Bulk)
1
CAP, AL, 22 uF, 100 V, ±20%, 1.3 Ω, AEC-Q200
Grade 2, SMD
Panasonic
EEE-FK2A220P
D1
1
Diode, Schottky, 45 V, 10 A, AEC-Q101, CFP15
Nexperia
PMEG045V100EPDAZ
RCOMP
1
RES, 2.61 k, 1%, 0.1 W, 0603
Yageo America
RC0603FR-072K61L
CCOMP
1
CAP, CERM, 0.01 μF, 50 V, ±10%, X7R, 0603
Kemet
C0603X103K5RACTU
CHF
1
CAP, CERM, 100 pF, 50 V, ±5%, C0G/NP0, AECQ200 Grade 0, 0603
TDK
CGA3E2NP01H101J080AA
RUVLOT
1
RES, 61.9 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603
Vishay-Dale
CRCW060361K9FKEA
RUVLOB
1
RES, 71.5 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603
Vishay-Dale
CRCW060371K5FKEA
RUVLOS
1
RES, 0, 5%, 0.1 W, 0603
Yageo America
RC0603JR-070RL
CSS
1
CAP, CERM, 0.022 μF, 50 V, ±10%, X7R, 0603
Kemet
C0603X223K5RACTU
RBIAS
1
RES, 0, 5%, 0.1 W, 0603
Yageo America
RC0603JR-070RL
CBIAS
1
CAP, CERM, 0.1 μF, 100 V, ±10%, X7R, AEC-Q200
Grade 1, 0603
MuRata
GCJ188R72A104KA01D
CVCC
1
CAP, CERM, 1 µF, 16 V, ±10%, X7R, AEC-Q200
Grade 1, 0603
TDK
CGA3E1X7R1C105K080AC
RVCC
1
RES, 5.1, 5%, 0.1 W, 0603
Yageo America
RC0603JR-075R1L
RPG
1
RES, 100 k, 1%, 0.1 W, AEC-Q200 Grade 0, 0603
Vishay-Dale
CRCW0603100KFKEA
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Table 10-2. List of Materials (continued)
REFERENCE
DESIGNATOR
QTY.
SPECIFICATION
MANUFACTURER(1)
PART NUMBER
RMODE
1
RES, 0, 5%, 0.1 W, 0603
Yageo America
RC0603JR-070RL
(1)
See the Third-Party Products Disclaimer.
10.2.2.3 Inductor Selection (LM)
When selecting the inductor, consider three key parameters: inductor current ripple ratio (RR), falling slope of the
inductor current, and RHP zero frequency (fRHP).
Inductor current ripple ratio is selected to have a balance between core loss and copper loss. The falling slope
of the inductor current must be low enough to prevent subharmonic oscillation at high duty cycle (additional RSL
resistor is required if not). Higher fRHP (lower inductance) allows a higher crossover frequency and is always
preferred when using a small value output capacitor.
The inductance value can be selected to set the inductor current ripple between 30% and 70% of the average
inductor current as a good compromise between RR, FRHP, and inductor falling slope.
10.2.2.4 Output Capacitor (COUT)
There are a few ways to select the proper value of output capacitor (COUT). The output capacitor value can be
selected based on output voltage ripple, output overshoot, or undershoot due to load transient.
The ripple current rating of the output capacitors must be enough to handle the output ripple current. By using
multiple output capacitors, the ripple current can be split. In practice, ceramic capacitors are placed closer to the
diode and the MOSFET than the bulk aluminum capacitors in order to absorb the majority of the ripple current.
10.2.2.5 Input Capacitor
The input capacitors decrease the input voltage ripple. The required input capacitor value is a function of the
impedance of the source power supply. More input capacitors are required if the impedance of the source power
supply is not low enough.
10.2.2.6 Diode Selection
A Schottky is the preferred type for a D1 diode due to its low forward voltage drop and small reverse recovery
charge. Low reverse leakage current is an important parameter when selecting the Schottky diode. The diode
must be rated to handle the maximum output voltage plus any switching node ringing. Also, it must be able to
handle the average output current.
10.2.3 Application Curve
100
Efficiency (%)
90
80
70
60
VSUPPLY
VSUPPLY
VSUPPLY
VSUPPLY
50
=9V
=6V
=4V
=3V
40
0
0.2
0.4
0.6
0.8
1
Output Current (A)
1.2
1.4
1.6
Figure 10-2. Efficiency versus Output Current
30
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10.3 System Examples
VLOAD
VSUPP LY
BIAS VCC
SW
UVLO
FB
RT
COMP
SS
PGO OD
PGND AGND MODE
Figure 10-3. Typical Boost Application
VSUPP LY = 2.9V - 45V
-
VLOAD
+
Car
Battery
BIAS VCC
To MCU
From MCU
SW
FB
PGO OD
UVLO
COMP
SS
RT
PGND AGND MODE
Figure 10-4. Typical Start-Stop Application
VSUPP LY = Min 2.9 V
VLOAD = 12V
+
BIAS VCC
1-cell or
2-cell
Battery
-
PGO OD
From MCU
UVLO
SW
FB
COMP
SS
RT
PGND AGND MODE
Figure 10-5. Emergency-Call/Boost On-Demand/Portable Speaker
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VLOAD
BIAS VCC
SW
UVLO
Option al
VSUPP LY
FB
RT
COMP
SS
PGO OD
PGND AGND MODE
Figure 10-6. Typical SEPIC Application
Inducta nce shoul d b e small enoug h
to o perate in DCM a t ful l loa d
VSUPP LY
BIAS VCC
UVLO
VLOAD = 15V - 48V
SW
FB
RT
COMP
SS
PGO OD
From MCU
PGND AGND MODE
Figure 10-7. LiDAR Bias Supply 1 (DCM Operation)
VLOAD = 90V - 144 V
Voltage
Tripler
VSUPP LY
Inducta nce shoul d b e b ig e nough
to o perate in CCM
BIAS VCC
SW
From MCU
UVLO
FB
RT
COMP
SS
PGO OD
PGND AGND MODE
Figure 10-8. LiDAR Bias Supply 2 (CCM Operation)
32
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VSUPP LY
VLOAD
BIAS VCC
SW
UVLO
FB
RT
COMP
SS
PGO OD
PGND AGND MODE
Ena ble Sprea d S pectru m
Figure 10-9. Low-Cost Single String LED Driver
VSUPP LY
VLOAD = 5V/12V
BIAS
SW
UVLO/SYNC
PGND
AGND
VCC
PGO OD
MODE
RT
FB
SS
COMP
Optiona l P rimary-Side
Soft-Start
Figure 10-10. Secondary-Side Regulated Isolated Flyback
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VLOAD 2 = +1 2V
VSUPP LY
V LOAD 3 = -8.5V
BIAS
SW
UVLO/SYNC
Optiona l DC Coupli ng
Capacitor for Low EMI
Isol ated S epic
AGND
PGND
To MCU
System Power
PGO OD
MODE
VLOAD1 = 3.3V/5V +/-2%
RT
FB
SS
COMP
VCC
Figure 10-11. Primary-Side Regulated Multiple-Output Isolated Flyback/Isolated SEPIC
VSUPP LY
VLOAD = 5V/12V
BIAS
SW
UVLO/SYNC
PGND
AGND
To MCU
System Power
PGO OD
VCC
MODE
RT
SS
COMP
FB
Figure 10-12. Typical Non-Isolated Flyback
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11 Power Supply Recommendations
The device is designed to operate from a power supply or a battery whose voltage range is from 1.5 V to 45
V. The input power supply must be able to supply the maximum boost supply voltage and handle the maximum
input current at 1.5 V. The impedance of the power supply and battery including cables must be low enough that
an input current transient does not cause an excessive drop. Additional input ceramic capacitors can be required
at the supply input of the converter.
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12 Layout
12.1 Layout Guidelines
The performance of switching converters heavily depends on the quality of the PCB layout. The following
guidelines will help users design a PCB with the best power conversion performance, thermal performance, and
minimize generation of unwanted EMI.
•
•
•
•
•
•
•
•
•
•
36
Put the D1 component on the board first.
Use a small size ceramic capacitor for COUT.
Make the switching loop (COUT to D1 to SW to PGND to COUT) as small as possible.
Leave a copper area near the D1 diode for thermal dissipation.
Put the RVCC resistor in series with the CVCC capacitor as near the device as possible between the VCC and
PGND pins.
Connect the COMP pin to the compensation components (RCOMP and CCOMP).
Connect the CCOMP capacitor to the analog ground trace.
Connect the AGND pin directly to the analog ground plane. Connect the AGND pin to the RMODE, RUVLOB, RT,
CSS, and RFBB components.
Connect the exposed pad to the AGND pin under the device.
Add several vias under the exposed pad to help conduct heat away from the device. Connect the vias to a
large ground plane on the bottom layer.
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12.2 Layout Examples
Thermal Dissipation
Area
VSUPPLY
GND
VLOAD
Do not connect input and
output capacitor grounds
underneath the device
D1
CVIN
LM
GND
COUT2
COUT1
SW
SW
16
15
14
13
PGND
1
VCC
2
11 MODE
BIAS
3
10
SS
PGO OD
4
9
FB
RT
5
6
7
8
RT
AGND
COMP
Connect to
pull-up resistor
RUVLOB
Connect to
VLOAD / VSUPPLY
UVLO
EP
RVCC
Connect to the ground
connection of CIN using
inner layer
Connect
to VLOAD
12 SW
RCOMP
RMODE
CSS
Connect to the ground connection
of COUT using inner layer
RFBT
CVCC
NC
Power Ground Plane
(Connect to EP via PGND pin)
PGND
CVIN
RFBB
CCOMP
Analog Ground Plane
(Connect to EP via AGND pin)
RUVLOT
Connect
to VSUPPLY
Figure 12-1. PCB Layout Example
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
13.1.2 Development Support
13.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM5157x-Q1 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
13.1.3 Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as
defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled
product restricted by other applicable national regulations, received from disclosing party under nondisclosure
obligations (if any), or any direct product of such technology, to any destination to which such export or re-export
is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.
Department of Commerce and other competent Government authorities to the extent required by those laws.
13.2 Documentation Support
For related documentation, see the following:
•
•
•
Texas Instruments, How to Design a Boost Converter Using LM5157x
Texas Instruments, How to Design an Isolated Flyback Converter Using LM5157x
Texas Instruments, How to Design a SEPIC Converter Using LM5157x
13.2.1 Related Documentation
For related documentation see the following:
•
• Texas Instruments, LM5157Q1EVM-BST User's Guide
• Texas Instruments, LM5157Q1EVM-FLY User's Guide
• Texas Instruments, LM5157Q1EVM-SEPIC User's Guide
13.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
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13.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
WEBENCH® is a registered trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
1-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LM51571QRTERQ1
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 150
51571Q
LM5157QRTERQ1
ACTIVE
WQFN
RTE
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 150
L5157Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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