LMC6024IMX

LMC6024 www.ti.com SNOS621D – AUGUST 2000 – REVISED MARCH 2013 LMC6024 Low Power CMOS Quad Operational Amplifier Check for Samples: LMC6024 FEATURES DESCRIPTION • • • • • • • • • The LMC6024 is a CMOS quad operational amplifier which can operate from either a single supply or dual supplies. Its performance features include an input common-mode range that reaches V−, low input bias current and voltage gain (into 100 kΩ and 5 kΩ loads) that is equal to or better than widely accepted bipolar equivalents, while the power supply requirement is less than 1 mW. 1 2 Specified for 100 kΩ and 5 kΩ Loads High Voltage Gain 120 dB Low Offset Voltage Drift 2.5 μV/°C Ultra Low Input Bias Vurrent 40 fA Input Common-mode Range Includes V− Operating Range from +5V to +15V Supply Low Distortion 0.01% at 1 kHz Slew Rate 0.11 V/μs Micropower Operation 1 mW APPLICATIONS • • • • • • • This chip is built with Texas Instrument's advanced Double-Poly Silicon-Gate CMOS process. See the LMC6022 datasheet for a CMOS dual operational amplifier with these same features. High-impedance Buffer or Preamplifier Current-to-voltage Converter Long-term Integrator Sample-and-hold Circuit Peak Detector Medical Instrumentation Industrial Controls Connection Diagram Top View Figure 1. 14-Pin DIP and SOIC Package See Package Number D0014A These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2013, Texas Instruments Incorporated LMC6024 SNOS621D – AUGUST 2000 – REVISED MARCH 2013 Absolute Maximum Ratings www.ti.com (1) (2) Differential Input Voltage ±Supply Voltage Supply Voltage (V+ − V−) 16V Lead Temperature Soldering, 10 sec. 260°C −65°C to +150°C Storage Temperature Range (V ) + 0.3V, (V−) − 0.3V + Voltage at Output/Input Pin Current at Input Pin ±5 mA Current at Output Pin ±18 mA Current at Power Supply Pin 35 mA Output Short Circuit to V+ See (3) − See (4) Output Short Circuit to V Junction Temperature 150°C ESD Tolerance (5) 1000V Power Dissipation See (6) (1) (2) (3) (4) (5) (6) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Do not connect output to V+ when V+ is greater than 13V or reliability may be adversely affected. Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature and/or multiple Op Amp shorts can result in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30 mA over long term may adversly affect reliability. Human body model, 100 pF discharge through a 1.5 kΩ resistor. The maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(max) − TA)/θJA. Operating Ratings −40°C ≤ TJ ≤ +85°C Temperature Range Supply Voltage Range 4.75V to 15.5V See (1) Power Dissipation Thermal Resistance (θJA) (2) 14-Pin DIP 14-Pin SOIC (1) (2) 2 85°C/W 115°C/W For operating at elevated temperatures the device must be derated based on the thermal resistance θJA with PD = (TJ − TA)/θJA. All numbers apply for packages soldered directly into a PC board. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LMC6024 LMC6024 www.ti.com SNOS621D – AUGUST 2000 – REVISED MARCH 2013 DC Electrical Characteristics The following specifications apply for V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V, and RL = 1M unless otherwise noted. Boldface limits apply at the temperature extremes; all other limits TJ = 25°C. Parameter VOS Test Conditions Input Offset Voltage Typical (1) 1 ΔVOS/ΔT Input Offset Voltage Average Drift 2.5 IB Input Bias Current 0.04 IOS Input Offset Current Input Resistance CMRR Common Mode Rejection Ratio 0V ≤ VCM ≤ 12V 9 mV Max μV/°C pA 200 Max 100 pA Max >1 Positive Power Supply Rejection Ratio 5V ≤ V+ ≤ 15V −PSRR Negative Power Supply Rejection Ratio 0V ≤ V− ≤ −10V VCM Input Common-Mode Voltage Range V+ = 5V and 15V For CMRR ≥ 50 DB 83 V+ = 15V Units 11 0.01 RIN +PSRR LMC6024I Limit (2) TeraΩ 63 dB Min 61 83 63 dB Min 61 94 74 −0.4 −0.1 dB Min 73 0 V+ − 1.9 V Max V+ − 2.3 V Min V+ − 2.5 AV Large Signal Voltage Gain RL = 100 kΩ (3) Sourcing 1000 200 100 Sinking 500 90 40 RL = 5 kΩ (3) Sourcing 1000 Sinking 250 100 75 50 20 VO Output Voltage Swing V+ = 5V RL = 100 kΩ to 2.5V 4.987 0.06 4.940 V Min V Max V Min 4.00 0.040 0.25 14.970 14.00 V Max V Min 13.90 0.007 0.06 0.09 14.840 V Max 13.70 V Min 13.50 0.110 0.32 0.40 (1) (2) (3) V/mV Min 4.20 0.35 V+ = 15V RL = 5 kΩ to 7.5V V/mV Min 4.40 0.09 V+ = 15V RL = 100 kΩ to 7.5V V/mV Min 4.43 0.004 V+ = 5V RL = 5 kΩ to 2.5V V/mV Min V Max Typical values represent the most likely parametric norm. All limits are guaranteed by testing or correlation. V+ = 15V, VCM = 7.5V, and RL connected to 7.5V. For Sourcing tests, 7.5V ≤ VO ≤ 11.5V. For Sinking tests, 2.5V ≤ VO ≤ 7.5V. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LMC6024 3 LMC6024 SNOS621D – AUGUST 2000 – REVISED MARCH 2013 www.ti.com DC Electrical Characteristics (continued) The following specifications apply for V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V, and RL = 1M unless otherwise noted. Boldface limits apply at the temperature extremes; all other limits TJ = 25°C. Parameter IO Output Current Test Conditions V+ = 5V Sourcing, VO = 0V Sinking VO = 5V (4) Typical (1) LMC6024I Limit (2) 22 13 Units mA Min 9 21 13 mA Min 9 V+ = 15V Sourcing, VO = 0V Sinking, VO = 13V 40 23 mA Min 15 (5) 39 23 160 240 mA Min 15 IS (4) (5) Supply Current All Four Amplifiers VO = 1.5V μA Max 280 Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature and/or multiple Op Amp shorts can result in exceeding the maximum allowed junction temperature of 150°C. Output currents in excess of ±30 mA over long term may adversly affect reliability. Do not connect output to V+ when V+ is greater than 13V or reliability may be adversely affected. AC Electrical Characteristics The following specifications apply for V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V, and RL = 1M unless otherwise noted. Boldface limits apply at the temperature extremes; all other limits TJ = 25°C. Parameter SR Slew Rate Test Conditions See (3) Typical (1) LMC6024I Limit (2) 0.11 0.05 0.03 Units V/μs Min GBW Gain-Bandwidth Product 0.35 MHz θM Phase Margin 50 Deg GM Gain Margin 17 dB (4) Amp-to-Amp Isolation See 130 dB en Input-Referred Voltage Noise F = 1 kHz 42 nV/√Hz in Input-Referred Current Noise F = 1 kHz 0.0002 pA/√Hz (1) (2) (3) (4) 4 Typical values represent the most likely parametric norm. All limits are guaranteed by testing or correlation. V+ = 15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of the positive and negative slew rates. Input referred, V+ = 15V and RL = 100 kΩ connected to 7.5V. Each amp excited in turn with 1 kHz to produce VO = 13 VPP. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LMC6024 LMC6024 www.ti.com SNOS621D – AUGUST 2000 – REVISED MARCH 2013 Typical Performance Characteristics VS = ±7.5V, TA = 25°C unless otherwise specified Supply Current vs Supply Voltage Input Bias Current vs Temperature Figure 2. Figure 3. Common-Mode Voltage Range vs Temperature Output Characteristics Current Sinking Figure 4. Figure 5. Output Characteristics Current Sourcing Input Voltage Noise vs Frequency Figure 6. Figure 7. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LMC6024 5 LMC6024 SNOS621D – AUGUST 2000 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VS = ±7.5V, TA = 25°C unless otherwise specified 6 Crosstalk Rejection vs Frequency CMRR vs Frequency Figure 8. Figure 9. CMRR vs Temperature Power Supply Rejection Ratio vs Frequency Figure 10. Figure 11. Open-Loop Voltage Gain vs Temperature Open-Loop Frequency Response Figure 12. Figure 13. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LMC6024 LMC6024 www.ti.com SNOS621D – AUGUST 2000 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VS = ±7.5V, TA = 25°C unless otherwise specified Gain and Phase Responses vs Load Capacitance Gain and Phase Responses vs Temperature Figure 14. Figure 15. Gain Error (VOS vs VOUT) Non-Inverting Slew Rate vs Temperature Figure 16. Figure 17. Inverting Slew Rate vs Temperature Large-Signal Pulse Non-Inverting Response (AV = +1) Figure 18. Figure 19. Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LMC6024 7 LMC6024 SNOS621D – AUGUST 2000 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VS = ±7.5V, TA = 25°C unless otherwise specified Non-Inverting Small Signal Pulse Response (AV = +1) Inverting Large-Signal Pulse Response Figure 20. Figure 21. Inverting Small-Signal Pulse Response Stability vs Capacitive Load Figure 22. Avoid resistive loads of less than 500Ω, as they may cause instability. Figure 23. Stability vs Capacitive Load Figure 24. 8 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LMC6024 LMC6024 www.ti.com SNOS621D – AUGUST 2000 – REVISED MARCH 2013 APPLICATION HINTS AMPLIFIER TOPOLOGY The topology chosen for the LMC6024 is unconventional (compared to general-purpose op amps) in that the traditional unity-gain buffer output stage is not used; instead, the output is taken directly from the output of the integrator, to allow rail-to-rail output swing. Since the buffer traditionally delivers the power to the load, while maintaining high op amp gain and stability, and must withstand shorts to either rail, these tasks now fall to the integrator. As a result of these demands, the integrator is a compound affair with an embedded gain stage that is doubly fed forward (via Cf and Cff) by a dedicated unity-gain compensation driver. In addition, the output portion of the integrator is a push-pull configuration for delivering heavy loads. While sinking current the whole amplifier path consists of three gain stages with one stage fed forward, whereas while sourcing the path contains four gain stages with two fed forward. Figure 25. LMC6024 Circuit Topology (Each Amplifier) The large signal voltage gain while sourcing is comparable to traditional bipolar op amps, for load resistance of at least 5 kΩ. The gain while sinking is higher than most CMOS op amps, due to the additional gain stage; however, when driving load resistance of 5 kΩ or less, the gain will be reduced as indicated in the Electrical Characterisitics. The op amp can drive load resistance as low as 500Ω without instability. COMPENSATING INPUT CAPACITANCE Refer to the LMC660 or LMC662 datasheets to determine whether or not a feedback capacitor will be necessary for compensation and what the value of that capacitor would be. CAPACITIVE LOAD TOLERANCE Like many other op amps, the LMC6024 may oscillate when its applied load appears capacitive. The threshold of oscillation varies both with load and circuit gain. The configuration most sensitive to oscillation is a unity-gain follower. See the Typical Performance Characteristics. The load capacitance interacts with the op amp's output resistance to create an additional pole. If this pole frequency is sufficiently low, it will degrade the op amp's phase margin so that the amplifier is no longer stable at low gains. The addition of a small resistor (50Ω to 100Ω) in series with the op amp's output, and a capacitor (5 pF to 10 pF) from inverting input to output pins, returns the phase margin to a safe value without interfering with lower-frequency circuit operation. Thus, larger values of capacitance can be tolerated without oscillation. Note that in all cases, the output will ring heavily when the load capcitance is near the threshold for oscillation. Figure 26. Rx, Cx Improve Capacitive Load Tolerance Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LMC6024 9 LMC6024 SNOS621D – AUGUST 2000 – REVISED MARCH 2013 www.ti.com Capacitive load driving capability is enhanced by using a pull up resistor to V+ (Figure 27). Typically a pull up resistor conducting 50 μA or more will significantly improve capacitive load responses. The value of the pull up resistor must be determined based on the current sinking capability of the amplifier with respect to the desired output swing. Open loop gain of the amplifier can also be affected by the pull up resistor (see DC Electrical Characteristics). Figure 27. Compensating for Large Capacitive Loads with a Pull Up Resistor PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the LMC6024, typically less than 0.04 pA, it is essential to have an excellent layout. Fortunately, the techniques for obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board, even though it may sometimes appear acceptably low, because under conditions of high humidity or dust or contamination, the surface leakage will be appreciable. To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC6024's inputs and the terminals of capacitors, diodes, conductors, resistors, relay terminals, etc. connected to the op-amp's inputs. See Figure 28. To have a significant effect, guard rings should be placed on both the top and bottom of the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifier inputs, since no leakage current can flow between two points at the same potential. For example, a PC board trace-to-pad resistance of 1012 ohms, which is normally considered a very large resistance, could leak 5 pA if the trace were a 5V bus adjacent to the pad of an input. This would cause a 100 times degradation from the LMC6024's actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a resistance of 1011 ohms would cause only 0.05 pA of leakage current, or perhaps a minor (2:1) degradation of the amplifier's performance. See Figure 28, Figure 30, and Figure 31 for typical connections of guard rings for standard op-amp configurations. If both inputs are active and at high impedance, the guard can be tied to ground and still provide some protection; see Figure 32. Figure 28. Example of Guard Ring in P.C. Board Layout (Using the LMC6024) 10 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LMC6024 LMC6024 www.ti.com SNOS621D – AUGUST 2000 – REVISED MARCH 2013 Guard Ring Connections Figure 29. Inverting Amplifier Guard Ring Connections Figure 30. Non-Inverting Amplifier Guard Ring Connections Figure 31. Follower Guard Ring Connections Figure 32. Howland Current Pump Guard Ring Connections The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few circuits, there is another technique which is even better than a guard ring on a PC board: Don't insert the amplifier's input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 33. (Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board.) Figure 33. Air Wiring Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LMC6024 11 LMC6024 SNOS621D – AUGUST 2000 – REVISED MARCH 2013 www.ti.com BIAS CURRENT TESTING The test method of Figure 34 is appropriate for bench-testing bias current with reasonable accuracy. To understand its operation, first close switch S2 momentarily. When S2 is opened, then (1) Figure 34. Simple Input Bias Current Test Circuit A suitable capacitor for C2 would be a 5 pF or 10 pF silver mica, NPO ceramic, or air-dielectric. When determining the magnitude of I−, the leakage of the capacitor and socket must be taken into account. Switch S2 should be left shorted most of the time, or else the dielectric absorption of the capacitor C2 could cause errors. Similarly, if S1 is shorted momentarily (while leaving S2 shorted) (2) where Cx is the stray capacitance at the +input. Typical Single-Supply Applications (V+ = 5.0 VDC) A 5V bias on the photodiode can cut its capacitance by a factor of 2 or 3, leading to improved response and lower noise. However, this bias on the photodiode will cause photodiode leakage (also known as its dark current). Figure 35. Photodiode Current-to-Voltage Converter 12 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LMC6024 LMC6024 www.ti.com SNOS621D – AUGUST 2000 – REVISED MARCH 2013 (V+ = 5.0 VDC) Figure 36. (Upper limit of output range dictated by input common-mode range; lower limit dictated by minimum current requirement of LM385.) Figure 37. Micropower Current Source Figure 38. Low-Leakage Sample-and-Hold If R1 = R5, R3 = R6, and R4 = R7; Then . ∴AV ≈ 100 for circuit shown. For good CMRR over temperature, low drift resistors should be used. Matching of R3 to R6 and R4 to R7 affects CMRR. Gain may be adjusted through R2. CMRR may be adjusted through R7. Figure 39. Instrumentation Amplifier Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LMC6024 13 LMC6024 SNOS621D – AUGUST 2000 – REVISED MARCH 2013 www.ti.com (V+ = 5.0 VDC) fO = 10 Hz Q = 2.1 Gain = −8.8 Figure 40. 10 Hz Bandpass Filter fc = 10 Hz d = 0.895 Gain = 1 Figure 41. 10 Hz High-Pass Filter (2 dB Dip) Figure 42. 1 Hz Low-Pass Filter (Maximally Flat, Dual Supply Only) 14 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LMC6024 LMC6024 www.ti.com SNOS621D – AUGUST 2000 – REVISED MARCH 2013 (V+ = 5.0 VDC) Gain = −46.8 Output offset voltage reduced to the level of the input offset voltage of the bottom amplifier (typically 1 mV), referred to VBIAS. Figure 43. High Gain Amplifier with Offset Voltage Reduction Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LMC6024 15 LMC6024 SNOS621D – AUGUST 2000 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision C (March 2013) to Revision D • 16 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 15 Submit Documentation Feedback Copyright © 2000–2013, Texas Instruments Incorporated Product Folder Links: LMC6024 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) LMC6024IM/NOPB ACTIVE SOIC D 14 55 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC6024IM LMC6024IMX/NOPB ACTIVE SOIC D 14 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMC6024IM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of