LMC6024IN

LMC6024 Low Power CMOS Quad Operational Amplifier November 1994 LMC6024 Low Power CMOS Quad Operational Amplifier General Description The LMC6024 is a CMOS quad operational amplifier which can operate from either a single supply or dual supplies. Its performance features include an input common-mode range that reaches V−, low input bias current and voltage gain (into 100 kΩ and 5 kΩ loads) that is equal to or better than widely accepted bipolar equivalents, while the power supply requirement is less than 1 mW. This chip is built with National’s advanced Double-Poly Silicon-Gate CMOS process. See the LMC6022 datasheet for a CMOS dual operational amplifier with these same features. n n n n n n Ultra low input bias current 40 fA Input common-mode range includes V− Operating range from +5V to +15V supply Low distortion 0.01% at 1 kHz Slew rate 0.11 V/µs Micropower operation 1 mW Applications n n n n n n n High-impedance buffer or preamplifier Current-to-voltage converter Long-term integrator Sample-and-hold circuit Peak detector Medical instrumentation Industrial controls Features n Specified for 100 kΩ and 5 kΩ loads n High voltage gain 120 dB n Low offset voltage drift 2.5 µV/˚C Connection Diagram 14-Pin DIP/SO DS011235-1 Top View Ordering Information Temperature Range Industrial −40˚C ≤ TJ ≤ +85˚C LMC6024IN LMC6024IM 14-Pin Molded DIP 14-Pin Small Outline M14A Rail Tape and Reel Package NSC Drawing N14A Transport Media Rail © 1999 National Semiconductor Corporation DS011235 www.national.com Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Differential Input Voltage Supply Voltage (V+ − V−) Lead Temperature (Soldering, 10 sec.) Storage Temperature Range Voltage at Output/Input Pin Current at Input Pin Current at Output Pin Current at Power Supply Pin Output Short Circuit to V+ Output Short Circuit to V− Junction Temperature ESD Tolerance (Note 4) Power Dissipation (Note 2) 150˚C 1000V (Note 3) ± Supply Voltage 16V 260˚C −65˚C to +150˚C (V+) + 0.3V, (V−) − 0.3V ± 5 mA ± 18 mA 35 mA (Note 12) Operating Ratings Temperature Range Supply Voltage Range Power Dissipation Thermal Resistance (θJA), (Note 11) 14-Pin DIP 14-Pin SO −40˚C ≤ TJ ≤ +85˚C 4.75V to 15.5V (Note 10) 85˚C/W 115˚C/W DC Electrical Characteristics The following specifications apply for V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V, and RL = 1M unless otherwise noted. Boldface limits apply at the temperature extremes; all other limits TJ = 25˚C. Typical Symbol VOS ∆VOS/∆T IB IOS RIN CMRR +PSRR −PSRR VCM Parameter Input Offset Voltage Input Offset Voltage Average Drift Input Bias Current Input Offset Current Input Resistance Common Mode Rejection Ratio Positive Power Supply Rejection Ratio Negative Power Supply Rejection Ratio Input Common-Mode Voltage Range V+ = 5V and 15V For CMRR ≥ 50 DB V+ − 1.9 AV Large Signal Voltage Gain RL = 100 kΩ (Note 7) Sourcing Sinking RL = 5 kΩ (Note 7) Sourcing Sinking 250 500 1000 1000 −0.4 0V ≤ V− ≤ −10V 94 0V ≤ VCM ≤ 12V V+ = 15V 5V ≤ V+ ≤ 15V 0.04 200 0.01 100 pA Max pA Max TeraΩ 63 61 83 63 61 74 73 −0.1 0 V+ − 2.3 V+ − 2.5 200 100 90 40 100 75 50 20 dB Min dB Min dB Min V Max V Min V/mV Min V/mV Min V/mV Min V/mV Min Conditions (Note 5) 1 2.5 LMC6024I Limit (Note 6) 9 11 mV Max µV/˚C Units >1 83 www.national.com 2 DC Electrical Characteristics (Continued) The following specifications apply for V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V, and RL = 1M unless otherwise noted. Boldface limits apply at the temperature extremes; all other limits TJ = 25˚C. Typical Symbol VO Parameter Output Voltage Swing Conditions V+ = 5V RL = 100 kΩ to 2.5V (Note 5) 4.987 0.004 V+ = 5V RL = 5 kΩ to 2.5V 4.940 0.040 V+ = 15V RL = 100 kΩ to 7.5V 14.970 0.007 V+ = 15V RL = 5 kΩ to 7.5V 14.840 0.110 IO Output Current V+ = 5V Sourcing, VO = 0V Sinking VO = 5V (Note 2) V+ = 15V Sourcing, VO = 0V Sinking, VO = 13V (Note 12) IS Supply Current All Four Amplifiers VO = 1.5V 160 22 21 40 39 LMC6024I Limit (Note 6) 4.40 4.43 0.06 0.09 4.20 4.00 0.25 0.35 14.00 13.90 0.06 0.09 13.70 13.50 0.32 0.40 13 9 13 9 23 15 23 15 240 280 V Min V Max V Min V Max V Min V Max V Min V Max mA Min mA Min mA Min mA Min µA Max Units 3 www.national.com AC Electrical Characteristics The following specifications apply for V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V, and RL = 1M unless otherwise noted. Boldface limits apply at the temperature extremes; all other limits TJ = 25˚C. Typical Symbol SR GBW θM GM en in Slew Rate Gain-Bandwidth Product Phase Margin Gain Margin Amp-to-Amp Isolation Input-Referred Voltage Noise Input-Referred Current Noise (Note 9) F = 1 kHz F = 1 kHz Parameter Conditions (Note 8) (Note 5) 0.11 0.35 50 17 130 42 0.0002 LMC6024I Limit (Note 6) 0.05 0.03 V/µs Min MHz Deg dB dB Units Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Note 2: Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature and/or multiple Op Amp shorts can result in exceeding the maximum allowed junction temperature of 150˚C. Output currents in excess of ± 30 mA over long term may adversly affect reliability. Note 3: The maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(max) − TA)/θJA. Note 4: Human body model, 100 pF discharge through a 1.5 kΩ resistor. Note 5: Typical values represent the most likely parametric norm. Note 6: All limits are guaranteed by testing or correlation. Note 7: V+ = 15V, VCM = 7.5V, and RL connected to 7.5V. For Sourcing tests, 7.5V ≤ VO ≤ 11.5V. For Sinking tests, 2.5V ≤ VO ≤ 7.5V. Note 8: V+ = 15V. Connected as Voltage Follower with 10V step input. Number specified is the slower of the positive and negative slew rates. Note 9: Input referred, V+ = 15V and RL = 100 kΩ connected to 7.5V. Each amp excited in turn with 1 kHz to produce VO = 13 VPP. Note 10: For operating at elevated temperatures the device must be derated based on the thermal resistance θJA with PD = (TJ − TA)/θJA. Note 11: All numbers apply for packages soldered directly into a PC board. Note 12: Do not connect output to V+ when V+ is greater than 13V or reliability may be adversely affected. www.national.com 4 Typical Performance Characteristics Supply Current vs Supply Voltage VS = ± 7.5V, TA = 25˚C unless otherwise specified Common-Mode Voltage Range vs Temperature Input Bias Current vs Temperature DS011235-27 DS011235-28 DS011235-29 Output Characteristics Current Sinking Output Characteristics Current Sourcing Input Voltage Noise vs Frequency DS011235-30 DS011235-31 DS011235-32 Crosstalk Rejection vs Frequency CMRR vs Frequency CMRR vs Temperature DS011235-34 DS011235-33 DS011235-35 5 www.national.com Typical Performance Characteristics Power Supply Rejection Ratio vs Frequency VS = ± 7.5V, TA = 25˚C unless otherwise specified (Continued) Open-Loop Frequency Response Open-Loop Voltage Gain vs Temperature DS011235-36 DS011235-37 DS011235-38 Gain and Phase Responses vs Load Capacitance Gain and Phase Responses vs Temperature Gain Error (VOS vs VOUT) DS011235-39 DS011235-40 DS011235-41 Non-Inverting Slew Rate vs Temperature Inverting Slew Rate vs Temperature Large-Signal Pulse Non-Inverting Response (AV = +1) DS011235-42 DS011235-43 DS011235-44 www.national.com 6 Typical Performance Characteristics Non-Inverting Small Signal Pulse Response (AV = +1) VS = ± 7.5V, TA = 25˚C unless otherwise specified (Continued) Inverting Large-Signal Pulse Response Inverting Small-Signal Pulse Response DS011235-46 DS011235-45 DS011235-47 Stability vs Capacitive Load Stability vs Capacitive Load DS011235-4 DS011235-5 Note 13: Avoid resistive loads of less than 500Ω, as they may cause instability. Application Hints AMPLIFIER TOPOLOGY The topology chosen for the LMC6024 is unconventional (compared to general-purpose op amps) in that the traditional unity-gain buffer output stage is not used; instead, the output is taken directly from the output of the integrator, to allow rail-to-rail output swing. Since the buffer traditionally delivers the power to the load, while maintaining high op amp gain and stability, and must withstand shorts to either rail, these tasks now fall to the integrator. As a result of these demands, the integrator is a compound affair with an embedded gain stage that is doubly fed forward (via Cf and Cff) by a dedicated unity-gain compensation driver. In addition, the output portion of the integrator is a push-pull configuration for delivering heavy loads. While sinking current the whole amplifier path consists of three gain stages with one stage fed forward, whereas while sourcing the path contains four gain stages with two fed forward. DS011235-6 FIGURE 1. LMC6024 Circuit Topology (Each Amplifier) The large signal voltage gain while sourcing is comparable to traditional bipolar op amps, for load resistance of at least 5 kΩ. The gain while sinking is higher than most CMOS op amps, due to the additional gain stage; however, when driv7 www.national.com Application Hints (Continued) ing load resistance of 5 kΩ or less, the gain will be reduced as indicated in the Electrical Characterisitics. The op amp can drive load resistance as low as 500Ω without instability. COMPENSATING INPUT CAPACITANCE Refer to the LMC660 or LMC662 datasheets to determine whether or not a feedback capacitor will be necessary for compensation and what the value of that capacitor would be. CAPACITIVE LOAD TOLERANCE Like many other op amps, the LMC6024 may oscillate when its applied load appears capacitive. The threshold of oscillation varies both with load and circuit gain. The configuration most sensitive to oscillation is a unity-gain follower. See the Typical Performance Characteristics. The load capacitance interacts with the op amp’s output resistance to create an additional pole. If this pole frequency is sufficiently low, it will degrade the op amp’s phase margin so that the amplifier is no longer stable at low gains. The addition of a small resistor (50Ω to 100Ω) in series with the op amp’s output, and a capacitor (5 pF to 10 pF) from inverting input to output pins, returns the phase margin to a safe value without interfering with lower-frequency circuit operation. Thus, larger values of capacitance can be tolerated without oscillation. Note that in all cases, the output will ring heavily when the load capcitance is near the threshold for oscillation. fier with respect to the desired output swing. Open loop gain of the amplifier can also be affected by the pull up resistor (see Electrical Characteristics). DS011235-26 FIGURE 3. Compensating for Large Capacitive Loads with a Pull Up Resistor PRINTED-CIRCUIT-BOARD LAYOUT FOR HIGH-IMPEDANCE WORK It is generally recognized that any circuit which must operate with less than 1000 pA of leakage current requires special layout of the PC board. When one wishes to take advantage of the ultra-low bias current of the LMC6024, typically less than 0.04 pA, it is essential to have an excellent layout. Fortunately, the techniques for obtaining low leakages are quite simple. First, the user must not ignore the surface leakage of the PC board, even though it may sometimes appear acceptably low, because under conditions of high humidity or dust or contamination, the surface leakage will be appreciable. To minimize the effect of any surface leakage, lay out a ring of foil completely surrounding the LMC6024’s inputs and the terminals of capacitors, diodes, conductors, resistors, relay terminals, etc. connected to the op-amp’s inputs. See Figure 4. To have a significant effect, guard rings should be placed on both the top and bottom of the PC board. This PC foil must then be connected to a voltage which is at the same voltage as the amplifier inputs, since no leakage current can flow between two points at the same potential. For example, a PC board trace-to-pad resistance of 1012 ohms, which is normally considered a very large resistance, could leak 5 pA if the trace were a 5V bus adjacent to the pad of an input. This would cause a 100 times degradation from the LMC6024’s actual performance. However, if a guard ring is held within 5 mV of the inputs, then even a resistance of 1011 ohms would cause only 0.05 pA of leakage current, or perhaps a minor (2:1) degradation of the amplifier’s performance. See Figure 5a, Figure 5b, Figure 5c for typical connections of guard rings for standard op-amp configurations. If both inputs are active and at high impedance, the guard can be tied to ground and still provide some protection; see Figure 5d. DS011235-7 FIGURE 2. Rx, Cx Improve Capacitive Load Tolerance Capacitive load driving capability is enhanced by using a pull up resistor to V+ Figure 3. Typically a pull up resistor conducting 50 µA or more will significantly improve capacitive load responses. The value of the pull up resistor must be determined based on the current sinking capability of the ampli- www.national.com 8 Application Hints (Continued) DS011235-8 FIGURE 4. Example of Guard Ring in P.C. Board Layout (Using the LMC6024) DS011235-10 (b) Non-Inverting Amplifier DS011235-9 (a) Inverting Amplifier DS011235-11 (c) Follower DS011235-12 (d) Howland Current Pump FIGURE 5. Guard Ring Connections The designer should be aware that when it is inappropriate to lay out a PC board for the sake of just a few circuits, there is another technique which is even better than a guard ring on a PC board: Don’t insert the amplifier’s input pin into the board at all, but bend it up in the air and use only air as an insulator. Air is an excellent insulator. In this case you may have to forego some of the advantages of PC board construction, but the advantages are sometimes well worth the effort of using point-to-point up-in-the-air wiring. See Figure 6. 9 www.national.com Application Hints (Continued) DS011235-13 (Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board.) DS011235-14 FIGURE 6. Air Wiring BIAS CURRENT TESTING The test method of Figure 7 is appropriate for bench-testing bias current with reasonable accuracy. To understand its operation, first close switch S2 momentarily. When S2 is opened, then FIGURE 7. Simple Input Bias Current Test Circuit A suitable capacitor for C2 would be a 5 pF or 10 pF silver mica, NPO ceramic, or air-dielectric. When determining the magnitude of I−, the leakage of the capacitor and socket must be taken into account. Switch S2 should be left shorted most of the time, or else the dielectric absorption of the capacitor C2 could cause errors. Similarly, if S1 is shorted momentarily (while leaving S2 shorted) where Cx is the stray capacitance at the +input. Typical Single-Supply Applications Photodiode Current-to-Voltage Converter (V+ = 5.0 VDC) Micropower Current Source DS011235-15 DS011235-16 Note 14: A 5V bias on the photodiode can cut its capacitance by a factor of 2 or 3, leading to improved response and lower noise. However, this bias on the photodiode will cause photodiode leakage (also known as its dark current). (Upper limit of output range dictated by input common-mode range; lower limit dictated by minimum current requirement of LM385.) www.national.com 10 Typical Single-Supply Applications (V+ = 5.0 VDC) (Continued) Low-Leakage Sample-and-Hold DS011235-17 Instrumentation Amplifier DS011235-18 If R1 = R5, R3 = R6, and R4 = R7; Then ∴AV ≈ 100 for circuit shown. For good CMRR over temperature, low drift resistors should be used. Matching of R3 to R6 and R4 to R7 affects CMRR. Gain may be adjusted through R2. CMRR may be adjusted through R7. 10 Hz Bandpass Filter 10 Hz High-Pass Filter (2 dB Dip) DS011235-20 DS011235-19 fO = 10 Hz Q = 2.1 Gain = −8.8 fc = 10 Hz d = 0.895 Gain = 1 11 www.national.com Typical Single-Supply Applications 1 Hz Low-Pass Filter (Maximally Flat, Dual Supply Only) (V+ = 5.0 VDC) (Continued) High Gain Amplifier with Offset Voltage Reduction DS011235-21 DS011235-22 Gain = −46.8 Output offset voltage reduced to the level of the input offset voltage of the bottom amplifier (typically 1 mV), referred to VBIAS. www.national.com 12 Physical Dimensions inches (millimeters) unless otherwise noted 14-Pin Small Outline Molded Package (M) Order Number LMC6024IM NS Package Number M14A 14-Pin Molded Dual-In-Line Package (N) Order Number LMC6024IN NS Package Number N14A 13 www.national.com LMC6024 Low Power CMOS Quad Operational Amplifier LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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