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LMF100
SNOSBG9B – JULY 1999 – REVISED JUNE 2015
LMF100 Dual High-Performance Switched Capacitor Filters
Not Recommended for New Designs
1 Features
3 Description
•
•
•
The LMF100 device consists of two independent
general-purpose,
high-performance
switched
capacitor filters. With an external clock and two to
four resistors, each filter block can realize various
second-order and first-order filtering functions. Each
block has three outputs. One output can be
configured to perform either an allpass, highpass, or
notch function. The other two outputs perform
bandpass and lowpass functions. The center
frequency of each filter stage is tuned by using an
external clock or a combination of a clock and resistor
ratio. Up to a fourth-order biquadratic function can be
realized with one LMF100. Higher order filters are
implemented by simply cascading additional
packages, and all the classical filters (such as
Butterworth, Bessel, Elliptic, and Chebyshev) can be
realized.
1
•
•
•
•
Wide 4-V to 15-V Power Supply Range
Operation up to 100 kHz
Low Offset Voltage:
– Typically (50:1 or 100:1 mode):
– Vos1 = ±5 mV
– Vos2 = ±15 mV
– Vos3 = ±15 mV
Low Crosstalk: –60 dB
Clock to Center Frequency Ratio Accuracy ±0.2%
(Typical)
f0 × Q Range up to 1.8 MHz
Pin-Compatible With MF10
2 Applications
•
•
Replacing Active RC Filters With Reduced Form
Factors and Higher Accuracy and Tunability
An Alternative to Integrated Continuous Time
Filters
The LMF100 is fabricated on TI’s high-performance
analog silicon gate CMOS process, LMCMOS™. This
allows for the production of a very low-offset, highfrequency filter building block. The LMF100 is pincompatible with the industry standard MF10, but
provides greatly improved performance.
Device Information(1)
PART NUMBER
LMF100
PACKAGE
BODY SIZE (NOM)
SOIC (20)
12.60 mm × 10.00 mm
PDIP (20)
24.33 mm × 6.35 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Fourth-Order 100-kHz Butterworth Lowpass Filter
Transfer Curve of Butterworth LP Filter Roll-Off
Magnitude vs Frequency
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Not Recommended for New Designs
LMF100
SNOSBG9B – JULY 1999 – REVISED JUNE 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
Absolute Maximum Ratings ...................................... 4
ESD Ratings ............................................................ 4
Recommended Operating Conditions....................... 4
Thermal Information ................................................. 5
Electrical Characteristics for V+ = +5 V and V− = −5
V................................................................................. 5
6.6 Electrical Characteristics for V+ = +2.5 V and V− =
−2.5 V......................................................................... 6
6.7 Logic Input Characteristics........................................ 8
6.8 Typical Characteristics ............................................ 10
7
Parameter Measurement Information ................ 14
7.1 Definition of Terms Graphics .................................. 14
8
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
16
16
16
16
Application and Implementation ........................ 24
9.1 Application Information............................................ 24
9.2 Typical Application ................................................. 24
10 Power Supply Recommendations ..................... 32
11 Layout................................................................... 32
11.1 Layout Guidelines ................................................. 32
12 Device and Documentation Support ................. 33
12.1
12.2
12.3
12.4
12.5
Device Support ....................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
33
33
33
34
34
13 Mechanical, Packaging, and Orderable
Information ........................................................... 34
Detailed Description ............................................ 16
4 Revision History
Changes from Revision A (July 1999) to Revision B
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
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SNOSBG9B – JULY 1999 – REVISED JUNE 2015
5 Pin Configuration and Functions
DW and N Package
20-Pin SOIC and PDIP (N20 or M20B)
(Top View)
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
1
LP
20
2
BP
19
N/AP/HP
I
The inverting input of the summing op-amp of each filter. These are high impedance inputs. The noninverting input is
internally tied to AGND so the opamp can be used only as an inverting amplifier.
I
S1 is a signal input pin used in modes 1b, 4, and 5. The input impedance is 1/fCLK x 1 pF. The pin should be driven with
a source impedance of less than 1 kΩ. If S1 is not driven with a signal it should be tied to AGND (mid-supply).
3
17
5
S1
The second order lowpass, bandpass and notch, allpass and highpass outputs. These outputs can typically swing to
within 1 V of each supply when driving a 5-kΩ load. For optimum performance, capacitive loading on these outputs
should be minimized. For signal frequencies above 15 kHz, the capacitance loading should be kept below 30 pF.
18
4
INV
I/O
16
SA/B
6
I
This pin activates a switch that connects one of the inputs of each filter’s second summer either to AGND (SA/B tied to V−)
or to the lowpass (LP) output (SA/B tied to V+). This offers the flexibility needed for configuring the filter in its various
modes of operation.
VA+
7 (1)
I
This is both the analog and digital positive supply.
VD+
8 (1)
I
Analog and digital negative supplies. VA– and VD– should be derived from the same source. They have been brought out
separately so they can be bypassed by separate capacitors, if desired. They can also be tied together externally and
bypassed with a single capacitor.
VA–
14
I
Analog and digital negative supplies. VA– and VD– should be derived from the same source. They have been brought out
separately so they can be bypassed by separate capacitors, if desired. They can also be tied together externally and
bypassed with a single capacitor.
VD–
13
Level shift pin. This is used to accommodate various clock levels with dual or single supply operation. With dual ±5-V
supplies and CMOS (±5 V) or TTL (0 V–5 V) clock levels, LSh should be tied to system ground.
LSh
9
I
For 0-V to 10-V single-supply operation the AGND pin should be biased at +5 V and the LSh pin should be tied to the
system ground for TTL clock levels. LSh should be biased at +5 V for ±5-V CMOS clock levels.
The LSh pin is tied to system ground for ±2.5V operation. For single 5V operation the LSh and VD+ pins are tied to
system ground for TTL clock levels.
10
CLK
11
I
Clock inputs for the two switched capacitor filter sections. Unipolar or bipolar clock levels may be applied to the CLK
inputs according to the programming voltage applied to the LSh pin. The duty cycle of the clock should be close to 50%,
especially when clock frequencies above 200 kHz are used. This allows the maximum time for the internal opamps to
settle, which yields optimum filter performance.
50/100
12 (1)
I
By tying this pin to V+ a 50:1 clock to filter center frequency ratio is obtained. Tying this pin at mid-supply (i.e., system
ground with dual supplies) or to V– allows the filter to operate at a 100:1 clock to center frequency ratio.
AGND
15
I
This is the analog ground pin. This pin should be connected to the system ground for dual supply operation or biased to
mid-supply for single-supply operation. For a further discussion of mid-supply biasing techniques see the Applications
Information (Section 3.2). For optimum filter performance a “clean” ground must be provided.
(1)
This device is pin-for-pin compatible with the MF10 except for the following changes:
(a) Unlike the MF10, the LMF100 has a single positive supply pin (VA+).
(b) On the LMF100 VD+ is a control pin and is not the digital positive supply as on the MF10.
(c) Unlike the MF10, the LMF100 does not support the current limiting mode. When the 50/100 pin is tied to V– the LMF100 will remain
in the 100:1 mode.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
16
V
Supply Voltage (V+ – V–)
+
V + 0.3
Voltage at any pin
V– – 0.3
Input current at any pin (2)
Package input current
5
(2)
Power dissipation (3)
N Package: 10 sec.
Soldering information
(4)
SOIC Package
(2)
(3)
(4)
mA
20
mA
500
mW
250
Vapor Phase (60 sec)
215
Infrared (15 sec)
220
Storage temperature, Tstg
(1)
V
150
°C
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V– or the absolute value of current at that pin should be
limited to 5 mA or less. The sum of the currents at all pins that are driven beyond the power supply voltages should not exceed
20 mA.VIN+)
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, RθJA, and the ambient
temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX − TA)/RθJA or the number given in the
Absolute Maximum Ratings, whichever is lower. For this device, TJMAX = 125°C, and the typical junction-to-ambient thermal resistance
of the LMF100CIN when board mounted is 55°C/W. For the LMF100CIWM this number is 66°C/W.
See AN-450Surface Mounting Methods and Their Effect on Product Reliability(Appendix D) for other methods of soldering surface
mount devices.
6.2 ESD Ratings
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1) (2)
VALUE
UNIT
±2000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
A military RETS specification is available upon request.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Temperature
LMF100CCN
LMF100CIWM
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MAX
70
–40
85
4 ≤V+ – V– ≤
Supply voltage
4
NOM
0
15
UNIT
°C
V
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SNOSBG9B – JULY 1999 – REVISED JUNE 2015
6.4 Thermal Information
LMF100
THERMAL METRIC (1)
DW (SOIC)
N (PDIP)
20 PINS
20 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
63.8
49.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
27.2
41.1
°C/W
RθJB
Junction-to-board thermal resistance
31.8
30.4
°C/W
ψJT
Junction-to-top characterization parameter
5.7
18.3
°C/W
ψJB
Junction-to-board characterization parameter
31.3
30.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics for V+ = +5 V and V− = −5 V
The following specifications apply for Mode 1, Q = 10 (R1 = R3 = 100 k, R2 = 10 k), V+ = +5 V and V− = −5 V unless otherwise
specified. All limits are TA = TJ = 25°C unless otherwise specified.
LMF100CCN
PARAMETER
LMF100CIWM
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
9
Is
f0
fCLK
Maximum supply current
fCLK = 250 kHz,
No Input Signal
0
TMIN to TMAX
Design
Limit (2)
TMIN to TMAX
Center frequency
Clock frequency
Clock to center frequency ratio
deviation
VPin12 = 5 V or 0
V, fCLK = 1 MHz
9
Q Error (MAX)
(3)
Q
Q = 10, Mode 1,
VPin12 = 5 V or 0
V,
fCLK = 1 MHz
Bandpass gain at f0
fCLK = 1 MHz
10000
0
0.1
100000
Hz
5
35000
00
5
3500000
Hz
±0.2%
±0.8%
Tested
Limit (1)
TMIN to TMAX
Design
Limit (2)
TMIN to TMAX
±0.8%
±0.8%
±0.5%
±5%
Tested
Limit (1)
TMIN to TMAX
Design
Limit (2)
TMIN to TMAX
±6%
±6%
0
±0.4
Tested
Limit (1)
TMIN to TMAX
Design
Limit (2)
TMIN to TMAX
DC Lowpass gain
R1 = R2 = 10 k,
fCLK = 250 kHz
(1)
(2)
(3)
(4)
DC Offset voltage (4)
fCLK = 250 kHz
dB
±0.2
dB
±15
mV
0
±0.2
Tested
Limit (1)
TMIN to TMAX
Design
Limit (2)
TMIN to TMAX
±0.2
±5
VOS1
±0.4
±0.4
0
HOLP
mA
0.1
0
HOBP
13
13
±0.5%
DQ
MAX
13
Tested
Limit (1)
±0.2%
fCLK/f
TYP
±5
±15
Tested
Limit (1)
TMIN to TMAX
Design
Limit (2)
TMIN to TMAX
±15
Tested limits are specified to Texas Instruments AOQL (Average Outgoing Quality Level).
Design limits are specified to Texas Instruments AOQL (Average Outgoing Quality Level) but are not 100% tested.
The accuracy of the Q value is a function of the center frequency (f0). This is illustrated in the curves under the heading Typical
Characteristics.
Vos1, Vos2, and Vos3 refer to the internal offsets as discussed in Application Information.
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Electrical Characteristics for V+ = +5 V and V− = −5 V (continued)
The following specifications apply for Mode 1, Q = 10 (R1 = R3 = 100 k, R2 = 10 k), V+ = +5 V and V− = −5 V unless otherwise
specified. All limits are TA = TJ = 25°C unless otherwise specified.
LMF100CCN
PARAMETER
LMF100CIWM
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
±30
SA/B = V+
VOS2
±30
mV
TMIN to TMAX
fCLK = 250 kHz
±80
TMIN to TMAX
±80
±15
SA/B = V–
±15
±70
Tested Limit (1)
mV
TMIN to TMAX
Design Limit
(2)
±70
TMIN to TMAX
±70
±15
VOS3
DC Offset voltage (4)
Crosstalk
fCLK = 250 kHz
(5)
Clock feedthrough (7)
TMIN to TMAX
±60
–60
40
40
BP
320
320
LP
300
300
6
6
4
−4.7
4
−4.7
20 kHz Bandwidth
100:1 Mode
fCLK = 250 kHz 100:1 Mode
TMIN to TMAX
Design
Limit (2)
Operational amplifier gain BW
product
SR
Operational amplifier slew rate
Isc
Maximum output,
Short circuit current (8)
IIN
(5)
(6)
(7)
(8)
µV
mV
TMIN to TMAX
±3.7
V
±3.7
RL = 3.5 k
(All Outputs)
GB
W
dB
±3.8
Tested
Limit (1)
Minimum output voltage swing
mV
±60
–60
N
RL = 5 k
(All Outputs)
VOUT
TMIN to TMAX
Design
Limit (2)
A Side to B Side or B Side to A Side
Output noise (6)
±15
±40
Tested
Limit (1)
fCLK = 250 kHz
MAX
±80
Tested Limit (1)
Design Limit (2)
DC Offset voltage (4)
TYP
3.9
−4.6
3.9
−4.6
5
5
MHz
20
20
V/µs
Source
All Outputs
12
12
mA
Sink
All Outputs
45
45
mA
Input current on Pins: 4, 5, 6, 9,
10, 11, 12, 16, 17
Tested Limit (1)
10
µA
Design Limit (2)
TMIN to TMAX
10
Crosstalk between the internal filter sections is measured by applying a 1 VRMS 10-kHz signal to one bandpass filter section input and
grounding the input of the other bandpass filter section. The crosstalk is the ratio between the output of the grounded filter section and
the 1 VRMS input signal of the other section.
In 50:1 mode the output noise is 3 dB higher.
In 50:1 mode the clock feed through is 6 dB higher.
The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then
shorting that output to the negative supply. The short circuit sink current is measured by forcing the output that is being tested to its
maximum negative voltage swing and then shorting that output to the positive supply. These are the worst case conditions.
6.6 Electrical Characteristics for V+ = +2.5 V and V− = −2.5 V
The following specifications apply for Mode 1, Q = 10 (R1 = R3 = 100 k, R2 = 10 k), V+ = +2.50 V and V− = −2.50 V unless
otherwise specified. All limits are TA = TJ = 25°C unless otherwise specified.
LMF100CCN
PARAMETER
LMF100CIWM
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
8
Is
Maximum supply current
fCLK = 250 kHz,
No Input Signal
Tested
Limit (1)
(1)
(2)
6
MAX
8
12
12
mA
TMIN to TMAX
Design
Limit (2)
f0
TYP
12
Center frequency
0.1
50000
0.1
50000
Hz
Tested limits are specified to Texas Instruments AOQL (Average Outgoing Quality Level).
Design limits are specified to Texas Instruments AOQL (Average Outgoing Quality Level) but are not 100% tested.
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Electrical Characteristics for V+ = +2.5 V and V− = −2.5 V (continued)
The following specifications apply for Mode 1, Q = 10 (R1 = R3 = 100 k, R2 = 10 k), V+ = +2.50 V and V− = −2.50 V unless
otherwise specified. All limits are TA = TJ = 25°C unless otherwise specified.
LMF100CCN
PARAMETER
UNIT
MIN
fCLK
Clock frequency
fCLK/f
Clock to center frequency ratio
deviation
LMF100CIWM
TEST CONDITIONS
TYP
5
MAX
MIN
15000
00
5
±0.2%
0
VPin12 = 5 V or 0
V, fCLK = 1 MHz
Tested
Limit (1)
TMIN to TMAX
Q Error (MAX)
(3)
Q
±1%
±1%
±0.5%
±5%
Tested
Limit (1)
TMIN to TMAX
Design
Limit (2)
TMIN to TMAX
±8%
±8%
0
HOBP
Bandpass gain at f0
fCLK = 1 MHz
0
±0.4
Tested
Limit (1)
TMIN to TMAX
Design
Limit (2)
TMIN to TMAX
DC Lowpass gain
R1 = R2 = 10 k,
fCLK = 250 kHz
DC Offset voltage (4)
fCLK = 250 kHz
TMIN to TMAX
Design
Limit (2)
TMIN to TMAX
Tested
Limit (1)
TMIN to TMAX
Design
Limit (2)
TMIN to TMAX
±5
±15
mV
±15
±20
±60
Tested Limit (1)
mV
TMIN to TMAX
Design Limit
(2)
fCLK = 250 kHz
±60
TMIN to TMAX
±60
±10
SA/B = V
–
Tested Limit
±10
TMIN to TMAX
±60
TMIN to TMAX
±60
±10
DC Offset voltage (4)
Crosstalk
(5)
Output noise (6)
Clock feedthrough (7)
(3)
(4)
(5)
(6)
(7)
fCLK = 250 kHz
mV
±50
(1)
Design Limit (2)
VOS3
±10
±25
Tested
Limit (1)
TMIN to TMAX
Design
Limit (2)
TMIN to TMAX
A Side to B Side or B Side to A Side
±30
–65
25
25
BP
250
250
LP
220
220
2
2
N
20 kHz Bandwidth
100:1 Mode
fCLK = 250 kHz 100:1 Mode
mV
±30
–65
fCLK = 250 kHz
dB
±0.2
±15
SA/B = V+
DC Offset voltage (4)
±0.2
0
±20
VOS2
dB
±0.2
Tested
Limit (1)
±5
VOS1
±0.5
±0.5
0
HOLP
Hz
±0.2%
±0.5%
Q = 10, Mode 1,
VPin12 = 5 V or 0
V,
fCLK = 1 MHz
MAX
1500000
±1%
Design
Limit (2)
DQ
TYP
dB
µV
mV
The accuracy of the Q value is a function of the center frequency (f0). This is illustrated in the curves under the heading Typical
Characteristics.
Vos1, Vos2, and Vos3 refer to the internal offsets as discussed in the Application Information.
Crosstalk between the internal filter sections is measured by applying a 1 VRMS 10-kHz signal to one bandpass filter section input and
grounding the input of the other bandpass filter section. The crosstalk is the ratio between the output of the grounded filter section and
the 1 VRMS input signal of the other section.
In 50:1 mode the output noise is 3 dB higher.
In 50:1 mode the clock feed through is 6 dB higher.
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Electrical Characteristics for V+ = +2.5 V and V− = −2.5 V (continued)
The following specifications apply for Mode 1, Q = 10 (R1 = R3 = 100 k, R2 = 10 k), V+ = +2.50 V and V− = −2.50 V unless
otherwise specified. All limits are TA = TJ = 25°C unless otherwise specified.
LMF100CCN
PARAMETER
UNIT
MIN
TYP
RL = 5 k
All Outputs
VOUT
LMF100CIWM
TEST CONDITIONS
Minimum output voltage swing
RL = 5 k (All
Outputs)
MAX
MIN
TYP
1.6
−2.2
MAX
1.6
−2.2
±1.5
Tested
Limit (1)
TMIN to TMAX
Design
Limit (2)
TMIN to TMAX
V
±1.4
±1.4
1.5
−2.1
RL = 3.5 k
All Outputs
1.5
−2.1
V
GB
W
Operational amplifier gain BW
product
5
5
MHz
SR
Operational amplifier slew rate
18
18
V/µs
Isc
(8)
Maximum output,
Short circuit current (8)
Source
All Outputs
10
10
mA
Sink
All Outputs
20
20
mA
The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then
shorting that output to the negative supply. The short circuit sink current is measured by forcing the output that is being tested to its
maximum negative voltage swing and then shorting that output to the positive supply. These are the worst case conditions.
6.7 Logic Input Characteristics
All limits apply to TA = TJ = 25°C unless otherwise specified.
LMF100CCN
PARAMETER
UNIT
MIN
V+ = +5 V, V− = −5 V,
TMIN to TMAX
TMIN to TMAX
TMIN to TMAX
VLSh = +5 V
TMIN to TMAX
V+ = +5 V, V− = −5 V,
TMIN to TMAX
VLSh = 0 V
TMIN to TMAX
V+ = +10 V, V− = 0 V,
TMIN to TMAX
VLSh = 0 V
(1)
(2)
8
0.8
V
2
V
0.8
V
2
TMIN to TMAX
Design Limit (2)
V
0.8
Tested Limit (1)
MAX Logical “0”
2
0.8
TMIN to TMAX
Design Limit (2)
V
2
Tested Limit (1)
MIN Logical “1”
2
2
TMIN to TMAX
Design Limit (2)
TTL Clock
Input Voltage
V
0.8
Tested Limit (1)
MAX Logical “0”
8
2
TMIN to TMAX
Design Limit (2)
V
2
Tested Limit (1)
MIN Logical “1”
–3
8
TMIN to TMAX
Design Limit (2)
V
2
Tested Limit (1)
MAX Logical “0”
3
−3
TMIN to TMAX
Design Limit (2)
MAX
8
Tested Limit (1)
V+ = +10 V, V− = 0 V,
TYP
3
TMIN to TMAX
Design Limit (2)
MIN Logical “1”
MIN
−3
Tested Limit (1)
VLSh = 0 V
CMOS Clock
Input Voltage
MAX
TMIN to TMAX
Design Limit (2)
MAX Logical “0”
TYP
3
Tested Limit (1)
MIN Logical “1”
LMF100CIWM
TEST CONDITIONS
TMIN to TMAX
0.8
Tested limits are specified to Texas Instruments AOQL (Average Outgoing Quality Level).
Design limits are specified to Texas Instruments AOQL (Average Outgoing Quality Level) but are not 100% tested.
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Logic Input Characteristics (continued)
All limits apply to TA = TJ = 25°C unless otherwise specified.
LMF100CCN
PARAMETER
UNIT
MIN
V+ = +2.5 V, V− = −2.5 V,
TMIN to TMAX
TMIN to TMAX
V+ = +5 V, V− = 0 V,
TMIN to TMAX
VLSh = +2.5 V
TMIN to TMAX
V+ = +5 V, V− = 0 V,
TMIN to TMAX
Design Limit (2)
1
V
2
V
0.8
V
2
TMIN to TMAX
VLSh = 0 V, VD+ = 0 V
V
0.8
Tested Limit (1)
MAX Logical “0”
4
1
TMIN to TMAX
Design Limit (2)
TTL Clock
Input Voltage
V
2
Tested Limit (1)
MIN Logical “1”
−1.5
4
TMIN to TMAX
Design Limit (2)
V
1
Tested Limit (1)
MAX Logical “0”
1.5
−1.5
TMIN to TMAX
Design Limit (2)
MAX
4
Tested Limit (1)
MIN Logical “1”
TYP
1.5
TMIN to TMAX
Design Limit (2)
MIN
−1.5
Tested Limit (1)
VLSh = 0 V
CMOS Clock
Input Voltage
MAX
TMIN to TMAX
Design Limit (2)
MAX Logical “0”
TYP
1.5
Tested Limit (1)
MIN Logical “1”
LMF100CIWM
TEST CONDITIONS
TMIN to TMAX
0.8
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6.8 Typical Characteristics
10
Figure 1. Power Supply Current vs Power Supply Voltage
Figure 2. Power Supply Current vs Temperature
Figure 3. Output Swing vs Supply Voltage
Figure 4. Positive Output Swing vs Temperature
Figure 5. Negative Output Swing vs Temperature
Figure 6. Positive Output Voltage Swing vs Load Resistance
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Typical Characteristics (continued)
Figure 7. Negative Output Voltage Swing vs Load
Resistance
Figure 8. fCLK/f0 Ratio vs Q
Figure 9. fCLK/f0 Ratio vs Q
Figure 10. fCLK/f0 Ratio vs fCLK
Figure 11. fCLK/f0 Ratio vs fCLK
Figure 12. fCLK/f0 Ratio vs fCLK
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Typical Characteristics (continued)
12
Figure 13. fCLK/f0 Ratio vs fCLK
Figure 14. fCLK/f0 Ratio vs Temperature
Figure 15. fCLK/f0 Ratio vs Temperature
Figure 16. Q Deviation vs Clock Frequency
Figure 17. Q Deviation vs Clock Frequency
Figure 18. Q Deviation vs Clock Frequency
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Typical Characteristics (continued)
Figure 19. Q Deviation vs Clock Frequency
Figure 20. Q Deviation vs Temperature
Figure 21. Q Deviation vs Temperature
Figure 22. Maximum f0 vs Q at Vs = ±7.5 V
Figure 23. Maximum f0 vs Q at Vs = ±5 V
Figure 24. Maximum f0 vs Q at Vs = ±2.5 V
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7 Parameter Measurement Information
7.1 Definition of Terms Graphics
Figure 25. Second-Order Bandpass Response Gain
Figure 26. Second-Order Bandpass Response
Phase
Figure 27. Second-Order Lowpass Response Gain
Figure 28. Second-Order Lowpass Response
Phase
Figure 29. Second-Order Highpass Response Gain
Figure 30. Second-Order Highpass Response
Phase
Figure 31. Second-Order Notch Response Gain
Figure 32. Second-Order Notch Response Phase
Figure 33. Second-Order Allpass Response Gain
Figure 34. Second-Order Allpass Response Phase
14
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Definition of Terms Graphics (continued)
Figure 35. Bandpass Response of Various Second-Order
Filters as a Function of Q.
Gains and Center Frequencies are Normalized to Unity
Gain
Figure 36. Lowpass Response of Various Second-Order
Filters as a Function of Q.
Gains and Center Frequencies are Normalized to Unity
Phase
Figure 37. Highpass Response of Various Second-Order
Filters as a Function of Q.
Gains and Center Frequencies are Normalized to Unity
Gain
Figure 38. Notch Response of Various Second-Order
Filters as a Function of Q.
Gains and Center Frequencies are Normalized to Unity
Gain
Figure 39. Allpass Response of Various Second-Order Filters as a Function of Q.
Gains and Center Frequencies are Normalized to Unity Gain
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8 Detailed Description
8.1 Overview
The LMF100 device contains two general-purpose, very high-performance switched capacitor filters that are costeffective and space-saving. It enables designers to implement all the classical filters up to fourth-order biquad
with one chip. This switched capacitor filters can be used in a broad range of industrial and consumer application
such as audio, communication, instrumentation, medical, telemetry, etc. It can be directly cascaded to implement
higher order filters,
8.2 Functional Block Diagram
8.3 Feature Description
The LMF100 is an all CMOS switched capacitor filter device that consists of two filters capable of wide supply
range from 4 V to 15 V. It features much higher performance than the pin-compatible MF10 device with operation
frequency to 100 kHz, which is 3X broader, and fo x Q range to 1.8 MHz which is 9X higher. Furthermore, it has
pins that also function to configure filter modes of operation, level shifting, clock to filter center frequency setting,
and power rail selections enabling flexibility and ease of programming.
8.4 Device Functional Modes
8.4.1 Modes of Operation
The LMF100 is a switched capacitor (sampled data) filter. To fully describe its transfer functions, a time domain
analysis is appropriate. Because this is cumbersome, and because the LMF100 closely approximates continuous
filters, the following discussion is based on the well-known frequency domain. Each LMF100 can produce two full
second-order functions. See Table 1 for a summary of the characteristics of the various modes.
16
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Device Functional Modes (continued)
8.4.1.1 MODE 1: Notch 1, Bandpass, Lowpass Outputs:
fnotch = f0 (See Figure 40)
fCLK
f
or CLK
100
50
= center frequency of the imaginary zero pair = f0
f0 = center frequency of the complex pole pair =
fnotch
HOLP
HOBP
(1)
(2)
R2
= Lowpass gain (as f ® 0) = R1
R3
= Bandpass gain (at f ® 0) = R1
(3)
(4)
-R2
f ®0
=
HON = Notch output gain as f ® f
R1
CLK / 2
(5)
f0
R3
=
= quality factor of the complex pole pair
BW R2
BW = the - 3 dB bandwidth of the bandpass output.
(6)
Circuit dynamics : HOBP1 = Q
(8)
HOBP
or HOBP = HOLP ´ Q = HON ´ Q
Q
HOLP(peak) @ Q ´ HOLP (for high Q' s)
(9)
Q=
(7)
HOLP =
(10)
8.4.1.2 MODE 1a: Noninverting BP, LP (See Figure 41)
f
f
f0 = CLK or CLK
100
50
(11)
(12)
HOLP = -1; HOLP(peak) @ Q ´ HOLP (for high Q' s)
HOBP1
HOBP2
(13)
R3
=R2
= 1(noninverting)
(14)
(15)
Circuit dynamics : HOBP1 = Q
(16)
Note: VIN should be driven from a low-impedance (
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