LMF100CIWM

LMF100 High Performance Dual Switched Capacitor Filter July 1999 LMF100 High Performance Dual Switched Capacitor Filter General Description The LMF100 consists of two independent general purpose high performance switched capacitor filters. With an external clock and 2 to 4 resistors, various second-order and first-order filtering functions can be realized by each filter block. Each block has 3 outputs. One output can be configured to perform either an allpass, highpass, or notch function. The other two outputs perform bandpass and lowpass functions. The center frequency of each filter stage is tuned by using an external clock or a combination of a clock and resistor ratio. Up to a 4th-order biquadratic function can be realized with a single LMF100. Higher order filters are implemented by simply cascading additional packages, and all the classical filters (such as Butterworth, Bessel, Elliptic, and Chebyshev) can be realized. The LMF100 is fabricated on National Semiconductor’s high performance analog silicon gate CMOS process, LMCMOS™. This allows for the production of a very low offset, high frequency filter building block. The LMF100 is pin-compatible with the industry standard MF10, but provides greatly improved performance. Features n Wide 4V to 15V power supply range n Operation up to 100 kHz n Low offset voltage: typically (50:1 or 100:1 mode): Vos1 = ± 5 mV Vos2 = ± 15 mV Vos3 = ± 15 mV n Low crosstalk −60 dB n Clock to center frequency ratio accuracy ± 0.2% typical n f0 x Q range up to 1.8 MHz n Pin-compatible with MF10 4th Order 100 kHz Butterworth Lowpass Filter DS005645-3 DS005645-2 Connection Diagram Surface Mount and Dual-In-Line Package DS005645-18 Top View Order Number LMF100CCN or LMF100CIWM See NS Package Number N20A or M20B LMCMOS™ is a trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS005645 www.national.com Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. (Note 14) Supply Voltage (V+ − V−) Voltage at Any Pin Input Current at Any Pin (Note 2) Package Input Current (Note 2) Power Dissipation (Note 3) Storage Temperature ESD Susceptability (Note 11) Soldering Information N Package: 10 sec. 16V V+ + 0.3V V− − 0.3V 5 mA 20 mA 500 mW 150˚C 2000V 260˚C J Package: 10 sec. 300˚C SO Package: Vapor Phase (60 sec.) 215˚C Infrared (15 sec.) 220˚C See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” (Appendix D) for other methods of soldering surface mount devices. Operating Ratings (Note 1) Temperature Range LMF100CCN LMF100CIWM Supply Voltage TMIN ≤ TA ≤ TMAX 0˚C ≤ TA ≤ +70˚C −40˚C ≤ TA ≤ +85˚C 4V ≤ V+ − V− ≤ 15V Electrical Characteristics The following specifications apply for Mode 1, Q = 10 (R1 = R3 = 100k, R2 = 10k), V+ = +5V and V− = −5V unless otherwise specified. Boldface limits apply for TMIN to TMAX; all other limits TA = TJ = 25˚C. LMF100CCN Symbol Parameter Conditions Typical (Note 8) 9 0.1 100 5.0 3.5 VPin12 = 5V or 0V fCLK = 1 MHz Q = 10, Mode 1 VPin12 = 5V or 0V fCLK = 1 MHz fCLK = 1 MHz R1 = R2 = 10k fCLK = 250 kHz VOS1 VOS2 VOS3 DC Offset Voltage (Note 5) DC Offset Voltage (Note 5) DC Offset Voltage (Note 5) Crosstalk (Note 6) Output Noise (Note 12) fCLK = 250 kHz fCLK = 250 kHz fCLK = 250 kHz A Side to B Side or B Side to A Side fCLK = 250 kHz 20 kHz Bandwidth 100:1 Mode Clock Feedthrough (Note 13) VOUT Minimum Output Voltage Swing N BP LP SA/B = V+ SA/B = V− Tested Limit (Note 9) 13 Design Limit (Note 10) 13 Typical (Note 8) 9 0.1 100 5.0 3.5 LMF100CIWM Tested Limit (Note 9) 13 Design Limit (Note 10) Units Is f0 fCLK fCLK/f0 Maximum Supply Current Center Frequency Range Clock Frequency Range MIN MAX MIN MAX fCLK = 250 kHz No Input Signal mA Hz kHz Hz MHz Clock to Center Frequency Ratio Deviation Q Error (MAX) (Note 4) ± 0.2 ± 0.5 ± 0.8 ±5 ± 0.8 ±6 ± 0.2 ± 0.5 ± 0.8 ±6 % % HOBP HOLP Bandpass Gain at f0 DC Lowpass Gain 0 0 ± 0.4 ± 0.2 ± 15 ± 80 ± 70 ± 40 ± 0.4 ± 0.2 ± 15 ± 80 ± 70 ± 60 0 0 ± 0.4 ± 0.2 ± 15 ± 80 ± 70 ± 60 dB dB mV mV mV mV dB ± 5.0 ± 30 ± 15 ± 15 −60 40 320 300 6 +4.0 −4.7 +3.9 −4.6 5 20 ± 5.0 ± 30 ± 15 ± 15 −60 40 320 300 6 µV mV fCLK = 250 kHz 100:1 Mode RL = 5k (All Outputs) RL = 3.5k (All Outputs) ± 3.8 ± 3.7 +4.0 −4.7 +3.9 −4.6 5 20 12 45 ± 3.7 V V MHz V/µs mA mA GBW SR Isc Op Amp Gain BW Product Op Amp Slew Rate Maximum Output Short Circuit Current (Note 7) Source Sink (All Outputs) 12 45 www.national.com 2 Electrical Characteristics (Continued) The following specifications apply for Mode 1, Q = 10 (R1 = R3 = 100k, R2 = 10k), V+ = +5V and V− = −5V unless otherwise specified. Boldface limits apply for TMIN to TMAX; all other limits TA = TJ = 25˚C. LMF100CCN Symbol Parameter Conditions Typical (Note 8) Tested Limit (Note 9) 10 Design Limit (Note 10) Typical (Note 8) LMF100CIWM Tested Limit (Note 9) 10 Design Limit (Note 10) Units IIN Input Current on Pins: 4, 5, 6, 9, 10, 11, 12, 16, 17 µA Electrical Characteristics The following specifications apply for Mode 1, Q = 10 (R1 = R3 = 100k, R2 = 10k), V+ = +2.50V and V− = −2.50V unless otherwise specified. Boldface limits apply for TMIN to TMAX; all other limits TA = TJ = 25˚C. LMF100CCN Symbol Parameter Conditions Typical (Note 8) Tested Limit (Note 9) 12 Design Limit (Note 10) 12 Typical (Note 8) LMF100CIWM Tested Limit (Note 9) 12 Design Limit (Note 10) Units Is f0 fCLK fCLK/f0 Maximum Supply Current Center Frequency Range Clock Frequency Range Clock to Center Frequency Ratio Deviation Q Error (MAX) (Note 4) MIN MAX MIN MAX fCLK = 250 kHz No Input Signal 8 0.1 50 5.0 1.5 8 0.1 50 5.0 1.5 mA Hz kHz Hz MHz VPin12 = 2.5V or 0V fCLK = 1 MHz Q = 10, Mode 1 VPin12 = 5V or 0V fCLK = 1 MHz fCLK = 1 MHz R1 = R2 = 10k fCLK = 250 kHz fCLK = 250 kHz fCLK = 250 kHz fCLK = 250 kHz A Side to B Side or B Side to A Side fCLK = 250 kHz 100:1 Mode N LP SA/B = V+ SA/B = V− ± 0.2 ±1 ±1 ± 0.2 ±1 % ± 0.5 0 0 ±5 ± 0.4 ± 0.2 ± 15 ± 60 ± 50 ± 25 ±8 ± 0.5 ± 0.2 ± 15 ± 60 ± 60 ± 30 ± 0.5 0 0 ±8 ± 0.5 ± 0.2 ± 15 ± 60 ± 60 ± 30 % dB dB mV mV mV mV dB HOBP HOLP VOS1 VOS2 VOS3 Bandpass Gain at f0 DC Lowpass Gain DC Offset Voltage (Note 5) DC Offset Voltage (Note 5) DC Offset Voltage (Note 5) Crosstalk (Note 6) Output Noise (Note 12) ± 5.0 ± 20 ± 10 ± 10 −65 25 250 220 2 +1.6 −2.2 +1.5 −2.1 5 18 ± 5.0 ± 20 ± 10 ± 10 −65 25 250 220 2 20 kHz Bandwidth BP Clock Feedthrough (Note 13) VOUT Minimum Output Voltage Swing fCLK = 250 kHz 100:1 Mode RL = 5k (All Outputs) RL = 3.5k (All outputs) GBW SR Isc Op Amp Gain BW Product Op Amp Slew Rate Maximum Output Short Circuit Current (Note 7) Source Sink (All Outputs) µV mV ± 1.5 ± 1.4 +1.6 −2.2 +1.5 −2.1 5 18 10 20 ± 1.4 V V MHz V/µs mA mA 10 20 3 www.national.com Logic Input Characteristics Boldface limits apply for TMIN to TMAX; all other limits TA = TJ = 25˚C. LMF100CCN Parameter Conditions Typical (Note 8) Tested Limit (Note 9) CMOS Clock Input Voltage MIN Logical “1” MAX Logical “0” MIN Logical “1” MAX Logical “0” TTL Clock Input Voltage MIN Logical “1” MAX Logical “0” MIN Logical “1” MAX Logical “0” CMOS Clock Input Voltage MIN Logical “1” MAX Logical “0” MIN Logical “1” MAX Logical “0” TTL Clock Input Voltage MIN Logical “1” MAX Logical “0” V+ = +5V, V− = −5V, VLSh = 0V V+ = +10V, V− = 0V, VLSh = +5V V+ = +5V, V− = −5V, VLSh = 0V V+ = +10V, V− = 0V, VLSh = 0V V+ = +2.5V, V− = −2.5V, VLSh = 0V V+ = +5V, V− = 0V, VLSh = +2.5V V+ = +5V, V− = 0V, VLSh = 0V, VD+ = 0V +3.0 −3.0 +8.0 +2.0 +2.0 +0.8 +2.0 +0.8 +1.5 −1.5 +4.0 +1.0 +2.0 +0.8 Design Limit (Note 10) +3.0 −3.0 +8.0 +2.0 +2.0 +0.8 +2.0 +0.8 +1.5 −1.5 +4.0 +1.0 +2.0 +0.8 Typical (Note 8) LMF100CIWM Tested Limit (Note 9) +3.0 −3.0 +8.0 +2.0 +2.0 +0.8 +2.0 +0.8 +1.5 −1.5 +4.0 +1.0 +2.0 +0.8 Design Limit (Note 10) V V V V V V V V V V V V V V Units Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional. These ratings do not guarantee specific performance limits, however. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < V− or VIN > V+) the absolute value of current at that pin should be limited to 5 mA or less. The sum of the currents at all pins that are driven beyond the power supply voltages should not exceed 20 mA. Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD = (TJMAX − TA)/θJA or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, TJMAX = 125˚C, and the typical junction-to-ambient thermal resistance of the LMF100CIN when board mounted is 55˚C/W. For the LMF100CIWM this number is 66˚C/W. Note 4: The accuracy of the Q value is a function of the center frequency (f0). This is illustrated in the curves under the heading “Typical Peformance Characteristics”. Note 5: Vos1, Vos2, and Vos3 refer to the internal offsets as discussed in the Applications Information section 3.4. Note 6: Crosstalk between the internal filter sections is measured by applying a 1 VRMS 10 kHz signal to one bandpass filter section input and grounding the input of the other bandpass filter section. The crosstalk is the ratio between the output of the grounded filter section and the 1 VRMS input signal of the other section. Note 7: The short circuit source current is measured by forcing the output that is being tested to its maximum positive voltage swing and then shorting that output to the negative supply. The short circuit sink current is measured by forcing the output that is being tested to its maximum negative voltage swing and then shorting that output to the positive supply. These are the worst case conditions. Note 8: Typicals are at 25˚C and represent most likely parametric norm. Note 9: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). Note 10: Design limits are guaranteed to National’s AOQL (Average Outgoing Quality Level) but are not 100% tested. Note 11: Human body model, 100 pF discharged through a 1.5 kΩ resistor. Note 12: In 50:1 mode the output noise is 3 dB higher. Note 13: In 50:1 mode the clock feedthrough is 6 dB higher. Note 14: A military RETS specification is available upon request. www.national.com 4 Typical Performance Characteristics Power Supply Current vs Power Supply Voltage Power Supply Current vs Temperature Output Swing vs Supply Voltage DS005645-40 DS005645-41 DS005645-42 Positive Output Swing vs Temperature Negative Output Swing vs Temperature Positive Output Voltage Swing vs Load Resistance DS005645-43 DS005645-44 DS005645-45 Negative Output Voltage Swing vs Load Resistance fCLK/f0 Ratio vs Q fCLK/f0 Ratio vs Q DS005645-47 DS005645-46 DS005645-48 fCLK/f0 Ratio vs fCLK fCLK/f0 Ratio vs fCLK fCLK/f0 Ratio vs fCLK DS005645-49 DS005645-50 DS005645-51 5 www.national.com Typical Performance Characteristics fCLK/f0 Ratio vs fCLK (Continued) fCLK/f0 Ratio vs Temperature fCLK/f0 Ratio vs Temperature DS005645-52 DS005645-53 DS005645-54 Q Deviation vs Clock Frequency Q Deviation vs Clock Frequency Q Deviation vs Clock Frequency DS005645-55 DS005645-56 DS005645-57 Q Deviation vs Clock Frequency Q Deviation vs Temperature Q Deviation vs Temperature DS005645-59 DS005645-58 DS005645-60 www.national.com 6 Typical Performance Characteristics Maximum f0 vs Q at Vs = ± 7.5V (Continued) Maximum f0 vs Q at Vs = ± 2.5V Maximum f0 vs Q at Vs = ± 5.0V DS005645-61 DS005645-62 DS005645-63 LMF100 System Block Diagram DS005645-1 7 www.national.com Pin Descriptions LP(1,20), BP(2,19), N/AP/HP(3,18) The second order lowpass, bandpass and notch/allpass/highpass outputs. These outputs can typically swing to within 1V of each supply when driving a 5 kΩ load. For optimum performance, capacitive loading on these outputs should be minimized. For signal frequencies above 15 kHz the capacitance loading should be kept below 30 pF. The inverting input of the summing opamp of each filter. These are high impedance inputs. The non-inverting input is internally tied to AGND so the opamp can be used only as an inverting amplifier. S1 is a signal input pin used in modes 1b, 4, and 5. The input impedance is 1/fCLK x 1 pF. The pin should be driven with a source impedance of less than 1 kΩ. If S1 is not driven with a signal it should be tied to AGND (mid-supply). This pin activates a switch that connects one of the inputs of each filter’s second summer either to AGND (SA/B tied to V−) or to the lowpass (LP) output (SA/B tied to V+). This offers the flexibility needed for configuring the filter in its various modes of operation. This is both the analog and digital positive supply. This pin needs to be tied to V+ except when the device is to operate on a single 5V supply and a TTL level clock is applied. For 5V, TTL operation, VD+ should be tied to ground (0V). Analog and digital negative supplies. VA−and VD− should be derived from the same source. They have been brought out separately so they can be bypassed by separate capacitors, if desired. They can also be tied together externally and bypassed with a single capacitor. LSh(9) Level shift pin. This is used to accommodate various clock levels with dual or single supply operation. With dual ± 5V supplies and CMOS ( ± 5V) or TTL (0V–5V) clock levels, LSh should be tied to system ground. For 0V–10V single supply operation the AGND pin should be biased at +5V and the LSh pin should be tied to the system ground for TTL clock levels. LSh should be biased at +5V for ± 5V CMOS clock levels. The LSh pin is tied to system ground for ± 2.5V operation. For single 5V operation the LSh and VD+ pins are tied to system ground for TTL clock levels. INV(4,17) CLK(10,11) S1(5,16) SA/B(6) Clock inputs for the two switched capacitor filter sections. Unipolar or bipolar clock levels may be applied to the CLK inputs according to the programming voltage applied to the LSh pin. The duty cycle of the clock should be close to 50%, especially when clock frequencies above 200 kHz are used. This allows the maximum time for the internal opamps to settle, which yields optimum filter performance. By tying this pin to V+ a 50:1 clock to filter center frequency ratio is obtained. Tying this pin at mid-supply (i.e., system ground with dual supplies) or to V− allows the filter to operate at a 100:1 clock to center frequency ratio. This is the analog ground pin. This pin should be connected to the system ground for dual supply operation or biased to mid-supply for single supply operation. For a further discussion of mid-supply biasing techniques see the Applications Information (Section 3.2). For optimum filter performance a “clean” ground must be provided. 50/100(12) (Note 15) VA+(7) (Note 15) VD+(8) (Note 15) AGND(15) VA−(14), VD−(13) Note 15: This device is pin-for-pin compatible with the MF10 except for the following changes: 1. Unlike the MF10, the LMF100 has a single positive supply pin (VA+). 2. On the LMF100 VD+ is a control pin and is not the digital positive supply as on the MF10. 3. Unlike the MF10, the LMF100 does not support the current limiting mode. When the 50/100 pin is tied to V− the LMF100 will remain in the 100:1 mode. www.national.com 8 1.0 Definitions of Terms fCLK: the frequency of the external clock signal applied to pin 10 or 11. f0: center frequency of the second order function complex pole pair. f0 is measured at the bandpass outputs of the LMF100, and is the frequency of maximum bandpass gain. (Figure 1). fnotch: the frequency of minimum (ideally zero) gain at the notch outputs. fz: the center frequency of the second order complex zero pair, if any. If fz is different from f0 and if Qz is high, it can be observed as the frequency of a notch at the allpass output. (Figure 13). Q: “quality factor” of the 2nd order filter. Q is measured at the bandpass outputs of the LMF100 and is equal to f0 divided by the −3 dB bandwidth of the 2nd order bandpass filter (Figure 1). The value of Q determines the shape of the 2nd order filter responses as shown in Figure 6. Qz: the quality factor of the second order complex zero pair, if any. QZ is related to the allpass characteristic, which is written: where QZ = Q for an all-pass response. HOBP: the gain (in V/V) of the bandpass output at f = f0. HOLP: the gain (in V/V) of the lowpass output as f → 0 Hz (Figure 2). HOHP: the gain (in V/V) of the highpass output as f → fCLK/2 (Figure 3). HON: the gain (in V/V) of the notch output as f → 0 Hz and as f → fCLK/2, when the notch filter has equal gain above and below the center frequency (Figure 4). When the low-frequency gain differs from the high-frequency gain, as in modes 2 and 3a (Figure 10 and Figure 12), the two quantities below are used in place of HON. HON1: the gain (in V/V) of the notch output as f → 0 Hz. HON2: the gain (in V/V) of the notch output as f → fCLK/2. DS005645-19 DS005645-20 (a) (b) FIGURE 1. 2nd-Order Bandpass Response 9 www.national.com 1.0 Definitions of Terms (Continued) DS005645-21 DS005645-22 (a) (b) FIGURE 2. 2nd-Order Low-Pass Response DS005645-23 DS005645-24 (a) (b) FIGURE 3. 2nd-Order High-Pass Response www.national.com 10 1.0 Definitions of Terms (Continued) DS005645-25 DS005645-26 (a) (b) FIGURE 4. 2nd-Order Notch Response DS005645-27 DS005645-28 (a) (b) FIGURE 5. 2nd-Order All-Pass Response 11 www.national.com 1.0 Definitions of Terms (a) Bandpass (Continued) (b) Low Pass (c) High-Pass DS005645-64 DS005645-65 DS005645-66 (d) Notch (e) All-Pass DS005645-67 DS005645-68 FIGURE 6. Response of various 2nd-order filters as a function of Q. Gains and center frequencies are normalized to unity. www.national.com 12 2.0 Modes of Operation The LMF100 is a switched capacitor (sampled data) filter. To fully describe its transfer functions, a time domain analysis is appropriate. Since this is cumbersome, and since the LMF100 closely approximates continuous filters, the following discussion is based on the well-known frequency domain. Each LMF100 can produce two full 2nd order functions. See Table 1 for a summary of the characteristics of the various modes. MODE 1: Notch 1, Bandpass, Lowpass Outputs: fnotch = f0 (See Figure 7) MODE 1a: Non-Inverting BP, LP (See Figure 8) Note: VIN should be driven from a low impedance ( < 1 kΩ) source. DS005645-11 FIGURE 7. MODE 1 DS005645-4 FIGURE 8. MODE 1a 13 www.national.com 2.0 Modes of Operation (Continued) MODE 1b: Notch 1, Bandpass, Lowpass Outputs: fnotch = f0 (See Figure 9) MODE 2: Notch 2, Bandpass, Lowpass: fnotch < f0 (See Figure 10) DS005645-14 FIGURE 9. MODE 1b DS005645-36 FIGURE 10. MODE 2 www.national.com 14 2.0 Modes of Operation (See Figure 11) (Continued) MODE 3: Highpass, Bandpass, Lowpass Outputs MODE 3a: HP, BP, LP and Notch with External Op Amp (See Figure 12) DS005645-5 *In Mode 3, the feedback loop is closed around the input summing amplifier; the finite GBW product of this op amp causes a slight Q enhancement. If this is a problem, connect a small capacitor (10 pF−100 pF) across R4 to provide some phase lead. FIGURE 11. MODE 3 15 www.national.com 2.0 Modes of Operation (Continued) DS005645-10 FIGURE 12. MODE 3a MODE 4: Allpass, Bandpass, Lowpass Outputs (See Figure 13) MODE 5: Numerator Complex Zeros, BP, LP (See Figure 14) *Due to the sampled data nature of the filter, a slight mismatch of fz and f0 occurs causing a 0.4 dB peaking around f0 of the allpass filter amplitude response (which theoretically should be a straight line). If this is unacceptable, Mode 5 is recommended. www.national.com 16 2.0 Modes of Operation (Continued) DS005645-6 FIGURE 13. MODE 4 DS005645-15 FIGURE 14. MODE 5 MODE 6a: Single Pole, HP, LP Filter (See Figure 15) DS005645-16 FIGURE 15. MODE 6a 17 www.national.com 2.0 Modes of Operation (Continued) DS005645-7 FIGURE 16. MODE 6b MODE 6b: Single Pole LP Filter (Inverting and NonInverting) (See Figure 16) MODE 6c: Single Pole, AP, LP Filter (See Figure 17) DS005645-17 FIGURE 17. MODE 6c www.national.com 18 2.0 Modes of Operation (Continued) DS005645-37 Equivalent Circuit DS005645-38 FIGURE 18. MODE 7 MODE 7: Summing Integrator (See Figure 18) 19 www.national.com 2.0 Modes of Operation (Continued) TABLE 1. Summary of Modes. Realizable filter types (e.g. low-pass) denoted by asterisks. Unless otherwise noted, gains of various filter outputs are inverting and adjustable by resistor ratios. Mode 1 1a 1b BP * LP * HP N * AP Number of Resistors 3 2 Adjustable fCLK/f0 No Notes (2) HOBP1 = −Q HOBP2 = + 1 * May need input buffer. HOLP = + 1 * * No No Yes (above Poor dynamics for high Q. Useful for high frequency applications. 3 2 * * * 3 fCLK/50 or fCLK/100) Universal State- 3 * * * 4 Yes Variable Filter. Best general-purpose mode. As above, but also 3a * * * * 7 Yes includes resistortuneable notch. Gives Allpass response with HOAP = − 1 and HOLP = −2. Gives flatter allpass response than above if R1 = R2 = 0.02R4. Single pole. Single pole. 4 * * * 3 No 5 6a 6b * * * * * 4 3 2 Yes Yes Yes (2) HOLP1 = + 1 6c 7 * * 3 2 No Yes Single pole. Summing integrator with adjustable time constant. 3.0 Applications Information The LMF100 is a general purpose dual second-order state variable filter whose center frequency is proportional to the frequency of the square wave applied to the clock input (fCLK). The various clocking options are summarized in the following table. Clocking Options Power Supply −5V and +5V −5V and +5V 0V and 10V 0V and 10V −2.5V and +2.5V 0V and 5V Clock Levels TTL (0V to +5V) CMOS (−5V to +5V) TTL (0V to 5V) CMOS (0V to +10V) CMOS (−2.5V to +2.5V) TTL (0V to +5V) 0V 0V LSh 0V 0V 0V +5V 0V VD+ +5V +5V +10V +10V +2.5V Power Supply 0V and 5V Clock Levels CMOS (0V to +5V) LSh +2.5V VD+ +5V By connecting pin 12 to the appropriate dc voltage, the filter center frequency, f0, can be made equal to either fCLK/100 or fCLK/50. f0 can be very accurately set (within ± 0.6%) by using a crystal clock oscillator, or can be easily varied over a wide frequency range by adjusting the clock frequency. If desired, the fCLK/f0 ratio can be altered by external resistors as in Figures 10, 11, 12, 13, 14, 15 and Figure 16. This is useful when high-order filters (greater than two) are to be realized by cascading the second-order sections. This allows each stage to be stagger tuned while using only one clock. The filter Q and gain are set by external resistor ratios. All of the five second-order filter types can be built using either section of the LMF100. These are illustrated in Figures 1, 2, 3, 4 and Figure 5 along with their transfer functions and some related equations. Figure 6 shows the effect of Q on the shapes of these curves. www.national.com 20 3.0 Applications Information (Continued) 3.1 DESIGN EXAMPLE In order to design a filter using the LMF100, we must define the necessary values of three parameters for each second-order section: f0, the filter section’s center frequency; H0, the passband gain; and the filter’s Q. These are determined by the characteristics required of the filter being designed. As an example, let’s assume that a system requires a fourth-order Chebyshev low-pass filter with 1 dB ripple, unity gain at dc, and 1000 Hz cutoff frequency. As the system order is four, it is realizable using both second-order sections of an LMF100. Many filter design texts (and National’s Switched Capacitor Filter Handbook) include tables that list the characteristics (f0 and Q) of each of the second-order filter sections needed to synthesize a given higher-order filter. For the Chebyshev filter defined above, such a table yields the following characteristics: f0A = 529 Hz QA = 0.785 QB = 3.559 f0B = 993 Hz For unity gain at dc, we also specify: H0A = 1 H0B = 1 The desired clock-to-cutoff-frequency ratio for the overall filter of this example is 100 and a 100 kHz clock signal is available. Note that the required center frequencies for the two second-order sections will not be obtainable with clock-to-center-frequency ratios of 50 or 100. It will be necessary to adjust externally. From Table 1, we see that Mode 3 can be used to produce a low-pass filter with resistor-adjustable center frequency. In most filter designs involving multiple second-order stages, it is best to place the stages with lower Q values ahead of stages with higher Q, especially when the higher Q is greater than 0.707. This is due to the higher relative gain at the center frequency of a higher-Q stage. Placing a stage with lower Q ahead of a higher-Q stage will provide some attenuation at the center frequency and thus help avoid clipping of signals near this frequency. For this example, stage A has the lower Q (0.785) so it will be placed ahead of the other stage. For the first section, we begin the design by choosing a convenient value for the input resistance: R1A = 20k. The absolute value of the passband gain HOLPA is made equal to 1 by choosing R4A such that: R4A = −HOLPAR1A = R1A = 20k. If the 50/100/CL pin is connected to mid-supply for nominal 100:1 clock-to-center-frequency ratio, we find R2A by: The resistors for the second section are found in a similar fashion: The complete circuit is shown in Figure 19 for split ± 5V power supplies. Supply bypass capacitors are highly recommended. 21 www.national.com 3.0 Applications Information (Continued) DS005645-30 FIGURE 19. Fourth-order Chebyshev low-pass filter from example in 3.1. ± 5V power supply. 0V–5V TTL or ± 5V CMOS logic levels. DS005645-31 FIGURE 20. Fourth-order Chebyshev low-pass filter from example in 3.1. Single +10V power supply. 0V–5V TTL logic levels. Input signals should be referred to half-supply or applied through a coupling capacitor. www.national.com 22 3.0 Applications Information (Continued) DS005645-32 DS005645-33 (a) Resistive Divider with Decoupling Capacitor (b) Voltage Regulator DS005645-34 (c) Operational Amplifier with Divider puts are not being directly used. Accompanying Figures 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 and Figure 17 are equations labeled “circuit dynamics”, which relate the Q and the gains at the various outputs. These should be consulted to determine peak circuit gains and maximum allowable signals for a given application. 3.4 OFFSET VOLTAGE The LMF100’s switched capacitor integrators have a slightly higher input offset voltage than found in a typical continuous time active filter integrator. Because of National’s new LMCMOS process and new design techniques the internal offsets have been minimized, compared to the industry standard MF10. Figure 22 shows an equivalent circuit of the LMF100 from which the output dc offsets can be calculated. Typical values for these offsets with SA/B tied to V+ are: VOS1 = opamp offset = ± 5 mV VOS2 = ± 30 mV at 50:1 or 100:1 VOS3 = ± 15 mV at 50:1 or 100:1 When SA/B is tied to V−, VOS2 will approximately halve. The dc offset at the BP output is equal to the input offset of the lowpass integrator (VOS3). The offsets at the other outputs depend on the mode of operation and the resistor ratios, as described in the following expressions. Mode 1 and Mode 4 FIGURE 21. Three Ways of Generating V+/2 for Single-Supply Operation 3.2 SINGLE SUPPLY OPERATION The LMF100 can also operate with a single-ended power supply. Figure 20 shows the example filter with a single-ended power supply. VA+ and VD+ are again connected to the positive power supply (4 to 15 volts), and VA− and VD− are connected to ground. The AGND pin must be tied to V+/2 for single supply operation. This half-supply point should be very “clean”, as any noise appearing on it will be treated as an input to the filter. It can be derived from the supply voltage with a pair of resistors and a bypass capacitor (Figure 21a), or a low-impedance half-supply voltage can be made using a three-terminal voltage regulator or an operational amplifier (Figure 21b and Figure 21c). The passive resistor divider with a bypass capacitor is sufficient for many applications, provided that the time constant is long enough to reject any power supply noise. It is also important that the half-supply reference present a low impedance to the clock frequency, so at very low clock frequencies the regulator or op-amp approaches may be preferable because they will require smaller capacitors to filter the clock frequency. The main power supply voltage should be clean (preferably regulated) and bypassed with 0.1 µF. 3.3 DYNAMIC CONSIDERATIONS The maximum signal handling capability of the LMF100, like that of any active filter, is limited by the power supply voltages used. The amplifiers in the LMF100 are able to swing to within about 1 volt of the supplies, so the input signals must be kept small enough that none of the outputs will exceed these limits. If the LMF100 is operating on ± 5 volts, for example, the outputs will clip at about 8Vp-p. The maximum input voltage multiplied by the filter gain should therefore be less than 8Vp-p. Note that if the filter Q is high, the gain at the lowpass or highpass outputs will be much greater than the nominal filter gain (Figure 6). As an example, a lowpass filter with a Q of 10 will have a 20 dB peak in its amplitude response at f0. If the nominal gain of the filter (HOLP) is equal to 1, the gain at f0 will be 10. The maximum input signal at f0 must therefore be less than 800 mVp-p when the circuit is operated on ± 5 volt supplies. Also note that one output can have a reasonable small voltage on it while another is saturated. This is most likely for a circuit such as the notch in Mode 1 (Figure 7). The notch output will be very small at f0, so it might appear safe to apply a large signal to the input. However, the bandpass will have its maximum gain at f0 and can clip if overdriven. If one output clips, the performance at the other outputs will be degraded, so avoid overdriving any filter section, even ones whose out23 Mode 1a www.national.com 3.0 Applications Information (Continued) Mode 1b Mode 3 Mode 2 and Mode 5 Mode 6a and 6c Mode 6b DS005645-12 FIGURE 22. Offset Voltage Sources In many applications, the outputs are ac coupled and dc offsets are not bothersome unless large signals are applied to the filter input. However, larger offset voltages will cause clipping to occur at lower ac signal levels, and clipping at any of the outputs will cause gain nonlinearities and will change f0 and Q. When operating in Mode 3, offsets can become excessively large if R2 and R4 are used to make fCLK/f0 significantly higher than the nominal value, especially if Q is also high. For example, Figure 23 shows a second-order 60 Hz notch filter. This circuit yields a notch with about 40 dB of attenuation at 60 Hz. A notch is formed by subtracting the bandpass output of a mode 3 configuration from the input using the unused side B opamp. The Q is 10 and the gain is 1 V/V in the passband. However, fCLK/f0 = 1000 to allow for a wide input spectrum. This means that for pin 12 tied to ground (100:1 mode), R4/R2 = 100. The offset voltage at the lowpass output (LP) will be about 3V. However, this is an extreme case and the resistor ratio is usually much smaller. Where necessary, the offset voltage can be adjusted by using the circuit of Figure 24. This allows adjustment of VOS1, which will have varying effects on the different outputs as described in the above equations. Some outputs cannot be adjusted this way in some modes, however (VOS(BP) in modes 1a and 3, for example). www.national.com 24 3.0 Applications Information (Continued) DS005645-39 R1 = 100 kΩ R2 = 1 kΩ R3 = 100 kΩ R4 = 100 kΩ Rg = 10 kΩ Rl = 10 kΩ Rh = 10 kΩ FIGURE 23. Second-Order Notch Filter DS005645-13 FIGURE 24. Method for Trimming VOS 3.5 SAMPLED DATA SYSTEM CONSIDERATIONS The LMF100 is a sampled data filter, and as such, differs in many ways from conventional continuous-time filters. An important characteristic of sampled-data systems is their effect on signals at frequencies greater than one-half the sampling frequency. (The LMF100’s sampling frequency is the same as its clock frequency.) If a signal with a frequency greater than one-half the sampling frequency is applied to the input of a sampled data system, it will be “reflected” to a frequency less than one-half the sampling frequency. Thus, an input signal whose frequency is fs/2 + 100 Hz will cause the system to respond as though the input frequency was fs/2 − 100 Hz. This phenomenon is known as “aliasing”, and can be reduced or eliminated by limiting the input signal 25 spectrum to less than fs/2. This may in some cases require the use of a bandwidth-limiting filter ahead of the LMF100 to limit the input spectrum. However, since the clock frequency is much higher than the center frequency, this will often not be necessary. Another characteristic of sampled-data circuits is that the output signal changes amplitude once every sampling period, resulting in “steps” in the output voltage which occur at the clock rate (Figure 25). If necessary, these can be “smoothed” with a simple R-C low-pass filter at the LMF100 output. The ratio of fCLK to fc (normally either 50:1 or 100:1) will also affect performance. A ratio of 100:1 will reduce any aliasing problems and is usually recommended for wide-band input www.national.com 3.0 Applications Information (Continued) signals. In noise-sensitive applications, a ratio of 100:1 will result in 3 dB lower output noise for the same filter configuration. The accuracy of the fCLK/f0 ratio is dependent on the value of Q. This is illustrated in the curves under the heading “Typical Performance Characteristics”. As Q is changed, the true value of the ratio changes as well. Unless the Q is low, the error in fCLK/f0 will be small. If the error is too large for a specific application, use a mode that allows adjustment of the ratio with external resistors. DS005645-35 FIGURE 25. The Sampled-Data Output Waveform www.national.com 26 Physical Dimensions inches (millimeters) unless otherwise noted Small Outline Package Order Number LMF100CIWM NS Package Number M20B Molded Dual-In-Line Package (N) Order Number LMF100CCN NS Package Number N20A 27 www.national.com LMF100 High Performance Dual Switched Capacitor Filter Notes LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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