LMX2581ESQE/NOPB

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents LMX2581E SNAS665 – MAY 2015 LMX2581E Wideband Frequency Synthesizer with Integrated VCO 1 Features 3 Description • • • • • • • The LMX2581E is a low-noise wideband frequency synthesizer that integrates a delta-sigma fractional N PLL, multiple core VCO, programmable output divider, and two differential output buffers. The VCO frequency range is from 1880 to 3800 MHz and can be sent directly to the output buffers or divided down by even values from 2 to 38. Each buffer is capable of output power from –3 to +12 dBm at 2700 MHz. Integrated low-noise LDOs are used for superior noise immunity and consistent performance. 1 • • • • • • • • • • Output Frequency from 50 to 3800 MHz Input Clock Frequency up to 900 MHz Phase Detector Frequency up to 200 MHz Supports Fractional and Integer Modes –229 dBc/Hz Normalized PLL Phase Noise –120.8 dBc/Hz Normalized PLL 1/f Noise –137 dBc/Hz VCO Phase Noise at 1 MHz offset for a 2.5 GHz Carrier 100 fs RMS Jitter in Integer Mode Programmable Fractional Modulator Order Programmable Fractional Denominator Programmable Output Power up to 12 dBm Programmable 32 Level Charge Pump Current Programmable Option to Use an External VCO Digital Lock Detect 3-Wire Serial Interface and Readback Single Supply Voltage from 3.15 V to 3.45 V Supports Logic Levels down to 1.6 V 2 Applications • • • • Wireless Infrastructure (UMTS, LTE, WiMax, Multi-Standard Base Stations) Broadband Wireless Test and Measurement Clock Generation This synthesizer is a highly programmable device and it enables the user to optimize its performance. In fractional mode, the denominator and the modulator order are programmable and can be configured with dithering as well. The user also has the ability to directly specify a VCO core or entirely bypass the internal VCO. Finally, many convenient features are included such as power down, Fastlock, auto mute, and lock detection. All registers can be programmed through a simple 3-wire interface and a read back feature is also available. The LMX2581E operates on a single 3.3 V supply and comes in a 32 pin 5.0 mm × 5.0 mm WQFN package. Device Information(1) PART NUMBER LMX2581E PACKAGE WQFN (32) DAP BODY SIZE (NOM) 5.00 mm × 5.00 mm (1) For all available packages, see the orderable addendum at the end of the datasheet. 4 Simplified Schematic Vtune Multiple Core VCO RFin MUX Fractional N Divider Vcc I Charge Pump CPout LD RFoutA RFoutB Vcc OSCin MUX Output Divider MUXout MUX 2X MUX R Divider DATA Serial Interface Control CLK LE CE 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMX2581E SNAS665 – MAY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified Schematic............................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 1 2 3 5 7.1 7.2 7.3 7.4 7.5 7.6 7.7 5 5 5 5 6 8 9 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics........................................... Timing Requirements, MICROWIRE Timing............. Typical Characteristics .............................................. 8.6 Register Maps ......................................................... 28 9 9.1 Application Information............................................ 42 9.2 Typical Applications ................................................ 42 9.3 Do's and Don'ts ....................................................... 46 10 Power Supply Recommendations ..................... 46 10.1 Supply Recommendations .................................... 46 10.2 Regulator Output Pins........................................... 47 11 Layout................................................................... 48 11.1 Layout Guidelines ................................................. 48 11.2 Layout Example .................................................... 48 12 Device and Documentation Support ................. 49 12.1 12.2 12.3 12.4 12.5 12.6 Detailed Description ............................................ 11 8.1 8.2 8.3 8.4 8.5 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ Programming........................................................... Application and Implementation ........................ 42 11 11 12 25 26 Device Support .................................................... Documentation Support ....................................... Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 49 49 49 49 49 49 13 Mechanical, Packaging, and Orderable Information ........................................................... 49 5 Revision History 2 DATE REVISION NOTES July 2015 * Initial release. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMX2581E LMX2581E www.ti.com SNAS665 – MAY 2015 6 Pin Configuration and Functions VccFRAC GND MUXout OSCin VccDIG GND BUFEN LD 32 31 30 29 28 27 26 25 DAP Package 32-Pin WQFN with Thermal Pad Top View CLK 1 24 VregVCO DATA 2 23 VbiasCOMP LE 3 22 VrefVCO CE 4 Top Down View 21 GND 0 (DAP) 13 14 15 16 RFoutB+ RFoutB- VccBUF VccVCO 12 GND 17 RFoutA- 18 8 RFoutA+ 7 GND 11 CPout Fin VbiasVCO 9 Vtune 19 10 20 6 GND 5 VccPLL FLout VccCP Pin Functions PIN TYPE DESCRIPTION NUMBER NAME 0 DAP GND The DAP should be grounded. 1 CLK Input MICROWIRE Clock Input. High Impedance CMOS input. 2 DATA Input MICROWIRE Data. High Impedance CMOS input. 3 LE Input MICROWIRE Latch Enable. High Impedance CMOS input. 4 CE Input Chip Enable Pin. 5 FLout Output Fastlock Output. This can switch in an external resistor to the loop filter during locking to improve lock time. 6 VccCP Supply Charge Pump Supply. 7 CPout Output Charge Pump Output. 8 GND GND Ground for the Charge Pump. Ground for the N and R divider. 9 GND GND 10 VccPLL Supply 11 Fin Input 12 RFoutA+ Output Differential divided output. For single-ended operation, terminate the complimentary side with a load equivalent to the load at this Pin. 13 RFoutA- Output Differential divided output. For single-ended operation, terminate the complimentary side with a load equivalent to the load at this pin. 14 RFoutB+ Output Differential divided output. For single-ended operation, terminate the complimentary side with a load equivalent to the load at this pin. 15 RFoutB- Output Differential divided output. For single-ended operation, terminate the complimentary side with a load equivalent to the load at this pin. 16 VccBUF Supply Supply for the Output Buffer. 17 VccVCO Supply Supply for the VCO. 18 GND GND Supply for the PLL. High frequency input pin for an external VCO. Leave Open or Ground if not used. Ground Pin for the VCO. This can be attached to the regular ground. Ensure a solid trace connects this pin to the bypass capacitors on pins 19, 23, and 24. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMX2581E 3 LMX2581E SNAS665 – MAY 2015 www.ti.com Pin Functions (continued) PIN 4 TYPE DESCRIPTION NUMBER NAME 19 VbiasVCO Output 20 Vtune Input VCO tuning voltage input. See the functional description regarding the minimum capacitance to put at this pin. 21 GND GND VCO ground. 22 VrefVCO Output VCO capacitance. Place a capacitor to GND (Preferably close to Pin 18). This value should be between 5% and 10% of the capacitance at pin 24. Recommended value is 1 µF. 23 VbiasCOMP Output VCO bias voltage temperature compensation circuit. Place a minimum 10 µF capacitor to GND (Preferably close to Pin 18). If it is possible, use more capacitance to slightly improve VCO phase noise. 24 VregVCO Output VCO regulator output. Place a minimum 10 µF capacitor to GND (Preferably close to Pin 18). If it is possible, use more capacitance to slightly improve VCO phase noise. 25 LD Output Multiplexed output that can perform lock detect, PLL N and R counter outputs, Readback, and other diagnostic functions. 26 BUFEN Input Enable pin for the RF output buffer. If not used, this can be overwritten in software. Bias circuitry for the VCO. Place a 2.2 µF capacitor to GND (Preferably close to Pin 18). 27 GND GND Digital Ground. 28 VccDIG Supply Digital Supply. 29 OSCin Input 30 MUXout Output Reference input clock. Multiplexed output that can perform lock detect, PLL N and R counter outputs, Readback, and other diagnostic functions.. 31 GND GND Ground for the fractional circuitry. 32 VccFRAC Supply Supply for the fractional circuitry. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMX2581E LMX2581E www.ti.com SNAS665 – MAY 2015 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Vcc Power supply voltage –0.3 3.6 V VIN Input voltage to pins other than Vcc pins –0.3 (Vcc + 0.3) V TL Lead temperature (solder 4 sec.) 260 °C TJ Junction temperature 150 °C VOSCin Voltage on OSCin (Pin29) ≤1.8 with Vcc Applied ≤1 with Vcc = 0 Storage Temperature, Tstg (1) –65 Vpp 150 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2500 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) ±1250 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) Vcc Power Supply Voltage TJ Junction Temperature TA Ambient Temperature MIN TYP MAX 3.15 3.3 3.45 V 125 °C 85 °C -40 UNIT 7.4 Thermal Information LMX2581E THERMAL METRIC (1) DAP (WQFN) UNIT 32 PINS RθJA Junction-to-ambient thermal resistance RθJC(top) Junction-to-case (top) thermal resistance RθJB Junction-to-board thermal resistance ψJT Junction-to-top characterization parameter ψJB Junction-to-board characterization parameter RθJC(bot) Junction-to-case (bottom) thermal resistance (1) 30 °C/W 4 For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMX2581E 5 LMX2581E SNAS665 – MAY 2015 www.ti.com 7.5 Electrical Characteristics (3.15 V ≤ Vcc ≤ 3.45 V, -40°C ≤ TA ≤ 85°C; except as specified. Typical values are at Vcc = 3.3 V, 25°C.) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CURRENT CONSUMPTION ICC Entire chip supply current One Output Enabled OUTx_PWR = 15 178 mA ICCCore Supply current except for output buffers Output Buffers and VCO Divider Disabled. 134 mA ICCRFout Additive current for each output buffer OUTx_PWR = 15 44 mA ICCVCO_DIV Additive VCO divider current VCO Divider Enabled 20 mA ICCPD Power down current Device Powered Down (CE Pin = LOW) 7 mA OSCin REFERENCE INPUT Doubler Enabled 5 250 Doubler Disabled 5 900 0.4 1.7 fOSCin OSCin frequency range vOSCin OSCin input voltage AC Coupled SpurFoscin Oscin spur Foscin = 100 MHz, Offset = 100 MHz -81 MHz Vpp dBc PLL fPD Phase detector frequency KPD Charge-pump gain 200 Gain = 1X 110 Gain = 2X 220 ... PNPLL_1/f_Norm (1) µA ... Gain = 31X Normalized PLL 1/f noise MHz 3410 Gain =31X Normalized to 1 GHz carrier and 10 kHz Offset –120.8 dBc/Hz –229 dBc/Hz PNPLL_FOM PLL figure of merit (Normalized Noise Floor) (1) Gain =31X. Normalized to PLL1 and fPD=1Hz fRFin External VCO input pin frequency Internal VCOs Bypassed (OUTA_PD=OUTB_PD=1) 0.5 2.2 GHz pRFin External VCO input pin power Internal VCOs Bypassed (OUTA_PD=OUTB_PD=1) 0 +8 dBm Phase detector spurs Fpd = 25 MHz –85 Fpd = 100 MHz –81 SpurFpd (2) dBc OUTPUTS pRFoutA+/pRFoutB+/H2RFoutX+/(1) (2) (3) (4) 6 Output power level (3) (3) Second harmonic (4) Inductor Pullup FOUT = 2.7 GHz OUTx_PWR=15 7.3 OUTx_PWR=45 12 FOUT = 2.7 GHz OUTx_PWR=15 –25 dBm dBc The PLL noise contribution is measured using a clean reference and a wide loop bandwidth and is composed into 1/f and flat components. PLL_Flat = PLL_FOM + 20*log(Fvco/Fpd)+10*log(Fpd / 1Hz). PLL_1/f = PLL_1/f_Norm + 20*log(Fvco / 1GHz) 10*log(Offset/10kHz). Once these two components are found, the total PLL noise can be calculated as PLL_Noise = 10*log( 10PLL_Flat/10) + 10PLL_1/f / 10 ) The spurs at the offset of the phase detector frequency are dependent on many factors, such as he phase detector frequency. The output power is dependent of the setup and is also programmable. Consult Application and Implementation for more information. The harmonics vary as a function of frequency, output termination, board layout, and output power setting. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMX2581E LMX2581E www.ti.com SNAS665 – MAY 2015 Electrical Characteristics (continued) (3.15 V ≤ Vcc ≤ 3.45 V, -40°C ≤ TA ≤ 85°C; except as specified. Typical values are at Vcc = 3.3 V, 25°C.) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 3800 MHz VCO fVCO KVCO ΔTCL tVCOCal Before the VCO Divider VCO gain Allowable temperature drift (5) VCO calibration time (6) Vtune = 1.3 Volts VCO not being re-calibrated fOSCin = 100 MHz fPD = 100 MHz Full Band Change 1880 — 3800 MHz fVCO = 1.9 GHz Core 1 fVCO = 2.2 GHz Core 2 PNVCO VCO phase noise (OUTx_PWR =15) fVCO = 2.7 GHz Core 3 fVCO = 3.3 GHz Core 4 (5) (6) All VCO Cores Combined 1880 Core 1 12 to 24 Core 2 15 to 30 Core 3 20 to 37 Core 4 21 to 37 MHz/V Fvco ≥2.5 GHz –125 +125 Fvco < 2.5 GHz –100 +125 No Preprogramming 140 With Preprogramming 10 10 kHz Offset –85.4 100 kHz Offset –114.5 1 MHz Offset –137.0 10 MHz Offset –154.2 40 MHz Offset –156.7 °C µs 10 kHz Offset –84.6 100 kHz Offset –114.1 1 MHz Offset –137.5 10 MHz Offset –154.5 40 MHz Offset –156.1 10 kHz Offset –81.7 100 kHz Offset –112.2 1 MHz Offset –136.0 10 MHz Offset –153.1 40 MHz Offset –155.0 10 kHz Offset –79.0 100 kHz Offset –108.6 1 MHz Offset –132.6 10 MHz Offset –152.0 40 MHz Offset –155.0 dBc/Hz dBc/Hz dBc/Hz dBc/Hz Continuous tuning range over temperature refers to programming the device at an initial temperature and allowing this temperature to drift WITHOUT reprogramming the device. This change could be up or down in temperature and the specification does not apply to temperatures that go outside the recommended operating temperatures of the device. VCO digital calibration time is the amount of time it takes for the VCO to find the correct frequency band when switching to a new frequency. After the correct frequency band is found , the remaining error is typically less than 1 MHz and then the PLL settles the rest of the error in an analog manner. Pre-programming refers to specifying a band that is close to the final (< 20 MHz), which greatly improves the VCO calibration time. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMX2581E 7 LMX2581E SNAS665 – MAY 2015 www.ti.com Electrical Characteristics (continued) (3.15 V ≤ Vcc ≤ 3.45 V, -40°C ≤ TA ≤ 85°C; except as specified. Typical values are at Vcc = 3.3 V, 25°C.) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Vcc V 0.4 V DIGITAL INTERFACE (DATA, CLK, LE, CE, MUXout, BUFEN, LD) VIH High-level input voltage VIL Low level input voltage 1.4 IIH High-level input current VIH = 1.75 V –5 5 µA IIL Low-level input current VIL = 0 V –5 5 µA VOH High-level output voltage IOH = –500 µA VOL Low-Level output voltage IOL = –500 µA 2 V 0 0.4 V 7.6 Timing Requirements, MICROWIRE Timing See Figure 1 MIN NOM MAX UNIT tES Clock-to-enable low time 35 ns tCS Data-to-clock set up time 10 ns tCH Data-to-clock hold time 10 ns tCWH Clock pulse width high 25 ns tCWL Clock pulse width low 25 ns tCES Enable-to-clock setup time 10 ns tEWH Enable pulse width high 10 ns MSB DATA D27 LSB D26 D25 D24 D23 D0 A3 A2 A1 A0 CLK tCES tCS tCH tCWH tCWL tES LE tEWH Figure 1. Serial Data Input Timing 8 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMX2581E LMX2581E www.ti.com SNAS665 – MAY 2015 7.7 Typical Characteristics Modeled Flat Noise Actual Measurement Modeled Flicker Noise Modeled Total Noise -90 -95 Phase Noise (dBc/Hz) Relative Phase Noise to Maximum Charge Pump Gain (dB) -85 -100 -105 -110 -115 -120 -125 -130 1x100 1x101 Offset (kHz) 1x102 6 5 4 3 2 1 1x103 1 Phase Noise (dBc/Hz) -100 -120 Fvco = 2000 MHz, VCO 1 Fvco = 2200 MHz, VCO 2 Fvco = 2700 MHz, VCO 3 Fvco = 3300 MHz, VCO 4 1x103 1x104 1x105 1x106 Offset (Hz) 5 1x107 7 9 11 13 15 17 19 21 23 25 27 29 31 Charge Pump Gain Setting (CPG) D001 Figure 3. KPD Impact on PLL Noise Metrics -80 -140 3 D001 Figure 2. Measurement of PLL Figure of Merit and Normalized 1/f Noise Phase Noise (dBc/Hz) Relative Normalized Flicker Noise Relative Figure of Merit 7 0 -135 1x10-1 -160 1x102 8 1x108 -80 -84 -88 -92 -96 -100 -104 -108 -112 -116 -120 -124 -128 -132 -136 -140 -144 -148 -152 -156 -160 1x103 Fvco = 2000 MHz, VCO 1 Fvco = 2200 MHz, VCO 2 Fvco = 2700 MHz, VCO 3 Fvco = 3300 MHz, VCO 4 1x104 D001 Figure 4. Closed Loop Noise for Narrower Bandwidth Filter 1x105 1x106 Offset (Hz) 1x107 1x108 D001 Figure 5. Closed Loop Noise for Wider Bandwidth 4000 -150 3750 -152 3500 3250 Frequency (MHz) Phase Noise (dBc/Hz) -154 -156 -158 3000 2750 2500 -160 2250 -162 2000 VCO_SEL=VCO3, VCO_CAPCODE=127 VCO_SEL=VCO4, VCO_CAPCODE=15 1750 -164 0 200 400 600 800 1000 1200 1400 1600 1800 2000 Output Frequency (MHz) D001 Figure 6. VCO Output Divider Noise Floor vs. Frequency 0 20 40 60 80 100 Time (us) 120 140 160 D001 Figure 7. VCO Digital Calibration Time Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMX2581E 9 LMX2581E SNAS665 – MAY 2015 www.ti.com Typical Characteristics (continued) 10 1000 50 ohm Resistor 18 nH Inductor 700 Magnitude of Input Impedance (ohms) 8 Power (dBm) 6 4 2 500 400 300 200 100 70 50 40 30 0 Pull-Up Component None 51 ohm Resistor 18 nH Inductor 20 -2 0 500 1000 1500 2000 2500 3000 Output Frequency (MHz) 3500 10 1E+8 4000 2E+8 3E+8 D001 Figure 8. Single-Ended Output Power vs. Frequency 5E+8 7E+8 1E+9 Frequency (Hz) 2E+9 3E+94E+9 D001 Figure 9. Impedance of RFoutX Pins 400 5 Real Magnitude Imaginary 350 0 300 250 -5 Impedance (ohms) Sensitivity (dBm) 200 -10 -15 -20 150 100 50 0 -50 -25 -100 25C, Buffer On 25C, Buffer Off -40 C Buffer Off 85C, Buffer Off -30 -150 -200 -250 -35 0 500 1000 1500 2000 2500 Frequency (MHz) 3000 3500 600 -12.5 500 -15 400 -17.5 300 Impedance (ohm) 700 -10 -20 -22.5 -25 -27.5 3E+9 4E+9 D001 Real Magnitude Imag 200 100 0 -100 -30 -200 OSCin Doubler Enabled OSCin Doubler Disabled -32.5 -300 -400 200 300 400 500 600 700 Frequency (MHz) 800 900 1000 D001 Figure 12. OSCin Input Sensitivity 10 2E+9 Frequency (Hz) Figure 11. Impedance of External VCO Input (Fin) Pin -7.5 -35 100 1E+9 D001 Figure 10. Sensitivity for External VCO Input (Fin) Pin Sensitivity (dBm) 0 4000 Submit Documentation Feedback 0 100 200 300 400 500 600 700 Frequency (MHz) 800 900 1000 D001 Figure 13. OSCin Input Impedance Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMX2581E LMX2581E www.ti.com SNAS665 – MAY 2015 8 Detailed Description 8.1 Overview The LMX2581E is a synthesizer, consisting of a reference input and R divider, phase detector and charge pump, VCO and high frequency fractional (N) divider, and two programmable output buffers. The device requires external components for the loop filter and output buffers, which are application dependent. Based on the oscillator input frequency (fOSC), PLL R divider value (PLL_R), PLL N Divider Value (PLL_N), Fractional Numerator (PLL_NUM), Fractional Denominator (PLL_DEN), and VCO divider value (VCO_DIV), the output frequency of the LMX2581E (fOUT) can be determined as follows: fOUT = fOSC × OSC_2X / PLL_R × (PLL_N + PLL_NUM / PLL_DEN) / VCO_DIV (1) 8.2 Functional Block Diagram Multiple Core VCO Programmable Capacitor Array (256 Values) Digital Control RFin Varactor Diode Vtune 4 Switchable VCO Cores N Divider MUX I 4/5 Prescaler Charge Pump CPout LD RFoutA RFoutB MUX Output Divider Compensation MUXout MUX 2X OSCin MUX R Divider DATA Serial Interface Control CLK LE CE Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMX2581E 11 LMX2581E SNAS665 – MAY 2015 www.ti.com 8.3 Feature Description 8.3.1 Typical Performance Characteristics 8.3.1.1 Phase Noise Typical Performance Plot Explanations Figure 2 shows 2700 MHz output and a 100 MHz phase detector frequency. The modeled noises (Flat, Flicker, and Total) are calculated from the normalized –229 dBc/Hz figure of merit and the -120.8 dBc/Hz normalized 1/f noise from the electrical table. After 200 kHz, the loop filter dynamics cause the noise to increase sharply. Figure 3 shows the relative changes with the normalized PLL noise and figure of merit as a function of charge pump gain. The PLL phase noise changes as a function of the charge pump gain. Figure 4 shows the phase noise for a filter optimized for spurs with a 20 MHz phase detector and running in fractional mode with strong dithering. Due to the narrower loop bandwidth, the impact of the VCO phase noise inside the loop bandwidth is in the 1 to 10 kHz region. In Figure 5, the loop filter was optimized for RMS jitter. This was in fractional mode with a phase detector of 200 MHz and uses the First Order Modulator. In Figure 6, the output divider noise floor only applies when the output divider is not bypassed and depends mainly on output frequency, not the actual divide value. 8.3.1.2 Other Typical Performance Plot Characteristics Explanations Figure 7 shows a frequency change of 1880 MHz to 3760 MHz with Fosc = Fpd = 100 MHz. If the VCO3 is selected as the starting VCO with VCO_CAPCODE=127, digital calibration time is closer to 115 µs. If VCO4 is selected as the starting VCO with VCO_CAPCODE=15, the calibration time is greatly shortened to something of the order of 5 µs. Figure 8 was measured with a board with very short traces. Only one of the differential outputs is routed. In Figure 9, the output impedance is mainly determined by the pullup component used at lower frequencies. For the resistor, it is 51 Ω up to about 2 GHz, where the impedance of the device starts to dominate. For the inductor it increases with frequency and then reaches a resonance frequency before coming down. These behaviors are specific to the pullup component. These impedance plots match the conditions that were used to measure output power. In Figure 12, the OSCin input sensitivity for a sine wave. The voltage has no impact and the temperature only has a slight impact. Enabling the doubler limits the performance In Figure 13, For lower frequencies, the magnitude of the OSCin input impedance can be considered high relative to 50 Ω. At higher frequencies, it is not as high and a resistive pad may be better than a simple shunt 50 Ω resistor for matching. 12 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMX2581E LMX2581E www.ti.com SNAS665 – MAY 2015 Feature Description (continued) 8.3.2 Impact of Temperature on VCO Phase Noise The phase noise specifications for the VCO in Electrical Characteristics are for a narrow loop bandwidth at room temperature. If the temperature is changed, Table 1 gives an approximation on how the VCO phase noise is impacted. For instance, if one was to lock the PLL at -40°C and then measure the phase noise at 1 MHz offset, the phase noise would typically be of the order of 2 dB better than if it was locked and measured at 25°C. If the PLL is locked at -40°C and then the temperature was to drift to 85°C, then the phase noise at 1 MHz offset would typically be about 2 dB worse than it would be if it was locked and measured at 25°C. These numbers are only approximations and may change between devices and over VCO cores slightly. Table 1. Approximate Change in VCO Phase Noise vs. Temperature and Temperature Drift in dB STARTING TEMPERATURE -40°C 25°C 85°C OFFSET FINAL TEMPERATURE 10 kHz 100 kHz 1 MHz 10 MHz 40 MHz -40°C -2 -1 -2 -2 0 25°C -1 0 0 -1 0 85°C -3 2 2 -0 0 -40°C -1 -1 0 -1 0 25°C These are all zero because all measurements are relative to this row. 85°C -3 2 2 0 0 -40°C -4 -2 -2 0 0 25°C -1 0 0 -2 0 85°C -2 2 2 0 0 8.3.3 OSCin INPUT and OSCin Doubler The OSCin pin is driven with a single-ended signal which is used as a frequency reference. Before the OSCin frequency reaches the phase detector, it may be doubled with the OSCin doubler and/or divided with the PLL R divider. Because the OSCin signal is used as a clock for the VCO calibration, the OSC_FREQ word needs to be programmed correctly and a proper signal needs to be applied at the OSCin pin at the time of programming the R0 register in order for the VCO calibration to properly work. Higher slew rates tend to yield the best fractional spurs and phase noise, so a square wave signal is best for OSCin. If using a sine wave, higher frequencies tend to yield better phase noise and fractional spurs due to their higher slew rates. The OSCin pin has high impedance, so for optimal performance, it is recommended to use either a shunt resistor or resistive pad to make sure that the impedances looking towards and away from the device input are both close to 50 Ω. 8.3.4 R Divider The R divider divides the OSCin frequency down to the phase detector frequency. With this device, it is possible to use both the doubler and the R divider at the same time. 8.3.5 PLL N Divider And Fractional Circuitry The N divider includes fractional compensation and can achieve any fractional denominator (PLL_DEN) from 1 to 4,194,303. The integer portion, PLL_N, is the whole part of the N divider value and the fractional portion, PLL_NUM / PLL_DEN, is the remaining fraction. PLL_N, PLL_NUM, and PLL_DEN are software programmable. So in general, the total N divider value, N, is determined by: N = PLL_N + PLL_NUM / PLL_DEN. The order of the delta sigma modulator is programmable from integer mode to third order. There are also several dithering modes that are also programmable. In order to make the fractional spurs consistent, the modulator is reset any time that the R0 register is programmed. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMX2581E 13 LMX2581E SNAS665 – MAY 2015 www.ti.com 8.3.5.1 Programmable Dithering Levels If used appropriately, dithering may be used to reduce sub-fractional spurs, but if used inappropriately, it can actually create spurs and increase phase noise. Table 2 provides guidelines for the use of dithering based on the fractional denominator, after the fraction is reduced to lowest terms. Table 2. Dithering Recommendations FRACTION DITHERING RECOMMENDATION Fractional Numerator = 0 Disable Dithering This is often the worst case for spurs, which can actually be turned into the best case by simply disabling dithering. This will have performance that is similar to integer mode. Equivalent Denominator < 20 Disable Dithering These fractions are not well randomized and dithering will likely create phase noise and spurs. Equivalent Denominator is not divisible by 2 or 3 Disable Dithering There will be no sub-fractional spurs, so dithering is likely not to be very effective Equivalent Denominator > 200 and is divisible by 2 or 3 Consider Dithering COMMENTS Dithering may help reduce the sub-fractional spurs, but understand it may degrade the PLL phase noise. In general, dithering is likely to cause more harm than good for poorly randomized fractions like 1/2. There are situations when dithering does make sense and when it is used, it is recommended to adjust the PFD_DLY word accordingly to compensate for this. 8.3.5.2 Programmable Delta Sigma Modulator Order The fractional modulator order is programmable, which gives the opportunity to better optimize phase noise and spurs. Theoretically, higher order modulators push out phase noise to farther offsets, as described in Table 3. Table 3. Choosing the Fractional Modulator Order MODULATOR ORDER APPLICATIONS Integer Mode (Order = 0) If the fractional numerator is zero, it is best to run the device in integer mode to minimize phase noise and spurs. First Order Modulator When the equivalent fractional denominator is 6 or less, the first order modulator theoretically has lower phase noise and spurs, so it always makes sense in these situations. When the fractional denominator is between 6 and about 20, consider using the first order modulator because the spurs might be far enough outside the loop bandwidth that they will be filtered. The first order modulator also does not create any sub-fractional spurs or phase noise. 2nd and 3rd Order Modulators The choice between 2nd and 3rd order modulator tends to be a little more application specific. If the fractional denominator is not divisible by 3, then the 2nd and 3rd order modulators will have spurs in the same offsets, so the 3rd is generally better for spurs. However, if stronger levels of dithering is used, the 3rd order modulator will create more close-in phase noise than the 2nd order modulator Figure 14 and Figure 15 give an idea of the theoretical impact of the delta sigma modulator order on the shaping of the phase noise and spurs. In terms of phase noise, this is what one would theoretically expect if strong dithering was used for a well-randomized fraction. Dithering can be set to different levels or even shut off and the noise can be eliminated. In terms of spurs, they can change based on fraction, but they will theoretically pushed out to higher phase detector frequencies. However, one must be aware that these are just THEORETICAL graphs and for offsets that on the order of less than 5% of the phase detector frequency, other factors can impact the noise and spurs. In Figure 14, the curves all cross at 1/6th of the phase detector frequency and that this transfer function peaks at half of the phase detector frequency, which is assumed to be well outside the loop bandwidth. Figure 15 shows the impact of the phase detector frequency on the modulator noise. 14 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMX2581E LMX2581E www.ti.com SNAS665 – MAY 2015 -50 Theoretical Gain for Noise and Spurs (dB) -60 -70 -80 -90 -100 -110 -120 -130 -140 1st Order Modulator 2nd Order Modulator 3rd Order Modulator -150 1x106 2x106 5x106 1x107 2x107 Offset (Hz) 5x107 1x108 2x108 D001 Figure 14. Theoretical Delta Sigma Noise Shaping for a 100 MHz Phase Detector Frequency -50 Theoretical Gain for Noise and Spurs (dB) -60 -70 -80 -90 -100 -110 -120 -130 Fpd=10MHz Fpd=100 MHz Fpd=200 MHz -140 -150 1x106 2x106 5x106 1x107 2x107 Offset (Hz) 5x107 1x108 2x108 D001 Figure 15. Theoretical Delta Sigma Noise Shaping for 3rd Order Modulator For lower offsets, the actual noise added by the delta sigma modulator may be higher than the theoretical values shown due to nonlinearity of the phase detector. This noise floor can vary with the modulator order, phase detector frequency, and PFD_DLY word setting as shown in the following table, which shows the phase noise at 10 kHz offset for a frequency close to 2801 MHz with a well randomized fraction and strong dithering. The phase noise in integer mode is also shown for comparison purposes. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMX2581E 15 LMX2581E SNAS665 – MAY 2015 www.ti.com Table 4. Impact of PFD_DLY, Modulator Order, and Phase Detector Frequency on Modulator Noise Floor INTEGER PFD_ DLY Fpd= 25 MHz Fpd= 50MHz 0 -106.7 -109.5 -111.4 1 -106.2 -108.8 -110.6 2 -106.0 -108.3 3 -106.0 4 -105.6 5 2nd ORDER MODULATOR Fpd= Fpd= 100 MHz 200 MHz Fpd= 25 MHz Fpd= 50MHz Fpd= Fpd= 100 MHz 200 MHz -111.0 -106.3 -108.8 -110.6 -110.9 -106.5 -108.4 -110.1 -109.7 -110.1 -105.6 -108.3 -108.2 -109.4 -109.9 -105.3 -107.7 -109.4 -110.0 -105.1 -105.5 -107.6 -108.8 -110.1 6 -105.1 -107.3 -108.5 7 -104.8 -106.8 -108.2 3rd ORDER MODULATOR Fpd= 25 MHz Fpd= 50MHz Fpd= Fpd= 100 MHz 200 MHz -111.0 -84.4 -87.5 -90.1 -110.0 -88.3 -91.3 -93.6 -98.5 -109.2 -110.1 -92.9 -96.1 -98.1 -102.8 -107.9 -109.2 -109.8 -99.2 -101.8 -102.6 -105.4 -107.5 -108.7 -109.3 -103.0 -105.4 -105.8 -106.2 -105.6 -107.4 -108.6 -109.0 -101.4 -104.0 -103.7 -105.5 -109.3 -104.6 -107.0 -107.8 -109.1 -98.4 -101.6 -102.7 -102.9 -105.9 -104.6 -106.2 -107.4 -108.7 -97.1 -100.6 -102.1 -100.2 -93.8 8.3.6 PLL Phase Detector and Charge Pump The phase detector compares the outputs of the R and N dividers and generates a correction current corresponding to the phase error. This charge pump current is software programmable to many different levels. The phase detector frequency, fPD, can be calculated as follows: fPD = fOSCin × OSC_2X / R (2) The charge pump outputs a correction current into the loop filter, which is implemented with external components. The gain of the charge pump is programmable to 32 different levels with the CPG word and the PFD_DLY word can adjust the minimum on time that the charge pump comes on for. 16 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMX2581E LMX2581E www.ti.com SNAS665 – MAY 2015 8.3.7 External Loop Filter The LMX2581E requires an external loop filter which is application-specific and can be configured by consulting LMX2581E Tools and Software. For the LMX2581E, it matters what impedance is seen from the Vtune pin looking outwards. This impedance is dominated by the component C3_LF for a third order filter or C1_LF for a second order filter (R3_LF = C3_LF = 0). If there is at least 3.3 nF for the capacitance that is shunt with this pin, the VCO phase noise will be close to the best it can be. If there is less, the VCO phase noise in the 100 k to 1MHz region. In cases where 3.3 nF might restrict the loop bandwidth to be too narrow, it might make sense to violate this restriction a little and sacrifice some VCO phase noise in order to get a wider loop bandwidth. R3_LF Vtune C3_LF LMX2581 CPout C2_LF C1_LF R2_LF Figure 16. Typical Loop Filter 10 Component 1 nF 3.3 nF 330 pF Phase Noise Degradation (dB) 8 6 4 2 0 -2 1x103 1x104 1x105 1x106 Offset (Hz) 1x107 5x107 D001 Figure 17. Vtune Capacitor Impact on VCO Phase Noise Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMX2581E 17 LMX2581E SNAS665 – MAY 2015 www.ti.com 8.3.8 Low Noise, Fully Integrated VCO The VCO takes the voltage from the loop filter and converts this into a frequency. The VCO frequency is related to the other frequencies and divider values as follows: fVCO = fPD × N = fOSCin × OSC_2X × N / R. The VCO is fully integrated, including the tank circuitry. In order to the reduce the VCO tuning gain and therefore improve the VCO phase noise performance, the internal VCO is actually made of VCO cores working as one. These cores starting from lowest frequency to highest frequency are VCO 1, VCO 2, VCO 3, and VCO 4. Each VCO core has 256 different frequency bands. Band 255 is the lowest frequency and Band 0 is the highest This creates the need for frequency calibration in order to determine the correct VCO core and correct frequency band in that VCO core. The frequency calibration routine is activated any time that the R0 register is programmed with the NO_FCAL bit equal to zero. In order for this frequency calibration to work properly, the OSC_FREQ word needs to be set to the correct setting. The VCO_SEL word allows the user to suggest a particular VCO core for the device to choose, which is useful for optimizing fractional spurs and minimizing lock time. Table 5. Approximate (NOT Ensured) VCO Core Frequency Ranges VCO CORE APPROXIMATE FREQUENCY RANGE VCO 1 1800 to 2270 MHz VCO 2 2135 to 2720 MHz VCO 3 2610 to 3220 MHz VCO 4 3075 to 3880 MHz 8.3.8.1 VCO Digital Calibration When the frequency is changed, the digital VCO goes through the following VCO calibration: 1. Depending on the status of the VCO_SEL word, the starting VCO core is selected. 2. The algorithm starts counting at the default band in this core as determined by the VCO_CAPCODE value. 3. The VCO increments or decrements the CAPCODE based on the what the actual VCO output is compared to the target VCO output. 4. Repeat step 3 until either the VCO is locked or the VCO is at VCO_CAPCODE = 0 or 255 5. If not locked, then choose the next appropriate VCO if possible and return to step 3. If not possible, the calibration is terminated. A good starting point is to set VCO_SEL = 2 for VCO 3 and set VCO_SEL_MODE = 1 to start at the selected core. If there is the potential of switching the VCO from a frequency above 3 GHz directly to a frequency below 2.2 GHz, VCO_SEL_MODE can not be set to 0. In this case, VCO_SEL_MODE can still be set to 1 to select a starting core, but the starting core specified by VCO_SEL can not be VCO 4. The digital calibration time can be improved dramatically by giving the VCO guidance regarding which VCO core and which VCO_CAPCODE to start using. Even if the wrong VCO core is chosen, which could happen near the boundary of two cores, the calibration time is improved. For situations where the frequency change is small, the device can be programmed to automatically start at the last VCO core used. For applications where the frequency change is relatively small, the best VCO calibration time can often be achieved by setting the VCO_SEL_MODE to choose the last VCO core that was used. 8.3.9 Programmable VCO Divider The VCO divider can be programmed to even values from 2 to 38 as well as bypassed by either one or both of the RFout outputs. When the zero delay mode is not enabled, the VCO divider is not in the feedback path between the VCO and the PLL and therefore has no impact on the PLL loop dynamics. After this programmable divider is changed, it may be beneficial to reprogram the R0 register to re-calibrate the VCO. The frequency at the RFout pin is related to the VCO frequency and divider value, VCO_DIV, as follows: fRFout = fVCO / VCO_DIV (3) When this divider is enabled, there will be some far-out phase noise contribution to the VCO noise. When changing to a VCO_DIV value of 4, either from a state of VCO_DIV=2 or OUTx_MUX = 0, it is necessary to program VCO_DIV first to a value of 6, then to a value of 4. This holds for no other VCO_DIV value and is not necessary if the VCO frequency (but not VCO_DIV) is changing. 18 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMX2581E LMX2581E www.ti.com SNAS665 – MAY 2015 8.3.10 0–Delay Mode When the VCO divider is used, an ambiguous phase relationship is created between the OSCin and RFout pins. 0–Delay mode can be enabled to eliminate this ambiguity. When this mode is used, special care needs to be taken because it does interfere with the VCO calibration if not done correctly. The correct way to use 0–Delay mode is as follows: 1. If N is not divisible by VCO_DIV, reduce the phase detector frequency to make it so. 2. Program as normal and lock the PLL. 3. Program the NO_FCAL =1. 4. Program 0_DLY = 1. This will cause the PLL to lose lock. 5. Program the PLL_N value with PLL_N* / VCO_DIV, where PLL_N* is the original value. 6. The PLL should now be locked in zero delay mode. 8.3.11 Programmable RF Output Buffers The output states of the RFoutA and RFoutB pins are controlled by the BUFEN pin as well as the BUFEN_DIS programming bit. If the pin is powered up, then output power can be programmed to various levels with the OUTx_PWR words. Table 6. Output States of the RFoutA and RFoutB Pins OUTA_PD OUTB_PD BUFEN_DIS BUFEN PIN OUTPUT STATE 1 X X Powered Down 0 X Powered Up Low Powered Down High Powered Up 0 1 8.3.11.1 Choosing the Proper Pullup Component The first decision is to whether to use a resistor or inductor for a pullup. • The resistor pullup involves placing a 50 Ω resistor to the power supply on each side, which makes the output impedance easy to match and close to 50 Ω. However, it is a higher current for the same output power, and the maximum possible output power is more limited. For this method, the OUTx_PWR setting should be kept about 30 or less (for a 3.3-V supply) to avoid saturation. The resistive pullup is also sometimes more desirable when the output frequency is lower. • The inductor pullup involves placing an inductor to the power supply. This inductor should look like high impedance at the frequency of interest. This method offers higher output power for the same current and higher maximum output power. The output power is about 3 dB higher for the same OUTx_PWR setting than the resistor pullup. Since the output impedance will be very high and poorly matched, it is recommended to either keep traces short or to AC couple this into a pad for better impedance matching. If an output is partially used or unused: • If the output is unused, then power it down in software. No external components are necessary. • If only one side of the differential output is used, include the pullup component and terminate the unused side, such that the impedance as seen by this pin looks similar to the impedance as seen by the used side. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMX2581E 19 LMX2581E SNAS665 – MAY 2015 www.ti.com 8.3.11.2 Choosing the Best Setting for the RFoutA_PWR and RFoutB_PWR Words Table 7 shows the impact of the RFoutX_PWR word on the output power and current RELATIVE to a setting of RFoutX_PWR = 15. The choice of pullup component has an impact on the output power, but not much impact on the output current. The relative noise floor measurements are made without the VCO divider engaged. Table 7. Impact of the RFoutX_PWR Word on the Output Power and Current OUTx_PWR RELATIVE CURRENT (mA) RESISTIVE PULLUP INDUCTOR PULLUP RELATIVE OUTPUT POWER (dB) RELATIVE NOISE FLOOR (dB) RELATIVE OUTPUT POWER (dB) RELATIVE NOISE FLOOR (dB) 0 −16 − 9.0 + 4.0 − 9.0 + 2.5 5 − 11 − 4.6 + 0.7 − 4.6 + 0.5 10 −5 −2.0 + 0.9 −2.0 - 0.1 15 0 0 0 0 0 20 +5 + 1.4 + 0.7 + 1.5 - 0.6 25 +10 + 2.1 + 1.6 + 2.8 - 1.1 30 +15 + 2.4 + 1.6 + 3.9 - 1.0 35 +20 + 2.2 + 1.6 + 4.8 - 0.9 40 +25 + 1.9 + 3.2 + 5.4 + 0.2 45 +30 + 1.4 + 5.6 +6.0 + 2.0 For a resistive pullup, a setting of 15 is optimal for noise floor and a setting if 30 is optimal for output power. Settings above 30 are generally not recommended for a resistive pullup. For an inductor pullup, a setting of 30 is optimal for noise floor and a setting of 45 is optimal for output power. These settings may vary a little based on output frequency, supply voltage, and loading of the output, but the above table gives a fairly close indication of what performance to expect. 8.3.12 Fastlock The LMX2581E includes the Fastlock feature that can be used to improve the lock times. When the frequency is changed, a timeout counter is used to engage the Fastlock for a programmable amount of time. During the time the device is in Fastlock, the FLout pin changes from high impedance to low, thus switching in the external resistor R2pLF in parallel with R2_LF. Vtune Charge Pump CPout C2_LF Fastlock Control FLout C1_LF R2pLF R2_LF Table 8. Normal Operation vs. Fastlock PARAMETER NORMAL OPERATION Charge Pump Gain CPG FASTLOCK FL_CPG FLout Pin High Impedance Grounded Once the loop filter values and charge pump gain are known for normal operation, they can be determined for Fastlock operation as well. In normal operation, one can not use the highest charge pump gain and still use Fastlock because there will be no larger current to switch in. The resistor and the charge pump current are changed simultaneously so that the phase margin remains the same while the loop bandwidth is multiplied by a factor of K as shown in Table 9: 20 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMX2581E LMX2581E www.ti.com SNAS665 – MAY 2015 Table 9. Fastlock Configuration PARAMETER SYMBOL CALCULATION Charge Pump Gain in Fastlock FL_CPG Typically use the highest value. Loop Bandwidth Multiplier K K=sqrt(FL_CPG/CPG) External Resistor R2pLF R2 / (K-1) 8.3.13 Lock Detect The LMX2581E offers two circuits to detect lock, Vtune and Digital Lock Detect, which may be used separately or in conjunction. Digital Lock Detect gives a reliable indication of lock/unlock if programmed correctly with the one exception, which occurs when the PLL is locked to a valid OSCin signal and then the OSCin signal is abruptly removed. In this case, digital lock detect can sometimes still indicate a locked state, but Vtune Lock detect will correctly indicate an unlocked state. Therefore, for the most reliable lock detect, it is recommended to use these in conjunction, because each technique's drawback is covered by the other one. Note that because the powerdown mode powers down the lock detect circuitry, it is possible to get a high lock detect indication when the device is powered down. The details of the two respective methods are described below in the Vtune Lock Detect and Digital Lock Detect (DLD) sections. 8.3.13.1 Vtune Lock Detect This style of lock detect only works with the internal VCO. Whenever the tuning voltage goes below the threshold of about 0.5 V, or above the threshold of about 2.2 V, the internal VCO will become unlocked and the Vtune lock detect will indicate that the device is unlocked. For this reason, when the Vtune lock detect says the PLL is unlocked, one can be certain that it is unlocked. 8.3.13.2 Digital Lock Detect (DLD) This lock detect works by comparing the phase error as presented to the phase detector. If the phase error plus the delay as specified by the PFD_DLY word outside the tolerance as specified by DLD_TOL, then this comparison would be considered to be an error, otherwise passing. At higher phase detector frequencies, it may be necessary to adjust the DLD_ERR_CNT and DLD_PASS_CNT. The DLD_ERR_CNT specifies how may errors are necessary to cause the circuit to consider the PLL to be unlocked. The DLD_PASS_CNT multiplied by 8 specifies how many passing comparisons are necessary to cause the PLL to be considered to be locked and also resets the count for the errors. The DLD_ERR_CNT and DLD_PASS_CNT values may be decreased to make the circuit more sensitive, but if lock detect is made too sensitive, chattering can occur and these values should be increased. 8.3.14 Part ID and Register Readback 8.3.14.1 Uses of Readback The LMX2581E allows any of its registers to be read back, which could be useful for the following applications below. • Register Readback – By reading back the register values, it can be confirmed that the correct information was written. In addition to this, Register R6 has special diagnostic information that could potentially be useful for debugging problems. • Part ID Readback – By reading back the part ID, this information may be used by whatever device is programming the LMX2581E to identify this device and know what programming information to send. In addition to this, the BUFEN and CE pins may be used to create 4 unique part ID values. Although these pins can impact the device, they may be overridden in software. It is not necessary to have the device programmed in order to do part ID Readback. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMX2581E 21 LMX2581E SNAS665 – MAY 2015 www.ti.com The procedure for doing this Readback is in Serial Timing for Readback. Depending on the settings for the ID(R0[31]) and RDADDR (R6[8:5]), information a different bit stream will be returned as shown in Table 10. Table 10. Uses of Readback ID BUFEN PIN CE PIN READBACK CODE 0 X X Readback register defined by RDADDR. 0 0 0x 00000500 0 1 0x 00000510 1 0 0x 00000520 1 1 0x 00000530 1 8.3.14.2 Serial Timing for Readback Readback is done through the the MUXout (or LD) pin with the same clock that is used to clock in the data. • • • • Choose either the MUXout (or LD) pin for reading back data and program the MUXOUT_SELECT (or LD_SELECT) to readback mode. Bring the LE pin from low to high to start the readback at the MSB. After the signal to the CLK pin goes high, the data will be ready at the readback pin 10 ns afterwards. It is recommended to read back the data on the falling edge of the clock. Technically, the first bit actually becomes ready after the rising edge of LE, but it still needs to be clocked out. The address being clocked out will all be 1's. Because the CLK pin is both used to clock in data and clock out data, special care needs to be taken to ensure that erroneous data is not being clocked in during readback. There are two approaches to deal with this. The first approach is to actually send valid data during readback. For this approach, R6 is a recommended register and the approach is shown in Figure 18: MSB LSB D27 MUXout D26 D25 D24 D23 D0 1 1 1 D27 1 LSB DATA D27 D26 D25 D24 D23 D0 A3 A2 A1 A0 CLK tCS tCES tCH tCWH tES tCWL LE tEWH Figure 18. Timing for Readback A second approach is to hold LE high during readback so that the clock pulses do not clock data into the part, but still function for readback purposes. Figure 19 demonstrates this method: MSB D27 MUXout LSB D26 D25 D24 D23 D0 1 1 1 1 LSB CLK tCWH tCES tCWL LE Figure 19. Timing for Readback, Holding LE High 22 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMX2581E LMX2581E www.ti.com SNAS665 – MAY 2015 8.3.15 Optimization of Spurs The LMX2581E offers several programmable features for optimizing fractional spurs. In order to get the best out of these features, it makes sense to understand the different kinds of spurs as well as their behaviors, causes, and remedies. Although optimizing spurs may involve some trial and error, there are ways to make this process more systematic. Texas Instruments offers tools for information and tools for fractional spurs such as Application Note AN-1879 ( AN-1879 Fractional N Frequency Synthesis), The Clock Design Tool, and this datasheet. 8.3.15.1 Phase Detector Spur The phase detector spur occurs at an offset from the carrier equal to the phase detector frequency, fPD. To minimize this spur, considering using a smaller value for PFD_DLY, smaller value for CPG_BLEED, and a lower phase detector frequency. In some cases where the loop bandwidth is very wide relative to the phase detector frequency, some benefit might be gained from using a narrower loop bandwidth or adding poles to the loop filter, but otherwise the loop filter has minimal impact. Bypassing at the supply pins and board layout can also have an impact on this spur, especially at higher phase detector frequencies. 8.3.15.2 Fractional Spur - Integer Boundary Spur This spur occurs at an offset equal to the difference between the VCO frequency and the closest integer channel for the VCO. For instance, if the phase detector frequency is 100 MHz and the VCO frequency was 2703 MHz, then the integer boundary spur would be at 3 MHz offset. This spur can be either PLL or VCO dominated. If it is PLL dominated, then the following table shows that decreasing the loop bandwidth and some of the programmable fractional words may impact this spur. If the spur is VCO dominated, then reducing the loop filter will not help, but rather reducing the phase detector and having a good slew rate and signal integrity at the OSCin pin will help. Regardless of whether it is PLL or VCO dominated, the VCO core does impact this spur. Table 11. Typical Integer Boundary Spur Levels FRACTIONAL INTEGER BOUNDARY SPURS PLL DOMINATED VCO CORE InBandSpur Metric VCO 1 -33 VCO 2 –25 VCO 3 –37 VCO 4 –34 FORMULA VCO DOMINATED VCOXtalkSpur METRIC -89 InBandSpur + PLL_Transfer_Function(Offset) - 20 × log(VCO_DIV) –83 –99 –87 FORMULA VCOXtalkSpur +VCO_Transfer_Function(Offset) + 20 × log(fPD) - 20 × log(Offset / 1MHz) It is common practice to benchmark a fractional PLL spurs by choosing a worst case VCO frequency and use this as a metric. However, one should be cautions that this is only a metric for the integer boundary spur. For instance, suppose that one was to compare two devices by using an 100 MHz phase detector frequency, tune the VCO to 2000.001 MHz, and measure the integer boundary spur at 1 kHz. If one part was to have better spurs at this frequency, this does not necessarily mean that the spurs would be better at a channel farther from an integer boundary, like 2025.001 MHz. 8.3.15.3 Fractional Spur - Primary Fractional Spurs These spurs occur at multiples of fPD / PLL_DEN and are not the integer boundary spur. For instance, if the phase detector frequency is 100 MHz and the fraction is 3/100, the primary fractional spurs would be at 1,2,4,5,6,...MHz. These are impacted by the loop filter bandwidth and modulator order. If a small frequency error is acceptable, then a larger equivalent fraction may improve these spurs. For instance, if the fraction is 53/200, expressing this as 530,000 / 2,000, 001. This larger un-equivalent fraction pushes the fractional spur energy to much lower frequencies that hopefully is not so critical. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMX2581E 23 LMX2581E SNAS665 – MAY 2015 www.ti.com 8.3.15.4 Fractional Spur - Sub-Fractional Spurs These spurs appear at a fraction of fPD / PLL_DEN and depend on modulator order. With the first order modulator, there are no sub-fractional spurs. The second order modulator can produce 1/2 sub-fractional spurs if the denominator is even. A third order modulator can produce sub-fractional spurs at 1/2,1/3, or 1/6 of the offset, depending if it is divisible by 2 or 3. For instance, if the phase detector frequency is 100 MHz and the fraction is 3/100, no sub-fractional spurs for a first order modulator or sub-fractional spurs at multiples of 1.5 MHz for a 2nd or 3rd order modulator would be expected. Aside from strategically choosing the fractional denominator and using a lower order modulator, another tactic to eliminate these spurs is to use dithering and express the fraction in larger equivalent terms (that is, 1000000/4000000 instead of 1/4). If a small frequency error is acceptable, also consider a larger un-equivalent fraction like (1000000,4000000). However, dithering can also add phase noise, so if dithering is used, this needs to be managed with the various levels it has and the PFD_DLY word to get the best possible performance. 8.3.15.5 Summary of Spurs and Mitigation Techniques Table 12 gives a summary of the spurs discussed so far and techniques to mitigate them. Table 12. Spurs and Mitigation Techniques SPUR TYPE OFFSET Phase Detector fPD Integer Boundary fVCO mod fPD WAYS to REDUCE 1. 2. 3. TRADE-OFF Reduce Phase Detector Frequency Decrease PFD_DLY Decrease CPG_BLEED Although reducing the phase detector frequency does improve this spur, it also degrades phase noise. Methods for PLL Dominated Spurs 1. Avoid the worst case VCO frequencies if possible. 2. Strategically choose which VCO core to use if possible. Reducing the loop bandwidth may 3. Ensure good slew rate and signal integrity at the degrade the total integrated noise if the OSCin pin bandwidth is too narrow. 4. Reduce the loop bandwidth or add more filter poles for out of band spurs 5. Experiment with modulator order, PFD_DLY, and CPG_BLEED Methods for VCO Dominated Spurs 1. Avoid the worst case VCO frequencies if possible. 2. Strategically choose which VCO core to use if possible. 3. Reduce Phase Detector Frequency 4. Ensure good slew rate and signal integrity at the OSCin pin 5. Make the impedance looking outwards from the OSCin pin close to 50 Ω. Primary Fractional Sub-Fractional 24 Reducing the phase detector may degrade the phase noise and also reduce the capacitance at the Vtune pin. Decreasing the loop bandwidth too much may degrade in-band phase noise. Also, larger un-equivalent fractions only sometimes work fPD / PLL_DEN 1. 2. 3. Decrease Loop Bandwidth Change Modulator Order Use Larger Un-equivalent Fractions fPD / PLL_DEN / k k=2,3, or 6 1. 2. 3. 4. 5. Use Dithering Use Larger Equivalent Fractions Dithering and larger fractions may Use Larger Un-equivalent Fractions increase phase noise. Reduce Modulator Order Eliminate factors of 2 or 3 in denominator (see AN1879, SNAA062) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMX2581E LMX2581E www.ti.com SNAS665 – MAY 2015 8.4 Device Functional Modes 8.4.1 Full Synthesizer Mode In this mode, the internal VCO is enabled. When combined with an external reference and loop filter, this mode provides a complete signal source. 8.4.2 External VCO Mode The LMX2581E allows the user to use an external VCO by using the Fin pin and selecting the external VCO mode for the MODE word. Because this is software selectable, the user may have a setup that switches between the external and internal VCO. Because the Fin pin is close to the RFoutA and RFoutB pins, some care needs to be taken to minimize board crosstalk when both an external VCO and an output buffer is used. If only one output buffer is required, it is recommended to use the RFoutB output because it is physically farther from the Fin pin and therefore will have less board related crosstalk. When using external VCO with a different characteristic, it may be necessary to change the phase detector polarity (CPP). 8.4.3 Powerdown Modes The LMX2581E can be powered down either fully or partially with the PWDN_MODE word or the CE pin. The two types of powerdown are in the following table. Table 13. LMX2581E Powerdown Modes POWERDOWN STATE DESCRIPTION Partial Powerdown VCO, PLL, and Output buffers are powered down, but the LDOs are kept powered up to reduce the time it takes to power the device back up. Full Powerdown VCO, PLL, Output Buffers, and LDOs are all powered down. When coming out of a full powerdown state, it is necessary to do the initial power-on programming sequence described in later sections. If coming out of a partial powerdown state, it is necessary to do the sequence for switching frequencies after initialization, that is described in later sections. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMX2581E 25 LMX2581E SNAS665 – MAY 2015 www.ti.com 8.5 Programming The LMX2581E is programmed using several 32-bit registers. A 32-bit shift register is used as a temporary register to indirectly program the on-chip registers. The shift register consists of a data field and an address field. The last LSB bits, ADDR[3:0], form the address field, which is used to decode the internal register address. The remaining 28 bits form the data field DATA[27:0]. While LE is low, serial data is clocked into the shift register upon the rising edge of clock (data is programmed MSB first). When LE goes high, data is transferred from the data field into the selected register bank. 8.5.1 Serial Data Input Timing There are several programming considerations (see Figure 20): • A slew rate of at least 30 V/us is recommended for the CLK, DATA, and LE signals • The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the LE signal, the data is sent from the shift registers to an actual counter. • The LE pin may be held high after programming and this will cause the LMX2581E to ignore clock pulses. • The CLK signal should not be high when LE transitions to low. • When CLK and DATA lines are shared between devices, it is recommended to divide down the voltage to the CLK, DATA, and LE pins closer to the minimum voltage. This provides better noise immunity. • If the CLK and DATA lines are toggled while the in VCO is in lock. As is sometimes the case when these lines are shared with other parts, the phase noise may be degraded during the time of this programming. MSB DATA D27 LSB D26 D25 D24 D23 A3 D0 A2 A1 A0 CLK tCES tCS tCH tCWH tCWL tES LE tEWH Figure 20. Serial Data Input Timing 8.5.2 Recommended Initial Power on Programming Sequence When the device is first powered up, the device needs to be initialized and the ordering of this programming is very important. After the following sequence is complete, the device should be running and locked to the proper frequency. 1. Apply power to the device and ensure the Vcc pins are at the proper levels. 2. Ensure that a valid reference is applied to the OSCin pin 3. Program register R5 with RESET (R5[4]) =1 4. Program registers R15,R13,R10,R9,R8,R7,R6,R5,R4,R3,R2,R1, and R0 5. Wait 20 ms 6. Program the R0 register again OR do the recommended sequence for changing frequencies. 8.5.3 Recommended Sequence for Changing Frequencies The recommended sequence for changing frequencies is as follows: 1. (optional) If the OUTx_MUX State is changing, program Register R5 2. (optional) If the VCO_DIV state is changing, program Register R3. See VCO_DIV[4:0] — VCO Divider Value if programming a to a value of 4. 3. (optional) If the MSB of the fractional numerator or charge pump gain is changing, program register R1 4. (Required) Program register R0 Although not necessary, it is also acceptable to program the R0 register a second time after this programming sequence. It is not necessary to program the initial power on sequence to change frequencies. 26 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMX2581E LMX2581E www.ti.com SNAS665 – MAY 2015 Programming (continued) 8.5.4 Triggering Registers The action of programming certain registers may trigger special actions as shown in Table 14. Table 14. Triggering Registers REGISTER CONDITIONS ACTIONS TRIGGERED WHY THIS IS DONE R5 RESET = 1 The registers are reset by the power on reset circuitry All Registers are reset to power on when power is initially applied. The RESET bit allows the default values. This takes less than 1 user the option to perform the same functionality of the us. The reset bit is self-clearing. power-on reset through software. R0 NO_FCAL = 0 —Starts the Frequency Calibration —Engages Fastlock (If FL_TOC>0) This activates the frequency calibration, which chooses the correct VCO core and also the correct frequency band within that core. This is necessary whenever the frequency is changed. If it is desired that the R0 register be programmed without activating this calibration, then the NO_FCAL bit can be set to zero. If the fastlock timeout counter is programmed to a nonzero value, then this action also engages fastlock. R0 NO_FCAL = 1 —Engages Fastlock (If FL_TOC>0) This engages fastlock, which may be used to decrease the lock time in some circumstances. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMX2581E 27 LMX2581E SNAS665 – MAY 2015 www.ti.com 8.6 Register Maps Table 15. Register Map Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 DATA[27:0] R15 0 R13 0 0 0 0 1 DLD_ERR_CNT[3:0] 0 0 0 0 1 1 1 1 1 1 DLD_ TOL [2:0] DLD_PASS_CNT[9:0] 1 0 1 1 VCO _ CAP _ MAN 1 0 0 0 0 0 1 0 0 0 VCO_CAPCODE[7:0] 1 1 1 1 0 1 1 0 1 R10 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 1 0 1 0 R9 0 0 0 0 0 0 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 1 R8 0 0 1 0 0 0 0 0 0 1 1 1 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 1 0 0 0 LD_ PINMODE[2:0] 0 1 1 1 uWI RE_ LOC K 0 1 1 0 RES ET 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 R7 0 R6 0 R5 0 FL_SELECT [4:0] FL_PINMODE [2:0] 0 0 0 0 0 0 1 0 0 0 R2 0 0 OSC _2X 0 CPP 1 OUT _LD EN FRAC_ DITHER [1:0] BUF EN_ DIS OSC_FREQ[2:0] 0 0 0 0 MUXOUT_ PINMODE [2:0] LD_SELECT [4:0] NO_ FCA L 1 0 0 VCO_ SEL_ MODE [1:0] OUTB_ MUX [1:0] FL_CPG[4:0] VCO_DIV[4:0] OUTB_PWR[5:0] OUTA _MUX [1:0] 0_ DLY LD_ INV 0 RDADDR[3:0] MODE [1:0] 0 PWDN_MODE [2:0] CPG_BLEED[5:0] OUTA_PWR[5:0] PLL_DEN[21:0] VCO_ SEL [1:0] CPG[4:0] ID MUXOUT_SELECT [4:0] FL_TOC[11:0] 0 R0 0 FL_ FRC E R3 R1 FL_ INV MUX _ INV RD_DIAGNOSTICS[19:0] PFD_DLY [2:0] R4 28 0 2 ADDRESS[3:0] PLL_NUM[21:12] PLL_N[11:0] FRAC_ ORDER [2:0] PLL_R[7:0] PLL_NUM[11:0] Submit Documentation Feedback OUT B _PD OUT A _PD Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMX2581E LMX2581E www.ti.com SNAS665 – MAY 2015 8.6.1 Programming Word Descriptions 8.6.1.1 Register R15 The programming of register R15 is only necessary when one wants to change the default value of VCO_CAPCODE for improving the VCO calibration time or use the VCO_CAP_MAN bit for diagnostic purposes. 8.6.1.1.1 VCO_CAP_MAN — Manual VCO Band Select This bit determines if the value of VCO_CAPCODE is just used as a starting point for the initial frequency calibration or if the VCO is forced to this value. If this is forced, it is only for diagnostic purposes. VCO_CAP_MAN IMPACT of VCO_CAPCODE 0 VCO_CAPCODE value is initial starting point for VCO digital calibration. 1 VCO_CAPCODE value is forced all the time. For diagnostic purposes only. 8.6.1.1.2 VCO_CAPCODE[7:0] — Capacitor Value for VCO Band Selection This word selects the VCO tank capacitor value that is initially used when VCO calibration is run or that is forced when VCO_CAP_MAN is set to one. The lower values correspond to less capacitance, which corresponds to a higher VCO frequency for a given VCO Core. If this word is not programmed, it is defaulted to 128. VCO_CAPCODE VCO TANK CAPACITANCE VCO FREQUENCY 0 Minimum Highest ... ... ... 255 Maximum Lowest 8.6.1.2 Register R13 Register R13 gives access to words that are used for the digital lock detect circuitry. 8.6.1.2.1 DLD_ERR_CNT[3:0] - Digital Lock Detect Error Count This is the amount of phase detector comparisons that may exceed the tolerance as specified in DLD_TOL before digital lock indicates an unlocked state. The recommended default is 4 for phase detector frequencies of 80 MHz or below; higher frequencies may require the user to experiment to optimize this value. 8.6.1.2.2 DLD_PASS_CNT[9:0] - Digital Lock Detect Success Count This value multiplied by 8 is the amount of phase detector comparison within the tolerance specified by DLD_TOL and adjusted by DLD_ERR_CNT that are necessary to cause the digital lock to indicate a locked state. The recommended value is 32 for phase detector frequencies of 80 MHz or below; higher frequencies may require the user to experiment and optimize this value based on application. 8.6.1.2.3 DLD_TOL[2:0] — Digital Lock Detect This is the tolerance that is used to compare with each phase error to decide if it is a success or a fail. Larger settings are generally recommended, but they are limited by several factors such as PFD_DLY, modulator order, and especially the phase detector frequency. DLD_TOL PHASE ERROR TOLERANCE (ns) TYPICAL PHASE DETECTOR FREQUENCY 0 1 Fpd > 130 MHz 1 1.7 80 MHz < Fpd ≤ 130 MHz 2 3 60 MHz < Fpd ≤ 80 MHz 3 6 45 MHz < Fpd ≤ 60 MHz 4 10 30 MHz 130 MHz. 1 760 ps 2 1130 ps 3 1460 ps 4 1770 ps 5 2070 ps 6 2350 ps 7 2600 ps Consider these settings for a 3rd order modulator when dithering is used. 8.6.1.7.2 FL_FRCE — Force Fastlock Conditions This bit forces the fastlock conditions on, provided that the FL_TOC word is greater than zero. FL_FRCE FASTLOCK TIMEOUT COUNTER FASTLOCK 0 Disabled >0 Fastlock engaged as long as timeout counter is counting down 0 1 0 Invalid State >0 Always Engaged 8.6.1.7.3 FL_TOC[11:0] — Fastlock Timeout Counter This word controls the timeout counter used for fastlock. FL_TOC FASTLOCK TIMEOUT COUNTER COMMENTS 0 Disabled Fastlock Disabled 1 2 x Reference Cycles 2 2 x 2 x Reference cycles ... 4095 Fastlock engaged as long as timeout counter is counting down 2 x 4095 x Reference cycles Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMX2581E 35 LMX2581E SNAS665 – MAY 2015 www.ti.com 8.6.1.7.4 FL_CPG[4:0] — Fastlock Charge Pump Gain This word determines the charge pump current that is active during fastlock. FL_CPG FASTLOCK CURRENT STATE 0 TRI-STATE 1 1X 2 2X .. ... 31 31X 8.6.1.7.5 CPG_BLEED[5:0] The CPG bleed word is for advanced users who want to get the lowest possible integer boundary spur. The impact of this word is on the order of 2 dB. For users who do not care about this, the recommendation is to default this word to zero. USER TYPE FRAC_ORDER CPG CPG BLEED RECOMMENDATION Basic User X X 0 1 36 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMX2581E LMX2581E www.ti.com SNAS665 – MAY 2015 8.6.1.8 Register R3 8.6.1.8.1 VCO_DIV[4:0] — VCO Divider Value This word determines the value of the VCO divider. Note that the this divider may be bypassed with the OUTA_MUX and OUTB_MUX words. VCO_DIV VCO DIVIDER VALUE 0 2 1 4 2 6 3 8 4 10 ... ... 18 38 20 - 31 Invalid State 8.6.1.8.2 OUTB_PWR[5:0] — RFoutB Output Power This word controls the output power for the RFoutB output. OUTB_PWR RFoutB POWER 0 Minimum ... ... 47 Maximum 48 – 63 Reserved 8.6.1.8.3 OUTA_PWR[5:0] — RFoutA Output Power This word controls the output power for the RFoutA output. OUTA_PWR RFout POWER 0 Minimum ... ... 47 Maximum 48 – 63 Reserved. 8.6.1.8.4 OUTB_PD — RFoutB Powerdown This bit powers down the RFoutB output. OUTB_PD RFoutB 0 Normal Operation 1 Powered Down 8.6.1.8.5 OUTA_PD — RFoutA Powerdown This bit powers down the RFoutA output. OUTA_PD RFoutA 0 Normal Operation 1 Powered Down Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMX2581E 37 LMX2581E SNAS665 – MAY 2015 www.ti.com 8.6.1.9 Register R2 8.6.1.9.1 OSC_2X — OSCin Doubler This bit controls the doubler for the OSCin frequency. OSC_2X OSCin DOUBLER 0 Disabled 1 Enabled 8.6.1.9.2 CPP - Charge Pump Polarity This bit sets the charge pump polarity. Note that the internal VCO has a negative tuning gain, so it should be set to negative gain with the internal VCO enabled. CPP CHARGE PUMP POLARITY 0 Positive 1 Negative (Default) 8.6.1.9.3 PLL_DEN[21:0] — PLL Fractional Denominator These words control the denominator for the PLL fraction. Note that 0 is only permissible in integer mode. PLL _ DEN PLL_DEN[21:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ... . . . . . . . . . . . . . . . . . . . . . . 4194 303 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 38 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMX2581E LMX2581E www.ti.com SNAS665 – MAY 2015 8.6.1.10 Register R1 8.6.1.10.1 CPG[4:0] — PLL Charge Pump Gain This word determines the charge pump current that used during steady state operation. CPG CHARGE PUMP CURRENT STATE 0 TRI-STATE 1 1X 2 2X .. ... 31 31X Note that if the CPG setting is 400 µA or lower, then the CPG_BLEED word needs to be set to 0. 8.6.1.10.2 VCO_SEL[1:0] - VCO Selection These words allow the user to specify which VCO the frequency calibration starts at. If uncertain, program this word to 0 to start at the lowest frequency VCO core. A programming setting of 3 (VCO 4) should not be used if switching to a frequency below 2.2 GHz. VCO_SEL VCO SELECTION 0 VCO 1 (Lowest Frequency) 1 VCO 2 2 VCO 3 3 VCO 4 (Highest Frequency) 8.6.1.10.3 FRAC_ORDER[2:0] — PLL Delta Sigma Modulator Order This word sets the order for the fractional engine. FRAC_ORDER MODULATOR ORDER 0 Integer Mode 1 1st Order Modulator 2 2nd Order Modulator 3 3rd Order Modulator 4-7 Reserved 8.6.1.10.4 PLL_R[7:0] — PLL R divider This word sets the value that divides the OSCin frequency. PLL_R PLL_R DIVIDER VALUE 0 256 1 1 (bypass) ... ... 255 255 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: LMX2581E 39 LMX2581E SNAS665 – MAY 2015 www.ti.com 8.6.1.11 Register R0 Register R0 controls the frequency of the device. Also, unless disabled by setting NO_FCAL = 1, the action of writing to the R0 register triggers a frequency calibration for the internal VCO. 8.6.1.11.1 ID - Part ID Readback When this bit is set, the part ID indicating the device is an LMX2581E is read back from the device. Consult the Feature Description for more details. ID READBACK MODE 0 Register 1 Part ID 8.6.1.11.2 FRAC_DITHER[1:0] — PLL Fractional Dithering This word sets the dithering mode. When the fractional numerator is zero, it is recommended, although not required, to set the FRAC_DITHER mode to disabled for the best possible spurs. Doing this shuts down the fractional circuitry and eliminates fractional spurs for these frequencies. This is the reason why the FRAC_DITHER word is in the R0 register, so that it can be set correctly for every frequency if this setting changes. FRAC_DITHER DITHERING MODE 0 Weak 1 Medium 2 Strong 3 Disabled 8.6.1.11.3 NO_FCAL — Disable Frequency Calibration Normally, when the R0 register is written to, a frequency calibration for the internal VCO is triggered. However, this feature may be disabled. If the frequency is changed, then this frequency calibration is necessary for the internal VCO. NO_FCAL VCO FREQUENCY CALIBRATION 0 Done upon write to R0 Register 1 Not done on write to R0 Register 8.6.1.11.4 PLL_N - PLL Feedback Divider Value This is the feedback divider value for the PLL. There are some restrictions on this depending on the modulator order. PLL_N PLL_N[11:0]