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LP5018, LP5024
SLVSEB8B – OCTOBER 2018 – REVISED OCTOBER 2018
LP50xx 18-, 24-Channel, 12-Bit, PWM Ultralow-Quiescent-Current, I2C RGB LED Drivers
1 Features
•
1
•
•
•
•
•
•
•
•
Operating Voltage Range:
– VCC Range: 2.7 V to 5.5 V
– EN, SDA, and SCL Pins Compatible With
1.8-V, 3.3-V, and 5-V Power Rails
– Output Maximum Voltage: 6 V
24 Constant-Current Sinks With High Precision
– 25.5 mA Maximum per Channel With VCC in
Full Range
– 35 mA Maximum per Channel When VCC ≥ 3.3
V
– Device-to-Device Error: ±7%; Channel-toChannel Error: ±7%
Ultralow Quiescent Current:
– Shutdown Mode: 1 µA (Maximum) With EN
Low
– Power Saving Mode: 10 µA (Typical) With EN
High and All LEDs Off for > 30 ms
Integrated 12-Bit, 29-kHz PWM Generator for
Each Channel:
– Independent Color-Mixing Register Per
Channel
– Independent Brightness-Control Register Per
RGB LED Module
– Optional Logarithmic- or Linear-Scale
Brightness Control
– Integrated 3-Phase PWM-Shifting Scheme
3 Programmable Banks (R, G, B) for Easy
Software Control of Each Color
2 External Hardware Address Pins Allow
Connecting up to 4 Devices
Broadcast Slave Address Allows Configuring
Multiple Devices Simultaneously
Auto-Increment Allows Writing or Reading
Consecutive Registers Within One Transmission
Up to 400-kHz Fast-Mode I2C Speed
2 Applications
LED Lighting, Indicator Lights, and Fun Lights for:
•
•
•
•
•
•
•
•
Smart Speaker (With Voice Assistant)
Smart Home Appliances
Video Doorbell
Electronic Smart Lock
Smoke and Heat Detector
STB and DVR
Smart Router
Handheld Device
3 Description
In smart homes and other applications that utilize
human-machine-interaction, high-performance RGB
LED drivers are required. LED animation effects such
as flashing, breathing, and chasing greatly improve
user experience, and minimal system noise is
essential.
The LP50xx device is an 18- or 24-channel constant
current sink LED driver. The LP50xx device includes
integrated color mixing and brightness control, and
pre-configuration simplifies the software coding
process. Integrated 12-bit, 29 kHz PWM generators
for each channel enable smooth, vivid color for LEDs,
and eliminate audible noise.
Device Information(1)
PART NUMBER
LP5018
PACKAGE
VQFN (32)
LP5024
BODY SIZE (NOM)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
VCC
VMCU
CVCC
VLED
VCC
OUT0
EN
OUT1
SDA
SCL
OUT2
ADDR0
MCU
ADDR1
LP5024
OUT21
VCAP
CVCAP
OUT22
IREF
RIREF
GND
OUT23
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP5018, LP5024
SLVSEB8B – OCTOBER 2018 – REVISED OCTOBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6
7.1
7.2
7.3
7.4
7.5
7.6
7.7
6
6
6
6
7
8
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 17
8.5 Programming .......................................................... 18
8.6 Register Maps ........................................................ 22
9
Application and Implementation ........................ 38
9.1 Application Information............................................ 38
9.2 Typical Application ................................................. 38
10 Power Supply Recommendations ..................... 41
11 Layout................................................................... 41
11.1 Layout Guidelines ................................................. 41
11.2 Layout Examples................................................... 42
12 Device and Documentation Support ................. 44
12.1
12.2
12.3
12.4
12.5
12.6
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
44
44
44
44
44
44
13 Mechanical, Packaging, and Orderable
Information ........................................................... 45
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (October 2018) to Revision B
Page
•
Added % after 100 in Parameter for IERR_DD and IERR_CC under OUTPUT STAGE................................................................. 7
•
Changed value of "KIREF = 100" to "KIREF = 105" .................................................................................................................. 16
Changes from Original (October 2018) to Revision A
•
2
Page
first release of production-data data sheet ............................................................................................................................. 1
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SLVSEB8B – OCTOBER 2018 – REVISED OCTOBER 2018
5 Description (continued)
The LP50xx device controls each LED output with a 12-bit PWM resolution at 29-kHz switching frequency, which
helps achieve a smooth dimming effect and eliminates audible noise. The independent color mixing and intensity
control registers make the software coding straightforward. When targeting a fade-in, fade-out type breathing
effect, the global R, G, B bank control reduces the microcontroller loading significantly. The LP50xx device also
implements a PWM phase-shifting function to help reduce the input power budget when LEDs turn on
simultaneously.
The LP50xx device implements an automatic power-saving mode to achieve ultralow quiescent current. When
channels are all off for 30 ms, the device total power consumption is down to 10 µA, which makes the LP50xx
device a potential choice for battery-powered end equipment.
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SLVSEB8B – OCTOBER 2018 – REVISED OCTOBER 2018
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6 Pin Configuration and Functions
VCAP
IREF
EN
SCL
SDA
VCC
ADDR1
ADDR0
32
31
30
29
28
27
26
25
LP5018 RSM Package
32-Pin VQFN With Exposed Thermal Pad
Top View
OUT0
1
24
NC
OUT1
2
23
NC
OUT2
3
22
NC
OUT3
4
21
NC
OUT4
5
20
NC
OUT5
6
19
NC
OUT6
7
18
OUT17
OUT7
8
17
OUT16
9
10
11
12
13
14
15
16
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
Exposed Thermal Pad (GND)
Not to scale
VCAP
IREF
EN
SCL
SDA
VCC
ADDR1
ADDR0
32
31
30
29
28
27
26
25
LP5024 RSM Package
32-Pin VQFN With Exposed Thermal Pad
Top View
OUT0
1
24
OUT23
OUT1
2
23
OUT22
OUT2
3
22
OUT21
OUT3
4
21
OUT20
Exposed Thermal Pad
(GND)
4
16
OUT16
OUT15
17
15
8
OUT14
OUT7
14
OUT17
OUT13
18
13
7
OUT12
OUT6
12
OUT18
OUT11
19
11
6
OUT10
OUT5
10
OUT19
OUT9
20
9
5
OUT8
OUT4
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Not to scale
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SLVSEB8B – OCTOBER 2018 – REVISED OCTOBER 2018
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
LP5018
LP5024
ADDR0
25
25
—
I2C slave-address selection pin. This pin must not be left floating.
ADDR1
26
26
—
I2C slave-address selection pin. This pin must not be left floating.
EN
30
30
I
IREF
31
31
—
Output current-reference global-setting pin
19, 20, 21,
22, 23, 24
—
—
No internal connection
OUT0
1
1
O
Current sink output 0. If not used, this pin can be left floating.
OUT1
2
2
O
Current sink output 1. If not used, this pin can be left floating.
OUT2
3
3
O
Current sink output 2. If not used, this pin can be left floating.
OUT3
4
4
O
Current sink output 3. If not used, this pin can be left floating.
OUT4
5
5
O
Current sink output 4. If not used, this pin can be left floating.
OUT5
6
6
O
Current sink output 5. If not used, this pin can be left floating.
OUT6
7
7
O
Current sink output 6. If not used, this pin can be left floating.
OUT7
8
8
O
Current sink output 7. If not used, this pin can be left floating.
OUT8
9
9
O
Current sink output 8. If not used, this pin can be left floating.
OUT9
10
10
O
Current sink output 9. If not used, this pin can be left floating.
OUT10
11
11
O
Current sink output 10. If not used, this pin can be left floating.
OUT11
12
12
O
Current sink output 11. If not used, this pin can be left floating.
OUT12
13
13
O
Current sink output 12. If not used, this pin can be left floating.
OUT13
14
14
O
Current sink output 13. If not used, this pin can be left floating.
OUT14
15
15
O
Current sink output 14. If not used, this pin can be left floating.
OUT15
16
16
O
Current sink output 15. If not used, this pin can be left floating.
OUT16
17
17
O
Current sink output 16. If not used, this pin can be left floating.
OUT17
18
18
O
Current sink output 17. If not used, this pin can be left floating.
OUT18
—
19
O
Current sink output 18. If not used, this pin can be left floating.
OUT19
—
20
O
Current sink output 19. If not used, this pin can be left floating.
OUT20
—
21
O
Current sink output 20. If not used, this pin can be left floating.
OUT21
—
22
O
Current sink output 21. If not used, this pin can be left floating.
OUT22
—
23
O
Current sink output 22. If not used, this pin can be left floating.
OUT23
—
24
O
Current sink output 23. If not used, this pin can be left floating.
SCL
29
29
I
I2C bus clock line. If not used, this pin must be connected to GND or VCC.
SDA
28
28
I/O
I2C bus data line. If not used, this pin must be connected to GND or VCC.
VCAP
32
32
—
Internal LDO output pin, this pin must be connected to a 1-µF capacitor to
GND. Place the capacitor as close to the device as possible.
VCC
27
27
I
GND
GND
NC
—
Chip enable input pin
Input power.
Exposed thermal pad also serves the ground pin for the device.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted) (1)
MIN
MAX
Voltage on EN, IREF, OUTx, SCL, SDA, VCC
–0.3
6
V
Voltage on ADDRx
–0.3
VCC+0.3
V
Voltage on VCAP
–0.3
2
V
Continuous power dissipation
UNIT
Internally limited
Junction temperature, TJ-MAX
–40
125
°C
Storage temperature, Tstg
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±1500
V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V
may actually have higher performance.
7.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)
MIN
MAX
2.7
5.5
V
Voltage on OUTx
0
5.5
V
Voltage on ADDRx, EN, SDA, SCL
0
5.5
V
Operating ambient temperature, TA
–40
85
°C
Input voltage on VCC
UNIT
7.4 Thermal Information
LP5018 or LP5024
THERMAL METRIC
(1)
RSM (QFN)
UNIT
32 PINS
RθJA
Junction-to-ambient thermal resistance
36.4
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
34.8
°C/W
RθJB
Junction-to-board thermal resistance
15.9
°C/W
ψJT
Junction-to-top characterization parameter
0.9
°C/W
ψJB
Junction-to-board characterization parameter
16
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
6.3
°C/W
(1)
6
For more information about traditional and new thermal metrics, see Semiconductor and ICPackage Thermal Metrics .
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7.5 Electrical Characteristics
over operating ambient temperature range (–40°C < TA tPSM
6
10
µA
VUVR
Undervoltage restart
VVCC rising
2.5
V
VUVF
Undervoltage shutdown
VVCC falling
VUV_HYS
Undervoltage shutdown hysteresis
IVCC
Shutdown supply current
2
µA
V
0.2
V
OUTPUT STAGE (OUTx)
Maximum sink current
(OUT0–OUTx) (For LP5024, x = 23.
For LP5018, x = 17.)
VVCC in full range,
Max_Current_Option = 0 (bit), PWM
= 100%
Maximum sink current
(OUT0–OUTx) (For LP5024, x = 23.
For LP5018, x = 17.)
VVCC ≥ 3.3 V, Max_Current_Option
= 1 (bit), PWM = 100%
Internal sink current limit
(OUT0–OUTx) (For LP5024, x = 23.
For LP5018, x = 17.)
VVCC in full range,
Max_Current_Option = 0 (bit), VIREF
=0V
35
Internal sink current limit
(OUT0–OUTx) (For LP5024, x = 23.
For LP5018, x = 17.)
VVCC ≥ 3.3V,
Max_Current_Option=1 (bit), VIREF =
0V
40
Ilkg
Leakage current (OUT0–OUTx) (For
LP5024, x = 23. For LP5018, x =
17.)
PWM = 0%
IERR_DD
Device to device current error,
IERR_DD=(IAVE-ISET)/ISET×100%
All channels' current set to 10 mA.
PWM = 100%. Already includes the
VIREF and KIREF tolerance
–7%
7%
IERR_CC
Channel to channel current error,
IERR_CC=(IOUTX-IAVE)/IAVE×100%
All channels' current set to 10 mA.
PWM = 100%. Already includes the
VIREF and KIREF tolerance
–7%
7%
VIREF
IREF voltage
0.7
KIREF
IREF ratio
105
ƒPWM
PWM switching frequency
IMAX
ILIM
VSAT
Output saturation voltage
25.5
mA
35
55
80
mA
21
VVCC in full range,
Max_Current_Option = 0 (bit), output
current set to 20 mA, the voltage
when the LED current has dropped
5%
75
120
0.1
1
V
29
0.25
µA
kHz
0.35
V
VVCC ≥ 3.3 V, Max_Current_Option
= 1 (bit), output current set to 20
mA, the voltage when the LED
current has dropped 5%
0.3
0.4
LOGIC INPUTS (EN, SCL, SDA, ADDRx)
VIL
Low level input voltage
VIH
High level input voltage
ILOGIC
Input current
VSDA
SDA output low level
0.4
1.4
V
V
–1
IPULLUP = 5 mA
1
µA
0.4
V
PROTECTION CIRCUITS
T(TSD)
Thermal-shutdown junction
temperature
160
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Electrical Characteristics (continued)
over operating ambient temperature range (–40°C < TA30 ms. Almost all analog blocks are
powered down in power-save mode. If any I2C command to the device occurs, the LP50xx device returns to
NORMAL mode.
16
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8.3.5 Protection Features
8.3.5.1 Thermal Shutdown
The LP50xx device implements a thermal shutdown mechanism to protect the device from damage due to
overheating. When the junction temperature rises to 160°C (typical), the device switches into shutdown mode.
The LP50xx device releases thermal shutdown when the junction temperature of the device is reduced to 145°C
(typical).
8.3.5.2 UVLO
The LP50xx device has an internal comparator that monitors the voltage at VCC. When VCC is below VUVF, reset
is active and the LP50xx device is in the INITIALIZATION state.
8.4 Device Functional Modes
VCC Power Up
EN = L
SHUTDOWN
From all states
EN = H
RESET = FF or UVLO = H
From all states
INITIALIZATION
STANDBY
Chip_EN = 1
Chip_EN = 0
TSD=H
I2C Command
POWER SAVE
THERMAL
SHUTDOWN
NORMAL
Power_Save_EN =1 and
All LEDs off > 30ms
TSD=L
Figure 15. Functional Modes
•
•
•
•
•
•
INITIALIZATION: The device enters into INITIALIZATION mode when EN = H. In this mode, all the registers
are reset. Entry can also be from any state, if the RESET (register) = FFh or UVLO is active.
NORMAL: The device enters the NORMAL mode when Chip_EN (register) = 1. ICC is 10 mA (typ.).
POWER SAVE: The device automatically enters the POWER SAVE mode when Power_Save_EN (register) =
1 and all the LEDs are off for a duration of >30 ms. In POWER SAVE mode, analog blocks are disabled to
minimize power consumption, but the registers retain the data and keep it available via I2C. ICC is 10 µA (typ.).
In case of any I2C command to this device, it returns to the NORMAL mode.
SHUTDOWN: The device enters into SHUTDOWN mode from all states on VCC power up or when EN = L.
ICC is < 1 µA (max).
STANDBY: The device enters the STANDBY mode when Chip_EN (register) = 0. In this mode, all the OUTx
pins are shut down, but the registers retain the data and keep it available via I2C. STANDBY is the lowpower-consumption mode, when all circuit functions are disabled. ICC is 10 µA (typ.).
THERMAL SHUTDOWN: The device automatically enters the THERMAL SHUTDOWN mode when the
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Device Functional Modes (continued)
junction temperature exceeds 160°C (typical). In this mode, all the OUTx outputs are shut down. If the
junction temperature decreases below 145°C (typical), the device returns to the NORMAL mode.
8.5 Programming
8.5.1 I2C Interface
The I2C-compatible two-wire serial interface provides access to the programmable functions and registers on the
device. This protocol uses a two-wire interface for bidirectional communications between the devices connected
to the bus. The two interface lines are the serial data line (SDA) and the serial clock line (SCL). Every device on
the bus is assigned a unique address and acts as either a master or a slave depending on whether it generates
or receives the serial clock, SCL. The SCL and SDA lines should each have a pullup resistor placed somewhere
on the line and remain HIGH even when the bus is idle.
8.5.1.1 Data Validity
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, the state
of the data line can only be changed when the clock signal is LOW.
Figure 16. Data Validity
8.5.1.2 Start and Stop Conditions
START and STOP conditions classify the beginning and the end of the data transfer session. A START condition
is defined as the SDA signal transitioning from HIGH to LOW while the SCL line is HIGH. A STOP condition is
defined as the SDA transitioning from LOW to HIGH while SCL is HIGH. The bus master always generates
START and STOP conditions. The bus is considered to be busy after a START condition and free after a STOP
condition. During data transmission, the bus master can generate repeated START conditions. First START and
repeated START conditions are functionally equivalent.
Figure 17. Start and Stop Conditions
18
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Programming (continued)
8.5.1.3 Transferring Data
Every byte put on the SDA line must be eight bits long, with the most-significant bit (MSB) being transferred first.
Each byte of data must be followed by an acknowledge bit. The acknowledge-related clock pulse is generated by
the master. The master releases the SDA line (HIGH) during the acknowledge clock pulse. The device pulls
down the SDA line during the ninth clock pulse, signifying an acknowledge. The device generates an
acknowledge after each byte has been received.
There is one exception to the acknowledge-after-every-byte rule. When the master is the receiver, it must
indicate to the transmitter an end of data by not acknowledging (negative acknowledge) the last byte clocked out
of the slave. This negative acknowledge still includes the acknowledge clock pulse (generated by the master),
but the SDA line is not pulled down.
After the START condition, the bus master sends a chip address. This address is seven bits long followed by an
eighth bit which is a data direction bit (READ or WRITE). For the eighth bit, a 0 indicates a WRITE, and a 1
indicates a READ. The second byte selects the register to which the data is written. The third byte contains data
to write to the selected register.
Figure 18. Acknowledge and Not Acknowledge on I2C Bus
8.5.1.4 I2C Slave Addressing
The device slave address is defined by connecting GND or VCC to the ADDR0 and ADDR1 pins. A total of four
independent slave addresses can be realized by combinations when GND or VCC is connected to the ADDR0
and ADDR1 pins (see Table 2 and Table 3).
The device responds to a broadcast slave address regardless of the setting of the ADDR0 and ADDR1 pins.
Global writes to the broadcast address can be used for configuring all devices simultaneously. The device
supports global read using a broadcast address; however, the data read is only valid if all devices on the I2C bus
contain the same value in the addressed register.
Table 2. Slave-Address Combinations
SLAVE ADDRESS
ADDR1
ADDR0
GND
GND
010 1000
GND
VCC
010 1001
VCC
GND
010 1010
VCC
VCC
010 1011
INDEPENDENT
BROADCAST
011 1100
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Table 3. Chip Address
SLAVE ADDRESS
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Independent
0
1
0
1
0
ADDR1
ADDR0
1 or 0
Broadcast
0
1
1
1
1
0
0
1 or 0
8.5.1.5 Control-Register Write Cycle
• The master device generates a start condition.
• The master device sends the slave address (7 bits) and the data direction bit (R/W = 0).
• The slave device sends an acknowledge signal if the slave address is correct.
• The master device sends the control register address (8 bits).
• The slave device sends an acknowledge signal.
• The master device sends the data byte to be written to the addressed register.
• The slave device sends an acknowledge signal.
• If the master device sends further data bytes, the control register address of the slave is incremented by 1
after the acknowledge signal. To reduce program load time, the device supports address auto incrementation.
The register address is incremented after each 8 data bits.
• The write cycle ends when the master device creates a stop condition.
Figure 19. Write Cycle
8.5.1.6 Control-Register Read Cycle
• The master device generates a start condition.
• The master device sends the slave address (7 bits) and the data direction bit (R/W = 0).
• The slave device sends an acknowledge signal if the slave address is correct.
• The master device sends the control register address (8 bits).
• The slave device sends an acknowledge signal.
• The master device generates a repeated-start condition.
• The master device sends the slave address (7 bits) and the data direction bit (R/W = 1).
• The slave device sends an acknowledge signal if the slave address is correct.
• The slave device sends the data byte from the addressed register.
• If the master device sends an acknowledge signal, the control-register address is incremented by 1. The
slave device sends the data byte from the addressed register. To reduce program load time, the device
supports address auto incrementation. The register address is incremented after each 8 data bits.
• The read cycle ends when the master device does not generate an acknowledge signal after a data byte and
generates a stop condition.
Figure 20. Read Cycle
20
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8.5.1.7 Auto-Increment Feature
The auto-increment feature allows writing or reading several consecutive registers within one transmission. For
example, when an 8-bit word is sent to the device, the internal address index counter is incremented by 1, and
the next register is written. The auto-increment feature is enabled by default and can be disabled by setting the
Auto_Incr_EN bit = 0 in the DEVICE_CONFIG1 register. The auto-increment feature is applied for the full register
address from 0h to FFh.
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8.6 Register Maps
Table 4 lists the memory-mapped registers of the device.
Table 4. Register Maps
REGISTER
NAME
ADDR
TYPE
D7
D6
DEVICE_
CONFIG0
00h
R/W
RESERVED
Chip_EN
DEVICE_
CONFIG1
01h
R/W
LED_CONFIG0
02h
BANK_
BRIGHTNESS
D4
D3
D2
D1
D0
RESERVED
Log_Scale_EN
Power_Save_
EN
Auto_Incr_EN
PWM_
Dithering_EN
DEFAULT
00h
Max_Current_
Option
LED_Global Off
3Ch
R/W
LED7_Bank_EN LED6_Bank_EN
(Only for
(Only for
LED5_Bank_EN LED4_Bank_EN LED3_Bank_EN LED2_Bank_EN LED1_Bank_EN LED0_Bank_EN
LP5024)
LP5024)
00h
03h
R/W
Bank_Brightness
FFh
BANK_A_
COLOR
04h
R/W
Bank_A_Color
00h
BANK_B_
COLOR
05h
R/W
Bank_B_Color
00h
BANK_C_
COLOR
06h
R/W
Bank_C_Color
00h
LED0_
BRIGHTNESS
07h
R/W
LED0_Brightness
FFh
LED1_
BRIGHTNESS
08h
R/W
LED1_Brightness
FFh
LED2_
BRIGHTNESS
09h
R/W
LED2_Brightness
FFh
LED3_
BRIGHTNESS
0Ah
R/W
LED3_Brightness
FFh
LED4_
BRIGHTNESS
0Bh
R/W
LED4_Brightness
FFh
LED5_
BRIGHTNESS
0Ch
R/W
LED5_Brightness
FFh
LED6_
BRIGHTNESS
0Dh
R/W
LED6_Brightness
(Only for LP5024)
FFh
LED7_
BRIGHTNESS
0Eh
R/W
LED7_Brightness
(Only for LP5024)
FFh
OUT0_COLOR
0Fh
R/W
OUT0_Color
00h
OUT1_COLOR
10h
R/W
OUT1_Color
00h
OUT2_COLOR
11h
R/W
OUT2_Color
00h
OUT3_COLOR
12h
R/W
OUT3_Color
00h
22
RESERVED
D5
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Register Maps (continued)
Table 4. Register Maps (continued)
REGISTER
NAME
ADDR
TYPE
OUT4_COLOR
13h
R/W
OUT4_Color
00h
OUT5_COLOR
14h
R/W
OUT5_Color
00h
OUT6_COLOR
15h
R/W
OUT6_Color
00h
OUT7_COLOR
16h
R/W
OUT7_Color
00h
OUT8_COLOR
17h
R/W
OUT8_Color
00h
OUT9_COLOR
18h
R/W
OUT9_Color
00h
OUT10_COLOR
19h
R/W
OUT10_Color
00h
OUT11_COLOR
1Ah
R/W
OUT11_Color
00h
OUT12_COLOR
1Bh
R/W
OUT12_Color
00h
OUT13_COLOR
1Ch
R/W
OUT13_Color
00h
OUT14_COLOR
1Dh
R/W
OUT14_Color
00h
OUT15_COLOR
1Eh
R/W
OUT15_Color
00h
OUT16_COLOR
1Fh
R/W
OUT16_Color
00h
OUT17_COLOR
20h
R/W
OUT17_Color
00h
00h
D7
D6
D5
D4
D3
D2
D1
D0
DEFAULT
OUT18_COLOR
21h
R/W
OUT18_Color
(Only for LP5024)
OUT19_COLOR
22h
R/W
OUT19_Color
(Only for LP5024)
00h
OUT20_COLOR
23h
R/W
OUT20_Color
(Only for LP5024)
00h
OUT21_COLOR
24h
R/W
OUT21_Color
(Only for LP5024)
00h
OUT22_COLOR
25h
R/W
OUT22_Color
(Only for LP5024)
00h
OUT23_COLOR
26h
R/W
OUT23_Color
(Only for LP5024)
00h
RESET
27h
W
Reset
00h
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Table 5. Access Type Codes
ACCESS TYPE
CODE
DESCRIPTION
Read Type
R
R
Read
W
Write
Write Type
W
Reset or Default Value
-n
Value after reset or the default
value
8.6.1 DEVICE_CONFIG0 (Address = 0h) [reset = 0h]
DEVICE_CONFIG0 is shown in Figure 21 and described in Table 6.
Return to Table 4.
Figure 21. DEVICE_CONFIG0 Register
7
RESERVED
R/W-0h
6
Chip_EN
R/W-0h
5
4
3
2
1
0
RESERVED
R/W-0h
Table 6. DEVICE_CONFIG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R/W
0h
Reserved
6
Chip_EN
R/W
0h
1 = LP50xx enabled
0 = LP50xx not enabled
RESERVED
R/W
0h
Reserved
5–0
8.6.2 DEVICE_CONFIG1 (Address = 1h) [reset = 3Ch]
DEVICE_CONFIG1 is shown in Figure 22 and described in Table 7.
Return to Table 4.
Figure 22. DEVICE_CONFIG1 Register
7
RESERVED
6
5
Log_Scale_EN
R/W-0h
R/W-1h
4
Power_Save_E
N
R/W-1h
3
Auto_Incr_EN
R/W-1h
2
1
0
PWM_Dithering Optional_Headr LED_Global Off
_EN
oom
R/W-1h
R/W-0h
R/W-0h
Table 7. DEVICE_CONFIG1 Register Field Descriptions
24
Bit
Field
Type
Reset
Description
7–6
RESERVED
R/W
0h
Reserved
5
Log_Scale_EN
R/W
1h
1 = Logarithmic scale dimming curve enabled
0 = Linear scale dimming curve enabled
4
Power_Save_EN
R/W
1h
1 = Automatic power-saving mode enabled
0 = Automatic power-saving mode not enabled
3
Auto_Incr_EN
R/W
1h
1 = Automatic increment mode enabled
0 = Automatic increment mode not enabled
2
PWM_Dithering_EN
R/W
1h
1 = PWM dithering mode enabled
0 = PWM dithering mode not enabled
1
Max_Current_Option
R/W
0h
1 = Output maximum current IMAX = 35 mA.
0 = Output maximum current IMAX = 25.5 mA.
0
LED_Global Off
R/W
0h
1 = Shut down all LEDs
0 = Normal operation
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8.6.3 LED_CONFIG0 (Address = 2h) [reset = 00h]
LED_CONFIG0 is shown in Figure 23 and described in Table 8.
Return to Table 4.
Figure 23. LED_CONFIG0 Register
7
LED7_Bank_E
N
R/W-0h
6
LED6_Bank_E
N
R/W-0h
5
LED5_Bank_E
N
R/W-0h
4
LED4_Bank_E
N
R/W-0h
3
LED3_Bank_E
N
R/W-0h
2
LED2_Bank_E
N
R/W-0h
1
LED1_Bank_E
N
R/W-0h
0
LED0_Bank_E
N
R/W-0h
Table 8. LED_CONFIG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7
LED7_Bank_EN
R/W
0h
1 = LED7 bank control mode enabled
0 = LED7 independent control mode enabled
6
LED6_Bank_EN
R/W
0h
1 = LED6 bank control mode enabled
0 = LED6 independent control mode enabled
5
LED5_Bank_EN
R/W
0h
1 = LED5 bank control mode enabled
0 = LED5 independent control mode enabled
4
LED4_Bank_EN
R/W
0h
1 = LED4 bank control mode enabled
0 = LED4 independent control mode enabled
3
LED3_Bank_EN
R/W
0h
1 = LED3 bank control mode enabled
0 = LED3 Independent control mode enabled
2
LED2_Bank_EN
R/W
0h
1 = LED2 bank control mode enabled
0 = LED2 independent control mode enabled
1
LED1_Bank_EN
R/W
0h
1 = LED1 bank control mode enabled
0 = LED1 independent control mode enabled
0
LED0_Bank_EN
R/W
0h
1 = LED0 bank control mode enabled
0 = LED0 independent control mode enabled
8.6.4 BANK_BRIGHTNESS (Address = 3h) [reset = FFh]
BANK_BRIGHTNESS is shown in Figure 24 and described in Table 9.
Return to Table 4.
Figure 24. BANK_BRIGHTNESS Register
7
6
5
4
3
Bank_Brightness
R/W-FFh
2
1
0
Table 9. BANK_BRIGHTNESS Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
Bank_Brightness
R/W
FFh
FFh = 100% of full brightness
...
80h = 50% of full brightness
...
00h = 0% of full brightness
8.6.5 BANK_A_COLOR (Address = 4h) [reset = 00h]
BANK_A_COLOR is shown in Figure 25 and described in Table 10.
Return to Table 4.
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Figure 25. BANK_A_COLOR Register
7
6
5
4
3
2
1
0
Bank_A_Color
R/W-0h
Table 10. BANK_A_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
Bank_A_Color
R/W
0h
FFh = The color mixing percentage is 100%.
...
80h = The color mixing percentage is 50%.
...
00h = The color mixing percentage is 0%.
8.6.6 BANK_B_COLOR (Address = 5h) [reset = 00h]
BANK_B_COLOR is shown in Figure 26 and described in Table 11.
Return to Table 4.
Figure 26. BANK_B_COLOR Register
7
6
5
4
3
2
1
0
Bank_B_Color
R/W-0h
Table 11. BANK_B_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
Bank_B_Color
R/W
0h
FFh = The color mixing percentage is 100%.
...
80h = The color mixing percentage is 50%.
...
00h = The color mixing percentage is 0%.
8.6.7 BANK_C_COLOR (Address = 6h) [reset = 00h]
BANK_C_COLOR is shown in Figure 27 and described in Table 12.
Return to Table 4.
Figure 27. BANK_C_COLOR Register
7
6
5
4
3
2
1
0
Bank_C_Color
R/W-0h
Table 12. BANK_C_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
Bank_C_Color
R/W
0h
FFh = The color mixing percentage is 100%.
...
80h = The color mixing percentage is 50%.
...
00h = The color mixing percentage is 0%.
8.6.8 LED0_BRIGHTNESS (Address = 7h) [reset = FFh]
LED0_BRIGHTNESS is shown in Figure 28 and described in Table 13.
Return to Table 4.
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Figure 28. LED0_BRIGHTNESS Register
7
6
5
4
3
LED0_Brightness
R/W-FFh
2
1
0
1
0
1
0
Table 13. LED0_BRIGHTNESS Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
LED0_Brightness
R/W
FFh
FFh = 100% of full intensity
...
80h = 50% of full intensity
...
00h = 0% of full intensity
8.6.9 LED1_BRIGHTNESS (Address = 8h) [reset = FFh]
LED1_BRIGHTNESS is shown in Figure 29 and described in Table 14.
Return to Table 4.
Figure 29. LED1_BRIGHTNESS Register
7
6
5
4
3
LED1_Brightness
R/W-FFh
2
Table 14. LED1_BRIGHTNESS Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
LED1_Brightness
R/W
FFh
FFh = 100% of full intensity
...
80h = 50% of full intensity
...
00h = 0% of full intensity
8.6.10 LED2_BRIGHTNESS (Address = 9h) [reset = FFh]
LED2_BRIGHTNESS is shown in Figure 30 and described in Table 15.
Return to Table 4.
Figure 30. LED2_BRIGHTNESS Register
7
6
5
4
3
LED2_Brightness
R/W-FFh
2
Table 15. LED2_BRIGHTNESS Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
LED2_Brightness
R/W
FFh
FFh = 100% of full intensity
...
80h = 50% of full intensity
...
00h = 0% of full intensity
8.6.11 LED3_BRIGHTNESS (Address = 0Ah) [reset = FFh]
LED3_BRIGHTNESS is shown in Figure 31 and described in Table 16.
Return to Table 4.
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Figure 31. LED3_BRIGHTNESS Register
7
6
5
4
3
LED3_Brightness
R/W-FFh
2
1
0
1
0
1
0
Table 16. LED3_BRIGHTNESS Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
LED3_Brightness
R/W
FFh
FFh = 100% of full intensity
...
80h = 50% of full intensity
...
00h = 0% of full intensity
8.6.12 LED4_BRIGHTNESS (Address = 0Bh) [reset = FFh]
LED4_BRIGHTNESS is shown in Figure 32 and described in Table 17.
Return to Table 4.
Figure 32. LED4_BRIGHTNESS Register
7
6
5
4
3
LED4_Brightness
R/W-FFh
2
Table 17. LED4_BRIGHTNESS Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
LED4_Brightness
R/W
FFh
FFh = 100% of full intensity
...
80h = 50% of full intensity
...
00h = 0% of full intensity
8.6.13 LED5_BRIGHTNESS (Address = 0Ch) [reset = FFh]
LED5_BRIGHTNESS is shown in Figure 33 and described in Table 18.
Return to Table 4.
Figure 33. LED5_BRIGHTNESS Register
7
6
5
4
3
LED5_Brightness
R/W-FFh
2
Table 18. LED5_BRIGHTNESS Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
LED5_Brightness
R/W
FFh
FFh = 100% of full intensity
...
80h = 50% of full intensity
...
00h = 0% of full intensity
8.6.14 LED6_BRIGHTNESS (Address = 0Dh) [reset = FFh]
LED6_BRIGHTNESS is shown in Figure 34 and described in Table 19.
Return to Table 4.
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Figure 34. LED6_BRIGHTNESS Register
7
6
5
4
3
LED6_Brightness
R/W-FFh
2
1
0
1
0
1
0
Table 19. LED6_BRIGHTNESS Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
LED6_Brightness
R/W
FFh
FFh = 100% of full intensity
...
80h = 50% of full intensity
...
00h = 0% of full intensity
8.6.15 LED7_BRIGHTNESS (Address = 0Eh) [reset = FFh]
LED7_BRIGHTNESS is shown in Figure 35 and described in Table 20.
Return to Table 4.
Figure 35. LED7_BRIGHTNESS Register
7
6
5
4
3
LED7_Brightness
R/W-FFh
2
Table 20. LED7_BRIGHTNESS Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
LED7_Brightness
R/W
FFh
FFh = 100% of full intensity
...
80h = 50% of full intensity
...
00h = 0% of full intensity
8.6.16 OUT0_COLOR (Address = 0Fh) [reset = 00h]
OUT0_COLOR is shown in Figure 36 and described in Table 21.
Return to Table 4.
Figure 36. OUT0_COLOR Register
7
6
5
4
3
2
OUT0_Color
R/W-00h
Table 21. OUT0_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
OUT0_Color
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.17 OUT1_COLOR (Address = 10h) [reset = 00h]
OUT1_COLOR is shown in Figure 37 and described in Table 22.
Return to Table 4.
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Figure 37. OUT1_COLOR Register
7
6
5
4
3
2
1
0
OUT1_Color
R/W-00h
Table 22. OUT1_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
OUT1_Color
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.18 OUT2_COLOR (Address = 11h) [reset = 00h]
OUT2_COLOR is shown in Figure 38 and described in Table 23.
Return to Table 4.
Figure 38. OUT2_COLOR Register
7
6
5
4
3
2
1
0
OUT2_Color
R/W-00h
Table 23. OUT2_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
OUT2_Color
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.19 OUT3_COLOR (Address = 12h) [reset = 00h]
OUT3_COLOR is shown in Figure 39 and described in Table 24.
Return to Table 4.
Figure 39. OUT3_COLOR Register
7
6
5
4
3
2
1
0
OUT3_Color
R/W-00h
Table 24. OUT3_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
OUT3_Color
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.20 OUT4_COLOR (Address = 13h) [reset = 00h]
OUT4_COLOR is shown in Figure 40 and described in Table 25.
Return to Table 4.
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Figure 40. OUT4_COLOR Register
7
6
5
4
3
2
1
0
OUT4_Color
R/W-00h
Table 25. OUT4_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
OUT4_Color
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.21 OUT5_COLOR (Address = 14h) [reset = 00h]
OUT5_COLOR is shown in Figure 41 and described in Table 26.
Return to Table 4.
Figure 41. OUT5_COLOR Register
7
6
5
4
3
2
1
0
OUT5_Color
R/W-00h
Table 26. OUT5_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
OUT5_Color
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.22 OUT6_COLOR (Address = 15h) [reset = 00h]
OUT6_COLOR is shown in Figure 42 and described in Table 27.
Return to Table 4.
Figure 42. OUT6_COLOR Register
7
6
5
4
3
2
1
0
OUT6_Color
R/W-00h
Table 27. OUT6_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
OUT6_Color
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.23 OUT7_COLOR (Address = 16h) [reset = 00h]
OUT7_COLOR is shown in Figure 43 and described in Table 28.
Return to Table 4.
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Figure 43. OUT7_COLOR Register
7
6
5
4
3
2
1
0
OUT7_Color
R/W-00h
Table 28. OUT7_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
OUT7_Color
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.24 OUT8_COLOR (Address = 17h) [reset = 00h]
OUT8_COLOR is shown in Figure 44 and described in Table 29.
Return to Table 4.
Figure 44. OUT8_COLOR Register
7
6
5
4
3
2
1
0
OUT8_Color
R/W-00h
Table 29. OUT8_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
OUT8_Color
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.25 OUT9_COLOR (Address = 18h) [reset = 00h]
OUT9_COLOR is shown in Figure 45 and described in Table 30.
Return to Table 4.
Figure 45. OUT9_COLOR Register
7
6
5
4
3
2
1
0
OUT9_Color
R/W-00h
Table 30. OUT9_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
OUT9_Color
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.26 OUT10_COLOR (Address = 19h) [reset = 00h]
OUT10_COLOR is shown in Figure 46 and described in Table 31.
Return to Table 4.
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Figure 46. OUT10_COLOR Register
7
6
5
4
3
2
1
0
OUT10_Color
R/W-00h
Table 31. OUT10_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
OUT10_Color
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.27 OUT11_COLOR (Address = 1Ah) [reset = 00h]
OUT11_COLOR is shown in Figure 47 and described in Table 32.
Return to Table 4.
Figure 47. OUT11_COLOR Register
7
6
5
4
3
2
1
0
OUT11_Color
R/W-00h
Table 32. OUT11_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
OUT11_Color
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.28 OUT12_COLOR (Address = 1Bh) [reset = 00h]
OUT12_COLOR is shown in Figure 48 and described in Table 33.
Return to Table 4.
Figure 48. OUT12_COLOR Register
7
6
5
4
3
2
1
0
OUT12_Color
R/W-00h
Table 33. OUT12_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
OUT12_Color
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.29 OUT13_COLOR (Address = 1Ch) [reset = 00h]
OUT13_COLOR is shown in Figure 49 and described in Table 34.
Return to Table 4.
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Figure 49. OUT13_COLOR Register
7
6
5
4
3
2
1
0
OUT13_Color
R/W-00h
Table 34. OUT13_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
OUT13_Color
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.30 OUT14_COLOR (Address = 1Dh) [reset = 00h]
OUT14_COLOR is shown in Figure 50 and described in Table 35.
Return to Table 4.
Figure 50. OUT14_COLOR Register
7
6
5
4
3
2
1
0
OUT14_Color
R/W-00h
Table 35. OUT14_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
OUT14_Color
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.31 OUT15_COLOR (Address = 1Eh) [reset = 00h]
OUT15_COLOR is shown in Figure 51 and described in Table 36.
Return to Table 4.
Figure 51. OUT15_COLOR Register
7
6
5
4
3
2
1
0
OUT15_Color
R/W-00h
Table 36. OUT15_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
OUT15_Color
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.32 OUT16_COLOR (Address = 1Fh) [reset = 00h]
OUT16_COLOR is shown in Figure 52 and described in Table 37.
Return to Table 4.
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Figure 52. OUT16_COLOR Register
7
6
5
4
3
2
1
0
OUT16_Color
R/W-00h
Table 37. OUT16_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
OUT16_Color
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.33 OUT17_COLOR (Address = 20h) [reset = 00h]
OUT17_COLOR is shown in Figure 53 and described in Table 38.
Return to Table 4.
Figure 53. OUT17_COLOR Register
7
6
5
4
3
2
1
0
OUT17_Color
R/W-00h
Table 38. OUT17_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
OUT17_Color
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.34 OUT18_COLOR (Address = 21h) [reset = 00h]
OUT18_COLOR is shown in Figure 54 and described in Table 39.
Return to Table 4.
Figure 54. OUT18_COLOR Register
7
6
5
4
3
2
1
0
OUT18_Color
R/W-00h
Table 39. OUT18_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
OUT18_Color
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.35 OUT19_COLOR (Address = 22h) [reset = 00h]
OUT19_COLOR is shown in Figure 55 and described in Table 40.
Return to Table 4.
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Figure 55. OUT19_COLOR Register
7
6
5
4
3
2
1
0
OUT19_Color
R/W-00h
Table 40. OUT19_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
OUT19_Color
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.36 OUT20_COLOR (Address = 23h) [reset = 00h]
OUT20_COLOR is shown in Figure 56 and described in Table 41.
Return to Table 4.
Figure 56. OUT20_COLOR Register
7
6
5
4
3
2
1
0
OUT20_Color
R/W-00h
Table 41. OUT20_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
OUT20_Color
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.37 OUT21_COLOR (Address = 24h) [reset = 00h]
OUT21_COLOR is shown in Figure 57 and described in Table 42.
Return to Table 4.
Figure 57. OUT21_COLOR Register
7
6
5
4
3
2
1
0
OUT21_Color
R/W-00h
Table 42. OUT21_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
OUT21_Color
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.38 OUT22_COLOR (Address = 25h) [reset = 00h]
OUT22_COLOR is shown in Figure 58 and described in Table 43.
Return to Table 4.
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Figure 58. OUT22_COLOR Register
7
6
5
4
3
2
1
0
OUT22_Color
R/W-00h
Table 43. OUT22_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
OUT22_Color
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.39 OUT23_COLOR (Address = 26h) [reset = 00h]
OUT23_COLOR is shown in Figure 59 and described in Table 44.
Return to Table 4.
Figure 59. OUT23_COLOR Register
7
6
5
4
3
2
1
0
OUT23_Color
R/W-00h
Table 44. OUT23_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
OUT23_Color
R/W
00h
FFh = The color mixing percentage is 0%.
...
80h =The color mixing percentage is 50%.
...
00h = The color mixing percentage is 100%.
8.6.40 RESET (Address = 27h) [reset = 00h]
RESET is shown in Figure 60 and described in Table 45.
Return to Table 4.
Figure 60. RESET Register
7
6
5
4
3
2
1
0
Reset
W-00h
Table 45. OUT14_COLOR Register Field Descriptions
Bit
Field
Type
Reset
Description
7–0
Reset
W
00h
FFh = Reset all the registers to default value.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The LP50xx device is an 18- or 24-channel constant-current-sink LED driver. The LP50xx device improves the
user experience in color mixing and intensity control, for both live effects and coding effort. The optimized
performance for RGB LEDs makes it a good choice for human-machine interaction applications.
9.2 Typical Application
The LP50xx design supports up to four devices in parallel with different configurations on the ADDR0 and
ADDR1 pins.
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Typical Application (continued)
VCC
VMCU
CVCC
VLED
RPULLUP
VCC
RPULLUP
OUT0
EN
OUT1
SDA
SCL
OUT2
ADDR0
MCU
ADDR1
LP5024
OUT21
VCAP
CVCAP
OUT22
IREF
RIREF
GND
VCC
OUT23
CVCC
VLED
VCC
OUT0
EN
OUT1
SDA
SCL
OUT2
ADDR0
ADDR1
LP5024
OUT21
VCAP
CVCAP
OUT22
IREF
RIREF
GND
OUT23
Figure 61. Driving Dual LP5024 Application Example
9.2.1 Design Requirements
Set the LED current to 15 mA using the RIREF resistor.
9.2.2 Detailed Design Procedure
LP50xx scales up the reference current (IREF) set by the external resistor (RIREF) to sink the output current (IOUT)
at each output port. The following formula can be used to calculate the external resistor (RIREF):
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Typical Application (continued)
RIREF =KIREF ×
VIREF
ISET
(2)
The SCL and SDA lines must each have a pullup resistor placed somewhere on the line (the pullup resistors are
normally located on the bus master). In typical applications, values of 1.8 kΩ to 4.7 kΩ are used.
VCAP is internal LDO output pin. This pin must be connected through a 1-µF capacitor to GND. Place the
capacitor as close to the device as possible.
TI recommends having a 1-µF capacitor between VCC and GND to ensure proper operation. Place the capacitor
as close to the device as possible.
9.2.3 Application Curves
The test condition for is that the testing is under bank control, using the following register values: 0x02 (0xFF),
0x04 (0xA0), 0x05 (0xA0), 0x06 (0xA0).
The test condition for is that the testing is under bank control, using the following register values: 0x02 (0xFF),
0x04 (0x10), 0x05 (0x10), 0x06 (0x10).
Figure 62. Current Waveform of OUT0, OUT1, OUT2 and
OUT3
40
Figure 63. Current Waveform of OUT0, OUT1, OUT2 and
OUT3
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10 Power Supply Recommendations
The device is designed to operate from a VVCC input-voltage supply range between 2.7 V and 5.5 V. This input
supply must be well-regulated and able to withstand maximum input current and maintain stable voltage without
voltage drop even in a load-transition condition (start-up or rapid intensity change). The resistance of the input
supply rail must be low enough that the input-current transient does not cause a drop below a 2.7-V level in the
LP50xx VVCC supply voltage.
11 Layout
11.1 Layout Guidelines
To prevent thermal shutdown, the junction temperature, TJ, must be less than T(TSD). If the voltage drop across
the output channels is high, the device power dissipation can be large. The LP50xx device has very good
thermal performance because of the thermal pad design; however, the PCB layout is also very important to
ensure that the device has good thermal performance. Good PCB design can optimize heat transfer, which is
essential for the long-term reliability of the device.
Use the following guidelines when designing the device layout:
• Place the CVCAP, CVCCand RIREF as close to the device as possible. Also, TI recommends to put the ground
plane as Figure 64 and Figure 65.
• Maximize the copper coverage on the PCB to increase the thermal conductivity of the board. The major heat
flow path from the package to the ambient is through copper on the PCB. Maximum copper density is
extremely important when no heat sinks are attached to the PCB on the other side from the package.
• Add as many thermal vias as possible directly under the package ground pad to optimize the thermal
conductivity of the board.
• Use either plated-shut or plugged and capped vias for all the thermal vias on both sides of the board to
prevent solder voids. To ensure reliability and performance, the solder coverage should be at least 85%.
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11.2 Layout Examples
GND
VCAP
IREF
EN
SCL
SDA
VCC
ADDR1
ADDR0
32
31
30
29
28
27
26
25
GND
To LED OUT0
1
24
To LED OUT1
2
23
To LED OUT2
3
22
To LED OUT3
4
21
GND
16
To LED OUT15
GND
15
OUT16 To LED
To LED OUT14
17
14
8
To LED OUT13
To LED OUT7
13
OUT17 To LED
To LED OUT12
18
12
7
To LED OUT11
To LED OUT6
11
19
To LED OUT10
6
10
To LED OUT5
To LED OUT9
20
9
5
To LED OUT8
To LED OUT4
GND
Figure 64. LP5018 Layout Example
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Layout Examples (continued)
GND
VCAP
IREF
EN
SCL
SDA
VCC
ADDR1
ADDR0
32
31
30
29
28
27
26
25
GND
To LED OUT0
1
24
OUT23 To LED
To LED OUT1
2
23
OUT22 To LED
To LED OUT2
3
22
OUT21 To LED
To LED OUT3
4
21
OUT20 To LED
GND
GND
16
OUT16 To LED
To LED OUT15
17
15
8
To LED OUT14
To LED OUT7
14
OUT17 To LED
To LED OUT13
18
13
7
To LED OUT12
To LED OUT6
12
OUT18 To LED
To LED OUT11
19
11
6
To LED OUT10
To LED OUT5
10
OUT19 To LED
To LED OUT9
20
9
5
To LED OUT8
To LED OUT4
GND
Figure 65. LP5024 Layout Example
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12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 46. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
LP5018
Click here
Click here
Click here
Click here
Click here
LP5024
Click here
Click here
Click here
Click here
Click here
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and without
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.
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PACKAGE OPTION ADDENDUM
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31-May-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LP5018RSMR
ACTIVE
VQFN
RSM
32
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
LP
5018
LP5024RSMR
ACTIVE
VQFN
RSM
32
3000
RoHS & Green NIPDAU | NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
LP
5024
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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