LP5890
SLVSGD5 – JULY 2021
LP5890 16 × 48 LED Matrix Driver With Ultra-low Power
– Upside and downside ghosting removal
– Low grayscale enhancement
– LED open, short, and weak short detection and
removal
1 Features
•
•
•
•
•
•
•
Separated VCC and VR/G/B power supply
– VCC voltage range: 2.5 V–5.5 V
– VR/G/B voltage range: 2.5 V–5.5 V
48-current source channels from 0.2 mA–20 mA
– Channel-to-channel accuracy: ±0.5% (typ.),
±2% (max.); device-to-device accuracy: ±0.5%
(typ.), ±2% (max.)
– Low knee voltage: 0.26 V (max.) when IOUT = 5
mA
– 3-bits (8 steps) global brightness control
– 8-bits (256 steps) color brightness control
– Maximum 16-bits (65536 steps) PWM
grayscale control
16 scan line switches with 190-mΩ RDS(ON)
Ultra-low power consumption
– Independent VCC down to 2.5 V
– Lowest ICC down to 3.9 mA with 50-MHz GCLK
– Intelligent power saving mode
Built-in SRAM to support 1 - 32 multiplexing,
– Single device drives up to 16 × 48 LEDs or 16 ×
16 RGB LEDs
– Dual devices stackable drive up to 32 × 96
LEDs or 32 × 32 RGB LEDs
High speed and low EMI Continuous Clock Series
Interface (CCSI)
– Only three wires: SCLK/SIN/SOUT
– External 50-MHz (max.) SCLK
– Internal frequency multiplier to support GCLK
range from 40 MHz–160 MHz
Optimized display performance
2 Applications
•
•
•
•
•
•
LED digital signage
Keyboard, gaming accessories
Major and smart home appliances
Smart speaker, wired and wireless speaker
Audio mixer, DJ equipment, and broadcast
Access equipment, switches, and servers
3 Description
Electronic devices are becoming smarter, requiring
to use larger quantity of LEDs for animation and
indication purposes and high performance LED matrix
driver is required to improve user experience with
small solution size.
The LP5890 is a highly integrated common cathode
matrix LED display driver with 48 constant current
sources and 16 scanning FETs. A single LP5890 is
capable of driving 16 × 16 RGB LED pixels while
stacking two LP5890s can drive 32 × 32 RGB LED
pixels. To achieve low power consumption, the device
supports separated power supplies for the red, green,
and blue LEDs by its common cathode structure.
Furthermore, the operation power of the LP5890 is
significantly reduced by ultra-low operation voltage
range (Vcc down to 2.5 V) and ultra-low operation
current (Icc down to 3.9 mA).
Device Information
PART NUMBER
LP5890
(1)
PACKAGE(1)
BODY SIZE (NOM)
VQFN (76)
9 mm × 9 mm
BGA (96)
6 mm × 6 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
LP5890 With Single Device or Dual Devices Stackable Connection
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP5890
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SLVSGD5 – JULY 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 2
6 Pin Configuration and Functions...................................3
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................5
7.4 Thermal Information....................................................5
7.5 Electrical Characteristics.............................................6
7.6 Timing Requirements.................................................. 9
7.7 Switching Characteristics............................................9
7.8 Typical Characteristics.............................................. 10
8 Detailed Description......................................................12
8.1 Overview................................................................... 12
8.2 Functional Block Diagram......................................... 13
8.3 Feature Description...................................................13
8.4 Device Functional Modes..........................................24
8.5 Continuous Clock Series Interface............................25
8.6 PWM Grayscale Control........................................... 30
8.7 Register Maps...........................................................33
9 Application and Implementation.................................. 47
9.1 Application Information............................................. 47
9.2 Typical Application.................................................... 47
10 Power Supply Recommendations..............................55
11 Layout........................................................................... 56
11.1 Layout Guidelines................................................... 56
11.2 Layout Example...................................................... 56
12 Device and Documentation Support..........................60
12.1 Receiving Notification of Documentation Updates..60
12.2 Support Resources................................................. 60
12.3 Trademarks............................................................. 60
12.4 Electrostatic Discharge Caution..............................60
12.5 Glossary..................................................................60
13 Mechanical, Packaging, and Orderable
Information.................................................................... 61
4 Revision History
DATE
REVISION
NOTES
July 2021
*
Initial release.
5 Description (continued)
The LP5890 implements a high speed transmission interface to support high device count daisy-chained and
high refresh rate while minimizing electrical-magnetic interference (EMI). The device supports up to 50-MHz
SCLK and up to 160-MHz GCLK (internal). Meanwhile, the device integrates enhanced circuits and intelligent
algorithms to solve the various display challenges in multiple LED matrix applications: Upper and downside
ghosting, Non-uniformity in low grayscale, Coupling, and Caterpillar caused by open or short LEDs, which make
the LP5890 a perfect choice in such applications.
The LP5890 also implements LED open/weak short/short detections and removals during operations and can
also report this information to the accompanying digital processor.
2
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Line3
Line4
Line5
Line6
Line7
Line8
Line9
Line10
Line11
Line12
Line13
Line14
Line15
SCLK
SIN
SOUT
71
70
69
68
67
66
65
64
63
62
61
60
59
58
Line2
74
72
Line1
75
73
Line0
76
6 Pin Configuration and Functions
R0
1
57
R15
G0
2
56
G15
B0
3
55
B15
R1
4
54
R14
G1
5
53
G14
B1
6
52
B14
GND
7
51
VG
VCC
8
50
VG
VR
9
49
VB
VR
10
48
VB
R2
11
47
R13
G2
12
46
G13
B2
13
45
B13
R3
14
44
R12
G3
15
43
G12
B3
16
42
B12
R4
17
41
R11
G4
18
40
G11
B4
19
39
B11
35
36
37
38
B10
G10
R10
34
G9
R9
33
B9
32
R8
30
B8
31
29
B7
G8
28
27
R7
G7
26
B6
25
G6
23
B5
24
22
G5
R6
21
R5
IREF
20
GND
Figure 6-1. LP5890 RRF Package 76-Pin VQFN With Exposed Thermal Pad Top View
1
2
3
4
5
6
7
8
9
10
11
A
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
B
L2
R1
B0
G0
R0
NC
SOU
T
SIN
SCL
K
NC
L14
C
L1
G1
GND
L15
D
L0
B1
E
GND
GND
F
VCC
G
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
R15
R14
VG
R2
R3
GND
GND
GND
G15
G14
VG
VR
G2
G3
GND
GND
GND
B15
B14
VB
H
VR
B2
B3
R7
B8
B9
B10
R13
VB
J
IREF
R4
G13
B13
K
G4
B4
R6
G6
G7
G8
G9
G10
B11
R12
G12
L
R5
G5
B5
B6
B7
R8
R9
R10
G11
R11
B12
Figure 6-2. LP5890 ZXL Package 96-Pin BGA Top View
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Table 6-1. Pin Functions
PIN
4
I/O
DESCRIPTION
NAME
RRF NO.
ZXL NO.
IREF
20
J1
I
Pin for setting the maximum constant-current value. Connecting an external
resistor between IREF and GND sets the maximum current for each constantcurrent output channel. When this pin is connected directly to GND, all outputs
are forced off. The external resistor should be placed close to the device.
VCC
8
F1
I
Device power supply.
VR
9, 10
G1, H1
I
Red LED power supply.
VG
51, 50
E11, F11
I
Green LED power supply.
VB
49, 48
G11, H11
I
Blue LED power supply.
R0-R15
1, 4, 11, 14, B5, B2,F2, F4,
17, 21, 24, J2, L1, K3, H5,
27, 32, 35, L6, L7, L8, L10,
38, 41, 44, K10, H10, E10,
47, 54, 57
E8
O
Red LED Constant-current output.
G0-G15
2, 5, 12, 15, B4, C2, G2, G4,
18, 22, 25, K1, L2, K4, K5,
28, 31, 34, K6, K7, K8, L9,
37, 40, 43, K11, J10, F10,
46, 53, 56
F8
O
Green LED Constant-current output.
B0-B15
3, 6, 13, 16, B3, D2, H2, H4,
19, 23, 26, K2, L3, L4, L5,
29, 30, 33, H6, H7, H8, K9,
36, 39, 42, L11, J11, G10,
45, 52, 55
G8
O
Blue LED Constant-current output.
LINE0LINE15
76, 75, 74,
73, 72, 71,
70, 69, 68,
67, 66, 65,
64, 63, 62,
61
D1, C1, B1, A1,
A2, A3, A4, A5,
A6, A7, A8, A9,
A10, A11, B11,
C11
O
Scan Lines.
SCLK
60
B9
I
Clock-signal input pin.
SIN
59
B8
I
Serial-data input pin.
SOUT
58
B7
O
Serial data output pin.
GND
7
C10, E1, E2,
D5, D6, D7, D8,
D10, D11,
E1,E2, E4, E5,
E6,E7, F5, F6,
F7,G5, G6, G7
-
Power-ground reference.
Thermal
pad
-
-
-
The thermal pad and the GND pin must be connected together on the board.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
VCC
–0.3
6
V
VR/G/B
–0.3
6
V
IREF, SCLK, SIN, SOUT, VSYNC
–0.3
6
V
RX/GX/BX
–0.3
6
V
LINE0 to LINE15
–0.3
6
V
Operating junction temperature, TJ
–40
150
°C
Storage temperature, Tstg
–55
150
°C
Voltage
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
7.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC
V(ESD)
(1)
(2)
Electrostatic discharge
JS-001(1)
UNIT
±4000
Charged-device model (CDM), per JEDEC specification JESD22C101(2)
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VCC
Device supply voltage
2.5
5.5
V
VLEDR/G/B
LED supply voltage
2.5
5.5
V
VIH
High level logic input voltage (SCLK, SIN, VSYNC)
VIL
Low level logic input voltage (SCLK, SIN, VSYNC)
IOH
High level logic output current (SOUT)
IOL
Low level logic output current (SOUT)
ICH
Constant output source current
ILINE
Line scan switch load current
TA
Ambient operating temperature
0.7 × VCC
V
0.3 × VCC
0.2
V
–2
mA
2
mA
20
mA
0
2
A
–40
85
°C
7.4 Thermal Information
LP5890
THERMAL METRIC(1)
RRF (VQFN)
ZXL (BGA)
UNIT
76 PINS
96 PINS
RθJA
Junction-to-ambient thermal resistance
22.2
33.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
10.7
18.6
°C/W
RθJB
Junction-to-board thermal resistance
7.2
11.7
°C/W
ψJT
Junction-to-top characterization parameter
0.1
0.3
°C/W
ψJB
Junction-to-board characterization parameter
7.1
11.6
°C/W
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LP5890
THERMAL METRIC(1)
RθJC(bot)
(1)
RRF (VQFN)
ZXL (BGA)
76 PINS
96 PINS
Junction-to-case (bottom) thermal resistance
UNIT
1.7
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
At VCC = VR = 2.8V, VG/B = 3.8V and TA = –40°C to +85°C; Typical values are at TA = 25°C (unless otherwise specified)
PARAMETER
Device supply voltage
VUVR
Undervoltage restart
VCC rising
VUVF
Undervoltage shutdown
VCC falling
VUV(HYS)
Undervoltage shutdown
hysteresis
ICC
Device supply current
MIN
TYP
2.5
MAX
UNIT
5.5
V
2.3
V
2.0
V
0.1
V
SCLK/SIN = GND, internal
GCLK=0MHz, GSn = 0000h, BC =
2h, CCR/G/B = 63h, PS_EN= 1h,
VOUTn = floating, RIREF = 7.8 kΩ
2.4
mA
SCLK = 10 MHz, internal GCLK =
50 MHz, GSn = 1FFFh, BC = 2h,
CCR/G/B = 63h,VOUTn = floating,
RIREF = 7.8 kΩ, ICH = 2 mA
3.9
mA
SCLK = 10 MHz, internal GCLK =
100 MHz, GSn = 1FFFh, BC = 2h,
CCR/G/B = 63h, VOUTn = floating,
RIREF = 7.8 kΩ, ICH = 2 mA
5
mA
VR/G/B
LED supply voltage
VIH
High level input voltage (SCLK,
SIN)
VIL
Low level input voltage (SCLK,
SIN)
VOH
High level output voltage (SOUT) IOH = –2 mA at SOUT
VOL
Low level output voltage (SOUT) IOL = 2 mA at SOUT
ILOGIC
Logic pin current (SCLK, SIN)
SCLK/SIN = VCC or GND
RDS(ON)
Scan switches' on-state
resistance (LINE0 to LINE15)
VCC = 2.8 V, TA= 25°C
190
mΩ
Reference voltage
SCLK/SIN = GND, internal GCLK=
0MHz, GSn = 0000h, BC = 2h,
CCR/G/B = 63h, VOUTn = floating,
RIREF = 7.8 kΩ
0.8
V
VIREF
VKNEE
ICH(LKG)
6
TEST CONDITIONS
VCC
Channel knee voltage (R0-R15 /
G0-G15 / B0-B15)
Channel leakage current (R0R15 / G0-G15 / B0-B15)
2.5
5.5
0.7 × VCC
V
V
VCC-0.4
-1
0.3 × VCC
V
VCC
V
0.4
V
1
uA
VLEDR/G/B ≥ 2.8 V, all channel
outputs on, output current at 1 mA
0.25
V
VLEDR/G/B ≥ 2.8 V, all channel
outputs on, output current at 5 mA
0.26
V
VLEDR/G/B ≥ 2.8 V, all channel
outputs on, output current at 10 mA
0.3
V
VLEDR/G/B ≥ 2.8 V, IMAX = 1b, all
channel outputs on, output current at
15 mA
0.37
V
VLEDR/G/B ≥ 2.8 V, IMAX=1b, all
channel outputs on, output current at
20 mA
0.41
V
1
uA
Channel voltage at 0 V
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7.5 Electrical Characteristics (continued)
At VCC = VR = 2.8V, VG/B = 3.8V and TA = –40°C to +85°C; Typical values are at TA = 25°C (unless otherwise specified)
PARAMETER
ΔIERR(CC)
Constant-current channel to
channel deviation (R0-R15 / G0G15 / B0-B15)(1)
TYP
MAX
UNIT
All CHn = on, BC = 00h, CC =
31h, VOUTn = (VLED-1)V, RIREF =
19.05 kΩ (ICH = 0.2-mA target), TA =
25°C, includes the VIREF tolerance,
at same color grouped outputs of
R0-R15 / G0-G15 / B0-B15
TEST CONDITIONS
MIN
±1
±2.5
%
All CHn = on, BC = 00h, CC =
7Dh, VOUTn = (VLED-1)V, RIREF =
19.05 kΩ (ICH = 0.5-mA target), TA =
25°C, includes the VIREF tolerance,
at same color grouped outputs of
R0-R15 / G0-G15 / B0-B15
±0.5
±1.5
%
All CHn = on, BC = 00h, CC =
FBh, VOUTn = (VLED-1)V, RIREF =
19.05 kΩ (ICH = 1-mA target), TA =
25°C, includes the VIREF tolerance,
at same color grouped outputs of
R0-R15 / G0-G15 / B0-B15
±0.5
±1.5
%
All CHn = on, BC = 2h, CC =
FBh, VOUTn = (VLED-1)V, RIREF =
7.8 kΩ (ICH = 5-mA target), TA =
25°C, includes the VIREF tolerance,
at same color grouped outputs of
R0-R15 / G0-G15 / B0-B15
±0.5
±2
%
All CHn = on, BC = 6h, CC =
A7h, VOUTn = (VLED-1)V, RIREF =
7.8 kΩ (ICH = 10-mA target), TA =
25°C, includes the VIREF tolerance,
at same color grouped outputs of
R0-R15 / G0-G15 / B0-B15
±0.5
±2
%
All CHn = on, BC = 7h, CC = FBh,
IMAX=1b, VOUTn = (VLED-1)V,
RIREF = 6.8 kΩ (ICH = 20-mA target),
TA = 25°C, includes the VIREF
tolerance, at same color grouped
outputs of R0-R15 / G0-G15 / B0B15
±0.5
±2.5
%
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7.5 Electrical Characteristics (continued)
At VCC = VR = 2.8V, VG/B = 3.8V and TA = –40°C to +85°C; Typical values are at TA = 25°C (unless otherwise specified)
PARAMETER
ΔIERR(DD)
Constant-current device to
device deviation (R0-R15 / G0G15 / B0-B15)(2)
TYP
MAX
UNIT
All CHn = on, BC = 00h, CC =
31h, VOUTn = (VLED-1)V, RIREF =
19.05 kΩ (ICH = 0.2-mA target), TA =
25°C, includes the VIREF tolerance,
at same color grouped outputs of
R0-R15 / G0-G15 / B0-B15
TEST CONDITIONS
MIN
±1
±2.5
%
All CHn = on, BC = 00h, CC =
7Dh, VOUTn = (VLED-1)V, RIREF =
19.05 kΩ (ICH = 0.5-mA target), TA =
25°C, includes the VIREF tolerance,
at same color grouped outputs of
R0-R15 / G0-G15 / B0-B15
±0.5
±1.5
%
All CHn = on, BC = 00h, CC =
FBh, VOUTn = (VLED-1)V, RIREF =
19.05 kΩ (ICH = 1-mA target), TA =
25°C, includes the VIREF tolerance,
at same color grouped outputs of
R0-R15 / G0-G15 / B0-B15
±0.5
±1
%
All CHn = on, BC = 2h, CC =
FBh, VOUTn = (VLED-1)V, RIREF =
7.8 kΩ (ICH = 5-mA target), TA =
25°C, includes the VIREF tolerance,
at same color grouped outputs of
R0-R15 / G0-G15 / B0-B15
±0.5
±1.5
%
All CHn = on, BC = 6h, CC =
A7h, VOUTn = (VLED-1)V, RIREF =
7.8 kΩ (ICH = 10-mA target), TA =
25°C, includes the VIREF tolerance,
at same color grouped outputs of
R0-R15 / G0-G15 / B0-B15
±0.5
±2
%
All CHn = on, BC = 7h, CC = FBh,
IMAX=1b, VOUTn = (VLED-1)V,
RIREF = 6.8 kΩ (ICH = 20-mA target),
TA = 25°C, includes the VIREF
tolerance, at same color grouped
outputs of R0-R15 / G0-G15 / B0B15
±0.5
±2
%
ΔIREG(LINE)
Line regulation (R0-R15 / G0G15 / B0-B15)(3)
VLED = 2.5 to 5.5V, All CHn =
on, VOUTn = (VLED-1)V, at same
color grouped outputs of R0-R15 /
G0-G15 / B0-B15
±1
%/V
ΔIREG(LOAD)
Load regulation (R0-R15 / G0G15 / B0-B15)(4)
VOUTn = (VLED-1)V to (VLED-3)V,
VR=VG/B=VLED=3.8V, All CHn =
on, at same color grouped outputs of
R0-R15 / G0-G15 / B0-B15
±1
%/V
TTSD
Thermal shutdown threshold
170
°C
THYS
Thermal shutdown hysteresis
15
°C
(1)
The deviation of each output in same color group (OUTR0-15 or OUTG0-15 or OUTB0-15) from the average of same color group
¿:%; = N +
:0
(2)
8
+:J
F 1O × 100
+ +:1 + ® + +:14 + +:15
16
constant current. The deviation is calculated by the formula. (X = R or G or B, n = 0-15)
spacer
The deviation of the average of constant-current in each color group from the ideal constant-current value. (X = R or G or B):
+:0 + +:1 + ® + +:14 + +:15
F Ideal Output Current
16
O × 100
¿:%; = N
Ideal Output Current
Ideal current is calculated by the following equation:
8+4'(
1 + %%_4(KN %%_) KN %%_$)
++&'#._4(KN ) KN $) =
× )#+0($%) ×
4+4'(
256
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spacer
Line regulation is calculated by the following equation. (X = R or G or B, n = 0-15):
(+:J =P 8.'& = 5.58) F (+:J =P 8.'& = 2.58)
100
¿:%8; = [
]×
(+:J =P 8.'& = 2.58)
5.58 F 2.58
spacer
Load regulation is calculated by the following equation. (X = R or G or B, n = 0-15):
( I at VXn 1V ) ( I Xn at VXn 3V )
100
]u
'(%V ) [ Xn
( I Xn at VXn 3V )
3V 1V
spacer
(3)
(4)
7.6 Timing Requirements
At VCC = VR = 2.8 V, VG/B = 3.8V and TA = –40°C to +85°C; Typical values are at TA = 25°C (unless otherwise specified)
PARAMETER
TEST CONDITIONS
fSCLK
Clock frequency (SCLK)
tw(H0)
High level pulse duration (SCLK)
tw(L0)
Low level pulse duration (SCLK)
tsu(0)
Setup time
SIN to SCLK↑
th(0)
Hold time
SCLK↑ to SIN↑↓
MIN
TYP
MAX
UNIT
50
MHz
9
ns
9
ns
10
ns
2
ns
7.7 Switching Characteristics
At VCC = VR = 2.8 V, VG/B = 3.8V and TA = –40°C to +85°C; Typical values are at TA = 25°C (unless otherwise specified)
TYP
MAX
tr
Rise time (SOUT)
PARAMETER
VCC = 3.3 V, CSOUT = 30 pF
2
10
ns
tf
Fall time (SOUT)
VCC = 3.3 V, CSOUT = 30 pF
2
10
ns
Propagation delay
SCLK↑ to SOUT↑↓, full temperature,
CSOUT = 30 pF
14.2
ns
tpd(0)
TEST CONDITIONS
MIN
3.5
UNIT
Figure 7-1. Timing and Switching Diagram
(1). Input pulse rise and fall time is 2 ns typically.
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7.8 Typical Characteristics
0.016
0.016
0.2 mA
1 mA
5 mA
10mA
15 mA
0.012
0.2 mA
1 mA
5 mA
10 mA
15 mA
0.014
Output Current (mA)
Output Current (mA)
0.014
0.01
0.008
0.006
0.004
0.012
0.01
0.008
0.006
0.004
0.002
0.002
0
0
0
0.2
0.4
0.6
0.8
1
1.2
VLED-VCH (V)
1.4
1.6
1.8
0
2
0.2
0.4
0.6
D001
0.8
1
1.2
VLED-VCH (V)
1.4
D002
Figure 7-3. Channel Current vs (VLED-Vchannel) Voltage
1
0.011
0.01
Constant Current Accuracy(%)
-40 oC
25 oC
85 oC
0.009
Output Current (A)
2
Vcc = 5.5 V
Figure 7-2. Channel Current vs (VLED-Vchannel) Voltage
0.008
0.007
0.006
0.005
0.004
0.003
0.8
0.6
-40oC Min
-40oC Max
25oC Min
25oC Max
85oC Min
85oC Max
0.4
0.2
0
-0.2
-0.4
0.002
0.001
0
0.2
0.4
0.6
0.8
1
1.2
VLED-VCH (V)
1.4
1.6
1.8
-0.6
2
0
2
4
6
D003
8
10
12
14
Output Current (mA)
D003_SLVSEJ1.grf
Figure 7-4. Channel Current vs (VLED-Vchannel) Voltage
0.016
0.8
0.014
0.6
0.012
-40oC Min
-40oC Max
25oC Min
25oC Max
85oC Min
85oC Max
0.2
0
18
20
D004
D004_SLVSEJ1.grf
1
0.4
16
Figure 7-5. Channel to Channel Accuracy vs Output Current
Output Current
Constant Current Accuracy(%)
1.8
D002_SLVSEJ1.grf
D001_SLVSEJ1.grf
Vcc = 2.8 V
0.2 mA, BC=00h, REF=19.05K
1 mA, BC=02h, REF=7.8K
5 mA, BC=02h, REF=7.8K
10 mA, BC=06h, REF=7.8K
15 mA, BC=06h, REF=7.8K
0.01
0.008
0.006
-0.2
0.004
-0.4
0.002
0
-0.6
0
2
4
6
8
10
12
14
Output Current (mA)
16
18
20
0
30
60
90
120 150 180 210
Color Control Code (Decimal)
240
270
D004
D004_SLVSEJ1.grf
Figure 7-6. Channel to Channel Accuracy vs Output Current
10
1.6
D005
D005_SLVSEJ1.grf
Figure 7-7. Color Control Code vs Output Current
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10.5
7.8
10
7.7
9.5
7.6
9
7.5
8.5
7.4
ICC (mA)
ICC (mA)
7.8 Typical Characteristics (continued)
8
7.5
7
7.3
7.2
7.1
6.5
7
6
6.9
5.5
6.8
5
40
60
80
100
120
140
GCLK Frequency (MHz)
160
180
6.7
2.4
2.6
2.8
3
D006
D006_SLVSEJ1.grf
Figure 7-8. Icc Current vs GCLK Frequency
3.2 3.4 3.6 3.8
Vcc voltage (V)
4
4.2
4.4
4.6
D007
D007_SLVSEJ1.grf
GCLK = 83 MHz
Figure 7-9. Icc Current vs Vcc Voltage
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8 Detailed Description
8.1 Overview
The LP5890 is a highly integrated RGB LED driver with 48 constant current sources and 16 scanning FETs. A
single LP5890 is capable of driving 16 × 16 RGB LED pixels while stacking two LP5890s can drive 32 × 32
RGB LED pixels. To achieve low power consumption, the device supports separated power supplies for the red,
green, and blue LEDs by its common cathode structure. Furthermore, the operation power of the LP5890 is
significantly reduced by ultra-low operation voltage range (VCC down to 2.5 V) and ultra-low operation current
(ICC down to 3.9 mA).
The LP5890 supports per channel current from 0.2 mA to 20 mA, with typical 1% channel-to-channel current
deviation and typical 1% device-to-device current deviation. The DC current value of all 48 channels is set by
an external IREF resistor and can be adjusted by the 8-step global brightness control (BC) and the 256-step
per-color group brightness control (CCR/CCG/CCB).
The LP5890 implements a high speed transmission interface to support high device count daisy-chained and
high refresh rate while minimizing electrical-magnetic interference (EMI). The LP5890 supports up to 50-MHz
SCLK (external) and up to 160-MHz GCLK (internal). Meanwhile, the device integrates enhanced circuits and
intelligent algorithms to solve the various display challenges in Narrow Pixel Pitch(NPP) LED display applications
and Mini or Micro-LED products: Dim at the fist scan line, Upper and downside ghosting, Non-uniformity in low
grayscale, Coupling, Caterpillar caused by open or short LEDs, which make the LP5890 a perfect choice in such
applications.
The LP5890 also implements LED open/weak short/short detections and removals during operations and can
also report this information to the accompanying digital processor.
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8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Independent and Stackable Mode
The LP5890 can operate in two different modes: independent or stackable. In independent mode, a single
LP5890 can drive a 16 × 16 RGB LED matrix, while in stackable mode, up to three LP5890s can be stacked
together, which means the line switches of one device can be shared to another. Stacking two LP5890s can
drive a 32 × 32 RGB LED matrix while stacking three LP5890s can drive a 32 × 48 RGB matrix. The mode can
be configured by the MOD_SIZE (For more details, see FC0).
8.3.1.1 Independent Mode
Figure 8-1 shows an implementation of a 16 × 32 RGB LED matrix using two LP5890s in independent mode.
Each device is responsible for its own 16 × 16 RGB LED matrix which means that all the data for section A is
stored in Device1 and the data for section B is stored in Device2.
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Figure 8-1. Two Devices in Independent Mode
The unused line must be assigned to the last several lines of the device. For example, if there are only 14
scanning lines, then the two unused lines should be assigned to 1_LS14 and 1_LS15.
8.3.1.2 Stackable Mode
While operating the LP5890 in stackable mode, as shown in Figure 8-2 and Figure 8-3, Device2 needs to be
rotated 180o relative to Device1. This action allows the position of line switches to be near the center column of
the LED matrix for better routing. For Device1, the lines will be connected sequentially (line switch 0 connected
to scan line 1). However, on Device2, it is connected in reverse order, with the 16th scan line is connected to line
switch 15 and the 32th scan line is connected to line switch 0.
Figure 8-2 shows the connection between two LP5890 devices in stackable mode driving a 32 × 32 RGB LED
pixels. The MOD_SIZE should be configured to 00b/10b. Device1 supplies 16 line switches for the first 16 scan
line, and Device2 supplies 16 line switches for scan line 17-32. The data for matrix sections A and C are stored
in Deivce1, while matrix sections B and D data are stored in Device2.
Physical Line0
A
1_LS0
B
...
...
Device1
32 Lines
1_LS15
Physical Line15
Physical Line16
C
D
2_LS15
...
...
Device2
2_LS0
Physical Line31
32 RGBs
Figure 8-2. Two Devices in Stackable Mode
Figure 8-3 shows the connection between three devices connected in stackable mode with MOD_SIZE bits set
to 11b. In this configuration, Device1 supplies the line switches for the first 16 scan lines, Device2 supplies line
switches for scan lines 17-32, and the line switches of Device3 are not used. Matrix A and D's data are stored in
Device 1, matrix B and E's data are stored in Device2, and matrix C and F's data are stored in Device3.
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Physical Line0
B
A
C
1_LS0
...
...
Device1
Device3
32 Lines
1_LS15
Physical Line15
Physical Line16
D
F
E
2_LS15
...
...
Device2
2_LS0
Physical Line31
48 RGBs
Figure 8-3. Three Devices in Stackable Mode
In order to make sure the scanning sequence is still from 1st line to 32nd line, the scan line switching order of the
second device needs to be reversed. This action can be configured by the SCAN_REV (For more details, see
FC4).
Table 8-1 shows the pin assignment between the LED matrix physical lines and the LP5890 corresponding pins,
depending on the SCAN_REV.
Table 8-1. Stackable With Different SCAN_REV Value
LED Matrix Physical Line
Device Line Switch Pin (SCAN_REV = 1)
Device Line Switch Pin (SCAN_REV = 0)
L0
1_LS0
1_LS0
L1
1_LS1
1_LS1
L2
1_LS2
1_LS2
L3
1_LS3
1_LS3
L4
1_LS4
1_LS4
L5
1_LS5
1_LS5
L6
1_LS6
1_LS6
L7
1_LS7
1_LS7
L8
1_LS8
1_LS8
L9
1_LS9
1_LS9
L10
1_LS10
1_LS10
L11
1_LS11
1_LS11
L12
1_LS12
1_LS12
L13
1_LS13
1_LS13
L14
1_LS14
1_LS14
L15
1_LS15
1_LS15
L16
2_LS15
2_LS0
L17
2_LS14
2_LS1
L18
2_LS13
2_LS2
L19
2_LS12
2_LS3
L20
2_LS11
2_LS4
L21
2_LS10
2_LS5
L22
2_LS9
2_LS6
L23
2_LS8
2_LS7
L24
2_LS7
2_LS8
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Table 8-1. Stackable With Different SCAN_REV Value (continued)
LED Matrix Physical Line
Device Line Switch Pin (SCAN_REV = 1)
Device Line Switch Pin (SCAN_REV = 0)
L25
2_LS6
2_LS9
L26
2_LS5
2_LS10
L27
2_LS4
2_LS11
L28
2_LS3
2_LS12
L29
2_LS2
2_LS13
L30
2_LS1
2_LS14
L31
2_LS0
2_LS15
When the LP5890 devices are used in stackable mode, if there are unused line switches, these unused line
switches must be the last line switches of the first or the second device. For example, if there are only 30
scanning lines, and if,
The unused line switches must be 2_LS14, 2_LS15 if SCAN_REV = '0'b, or 2_LS1, 2_LS0 if SCAN_REV = '1'b.
8.3.2 Current Setting
8.3.2.1 Brightness Control (BC) Function
The LP5890 device is able to adjust the output current of all constant-current outputs simultaneously. This
function is called global brightness control (BC). The global BC for all outputs is programmed with a 3-bit
register, thus all output currents can be adjusted in 8 steps for a given current-programming resistor, RIREF.
When the 3-bit BC register changes, the gain of output current, GAINBC changes as Table 8-2 below.
Table 8-2. Current Gain Versus BC Code
BC Register (BC)
Current Gain (GAINBC)
000b
24.17
001b
30.57
010b
49.49
011b (default)
86.61
100b
103.94
101b
129.92
110b
148.48
111b
173.23
The maximum output current per channel, IOUTSET, is determined by resistor, RIREF, and the GAINBC. The
voltage on IREF is typically 0.8 V. RIREF can be calculated by Equation 1 below. For noise immunity purpose,
suggest RIREF < 40 kΩ.
4+4'( (G×) =
8+4'( (8)
8+4'( (8)
=
× )#+0($%)
++4'( (I#) +1765'6 (I#)
(1)
8.3.2.2 Color Brightness Control (CC) Function
The LP5890 device is able to adjust the output current of each of the three color groups R0-R15, G0-G15, and
B0-B15 separately. This function is called color brightness control (CC). For each color, it has 8-bit data register,
CC_R, CC_G, or CC_B. Thus, all color group output currents can be adjusted in 256 steps from 0% to 100%
of the maximum output current, IOUTSET. The output current of each color, IOUT_R (or G or B), can be calculated by
Equation 2 below.
+176 _4(KN ) KN $) = +1765'6 ×
1 + %%_4(KN %%_) KN %%_$)
256
(2)
Table Table 8-3 shows the CC data versus the constant-current against IOUTSET:
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Table 8-3. CC Data vs Current Ratio
CC Register (CC_R or CC_G or
CC_B)
Ratio of IOUTSET
0000 0000b
1/256
0.39%
0000 0001b
2/256
0.78%
...
...
...
0111 1111b (default)
128/256
50%
...
...
...
1111 1110b
255/256
99.61%
1111 1111b
256/256
100%
8.3.2.3 Choosing BC/CC for a Different Application
BC is mainly used for global brightness adjustment to adapt to ambient brightness, such as between day and
night, indoor and outdoor.
Suggested BC is 3h or 4h, which is in the middle of the range, allowing flexible changes in brightness up and
down.
•
•
If the current of one color group (usually R LEDs) is close to the output maximum current (10 mA or 20 mA),
choose the maximum BC value, 7h, to prevent the constant output current from exceeding the upper limit in
case a larger BC code is input accidentally.
If the current of one color group (usually B LEDs) is close to the output minimum current (0.2 mA), choose the
minimum BC code, 0h, to prevent the constant output current from exceeding the lower limit in case a lower
BC code is input accidentally.
The CC can be used to fine tune the brightness in 256 steps. The CC is suitable for white balance adjustment
between RGB color group. To get a pure white color, the general requirement for the luminous intensity ratio
of R, G, B LED is 5:3:2. Depending on the characteristics of the LED (Electro-Optical conversion efficiency),
the current ratio of R, G, B LED will be much different from this ratio. Usually, the Red LED needs the largest
current. Choose 255d (the maximum value) CC code for the color group that needs the largest initial current,
then choose proper CC code for the other two color groups according to the current ratio requirement of the LED
used.
8.3.3 Frequency Multiplier
The LP5890 has an internal frequency multiplier to generate the GCLK by SCLK. The GCLK frequency can be
configured by FREQ_MOD (for more details, see FC0) and FREQ_MUL (for more details, see FC0) from 40
MHz to 160 MHz. As Figure 8-4 shows, if the GCLK frequency is not higher than 80 MHz, the GCLK_MOD is set
to 0 to disable the bypass switch (enable the ½ divider), while the GCLK frequency is higher than 80 MHz, the
GCLK_MOD is set to 1 to enable the bypass switch (disable the ½ divider).
GCLK_MUL
SCLK
GCLK_MOD
1/2
GCLK
Figure 8-4. Frequency Multiplier Block Diagram
8.3.4 Line Transitioning Sequence
The LP5890 defines a timing sequence of scan line transition. T_SW is the total transitioning time.
Table 8-4 is the relation between LINE_SWT bits and the line switch time (GCLK numbers) with different internal
GCLK frequency.
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Table 8-4. Line Switch Time
LINE_SW
T
GCLK
numbers
T_SW (us, 40
MHZ GCLK)
T_SW (us, 60 MHZ
GCLK)
T_SW (us, 100 MHZ T_SW (us, 120 MHZ T_SW(us, 160 MHZ
GCLK)
GCLK)
GCLK)
0000b
45
1.125
0.7515
0.45
0.3735
0.2835
0001b
60
1.5
1.002
0.6
0.498
0.378
0010b
90
2.25
1.503
0.9
0.747
0.567
0011b
120
3
2.004
1.2
0.996
0.756
0100b
150
3.75
2.505
1.5
1.245
0.945
0101b
180
4.5
3.006
1.8
1.494
1.134
0110b
210
5.25
3.507
2.1
1.743
1.323
0111b
240
6
4.008
2.4
1.992
1.512
1000b
270
6.75
4.509
2.7
2.241
1.701
1001b
300
7.5
5.01
3
2.49
1.89
1010b
330
8.25
5.511
3.3
2.739
2.079
1011b
360
9
6.012
3.6
2.988
2.268
1100b
390
9.75
6.513
3.9
3.237
2.457
1101b
420
10.5
7.014
4.2
3.486
2.646
1110b
450
11.25
7.515
4.5
3.735
2.835
1111b
480
12
8.016
4.8
3.984
3.024
T0 is set by the LINE_SW_T0 (see FC4 for more details). T2 constantly equals to 5 GCLKs.
T1 and T3 can be calculated by LINE_TIMEMODE (see FC0 for more details).
8.3.5 Protections and Diagnostics
8.3.5.1 Thermal Shutdown Protection
The Thermal Shutdown (TSD) function turns off all IC constant-current outputs when the junction temperature
(TJ) exceeds 170°C (typical). Normal operation resumes when TJ falls below 155°C (typical).
8.3.5.2 IREF Resistor Short Protection
The IREF resistor short protection (ISP) function prevents unwanted large currents from flowing though the
constant-current output when the IREF resistor is shorted accidentally. The LP5890 device turns off all output
channels when the IREF pin voltage is lower than 0.19 V (typical). When the IREF pin voltage goes higher than
0.325 V (typical), the LP5890 device resumes normal operation.
8.3.5.3 LED Open Load Detection and Removal
8.3.5.3.1 LED Open Detection
The LED Open Detection (LOD) function detects faults caused by an open circuit in any LED, or a short from
OUTn to VLED with low impedance. LOD was realized by comparing the OUTn voltage to the LOD detection
threshold voltage level set by LODVTH_R/LODVTH_G/LODVTH_B (see FC3 for more details). If the OUTn
voltage is higher than the programmed voltage, the corresponding output LOD bit is set to 1 to indicate an open
LED. Otherwise, the output of that LOD bit is 0. LOD data output by the detection circuit are valid only during the
OUTn turning on period.
Figure 8-5 shows the equivalent circuit of LED open detection.
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VG
VR
B0 G0 R0
LODVTH_R
VB
LODVTH_G
VR
VG
VB
LODVTH_B
LODVTH_G
LODVTH_G
LODVTH_R
+
+
+
+
+
+
±
±
±
±
±
±
Channel
Control
Channel
Control
Channel
Control
Channel
Control
Channel
Control
Channel
Control
R15 G15 B15
Y
LOD Detection
0b - Normal
1b - LED-short
48-bit LOD Data
48-bit
LSB
SCLK
SIN
READLOD
MSB
SOUT
48-bit Common Shift Register
Figure 8-5. LED Open Detection Circuit
The LED open detection function records the position of the open LED, which contains the scan line number
and relevant channel number. The scan line order is stored in LOD_LINE_WARN register (for more details see
FC12), and the channel number is latched into the internal 48-bit LOD data register for more details see FC14)
at the end of each segment. Figure 8-6 shows the bit arrangement of the LOD data register.
LOD Data Register
LSB
LOD Bit0
LOD Bit1
LOD Bit2
LOD Bit3
LOD Bit4
LOD Bit5
LOD Bit6
LOD Bit7
LOD Bit8
LOD Bit9
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
LOD Bit10 LOD Bit11 LOD Bit12 LOD Bit13 LOD Bit14 LOD Bit15
R10
R11
R12
R13
R14
R15
LOD Bit16 LOD Bit17 LOD Bit18 LOD Bit19 LOD Bit20 LOD Bit21 LOD Bit22 LOD Bit23 LOD Bit24 LOD Bit25 LOD Bit26 LOD Bit27 LOD Bit28 LOD Bit29 LOD Bit30 LOD Bit31
G0
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
MSB
LOD Bit32 LOD Bit33 LOD Bit34 LOD Bit35 LOD Bit36 LOD Bit37 LOD Bit38 LOD Bit39 LOD Bit40 LOD Bit41 LOD Bit42 LOD Bit43 LOD Bit44 LOD Bit45 LOD Bit46 LOD Bit47
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
Figure 8-6. Bit Arrangement in LOD Data Register
8.3.5.3.2 Read LED Open Information
The LOD readback function needs to be enabled before read LED open information. This function is enabled by
LOD_LSD_RB (for more details, see FC3).
Figure 8-7 shows the steps to read LED open information. Wait at least one sub-period time between Step2 and
Step3 command.
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Figure 8-7. Steps to Read LED Open Information
8.3.5.3.3 LED Open Caterpillar Removal
Figure 8-8 shows the caterpillar issue caused by open LED. Suppose the LED0-1 is an open LED. When line0 is
chosen and the OUT1 is turned on, the OUT1 voltage will be forced to approach to VLED because of the broken
path of the current source. However, the voltage of the un-chosen lines are below the Vclamp which is much
lower than VLED, causing all LEDs which connect to the channel OUT1 light unwanted.
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Figure 8-8. LED Open Caterpillar
The LP5890 implements circuits that can eliminate the caterpillar issue caused by open LEDs. The LED open
caterpillar removal function is configured by LODRM_EN (fore more details, see FC0). When LODRM_EN is set
to 1b, the caterpillar removal function is enabled. The corresponding channel OUTn is turned off when scanning
to line with open LED. The caterpillar issue is eliminated until device resets or LODRM_EN is set to 0b.
The internal caterpillar elimination circuit can handle a maximum of three lines that have open LEDs fault
condition. If there are open LEDs located in three or fewer lines, the LP5890 is able to handle the open LEDs all
in these lines. If there are open LEDs in more than three lines, the caterpillar issue is solved for the lines where
the first three open LEDs were detected, but the open LEDs in the fourth and subsequent lines still cause the
caterpillar issue.
8.3.5.4 LED Short and Weak Short Circuitry Detection and Removal
8.3.5.4.1 LED Short and Weak Short Detection
The LED Short Detection (LSD) function detects faults caused by a short circuit in any LED. LSD was realized
by comparing the OUTn voltage to the LSD threshold voltage. If the OUTn voltage is lower than the threshold
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voltage, the corresponding output LSD bit is set to 1 to indicate an short LED, otherwise, the output of that LSD
bit is 0. LSD data output by the detection circuit are valid only during the OUTn turning on period.
LSD weak short can be detected by adjusting threshold voltage, which level is set by LSDVTH_R/LSDVTH_G/
LSDVTH_B (for more details, see FC3).
Figure 8-9 shows the equivalent circuit of LED short detection.
VG
VR
LSDVTH_R
B0 G0 R0
VB
LSDVTH_G
VR
VG
VB
LSDVTH_B
LSDVTH_G
LSDVTH_G
LSDVTH_R
+
+
+
+
+
+
±
±
±
±
±
±
Channel
Control
Channel
Control
Channel
Control
Channel
Control
Channel
Control
Channel
Control
R15 G15 B15
Y
LSD Detection
0b - Normal
1b - LED-short
48-bit LSD Data
48-bit
LSB
SCLK
SIN
READLSD
MSB
SOUT
48-bit Common Shift Register
Figure 8-9. LED Short Detection Circuit
The LED short detection function records the position of the short LED, which contains the scan line order and
relevant channel number. The scan line order is stored LSD_LINE_WARN register (for more details, see FC13),
and the channel number is latched into the internal 48-bit LSD data register (fore more details see FC15) at the
end of each segment. Figure 8-10 shows the bit arrangement of the LSD data register.
LSD Data Register
LSB
LSD Bit0
LSD Bit1
LSD Bit2
LSD Bit3
LSD Bit4
LSD Bit5
LSD Bit6
LSD Bit7
LSD Bit8
LSD Bit9
LSD Bit10
LSD Bit11
LSD Bit12
LSD Bit13
LSD Bit14
LSD Bit15
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
LSD Bit16
LSD Bit17
LSD Bit18
LSD Bit19
LSD Bit20
LSD Bit21
LSD Bit22
LSD Bit23
LSD Bit24
LSD Bit25
LSD Bit26
LSD Bit27
LSD Bit28
LSD Bit29
LSD Bit30
LSD Bit31
G0
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
MSB
LSD Bit32
LSD Bit33
LSD Bit34
LSD Bit35
LSD Bit36
LSD Bit37
LSD Bit38
LSD Bit39
LSD Bit40
LSD Bit41
LSD Bit42
LSD Bit43
LSD Bit44
LSD Bit45
LSD Bit46
LSD Bit47
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
Figure 8-10. Bit Arrangement in the LSD Data Register
8.3.5.4.2 Read LED Short Information
The LSD readback function needs to be enabled before reading LED Short information. This function is enabled
by LOD_LSD_RB (see FC3 for more details).
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Figure 8-11 shows the steps to read LED Short information. Wait at least one sub-period time between Step2
and Step3 command.
Figure 8-11. Steps to Read LED Short Information
8.3.5.4.3 LSD Caterpillar Removal
Figure 8-12 shows the LSD caterpillar issue caused by short LED. Suppose the LED0-1 is a short LED. When it
scans to the line1 and the OUT1 is turned off, the OUT1 voltage is the same with scan line0 voltage because of
the short path of the LED0-1. At this time, there is a current path from the line0 to the GND through the LED1-1
and SW1-1, which causes LED1-1 light to be unwanted.
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Figure 8-12. LED Short Caterpillar
The LP5890 device implements internal circuits that can eliminate the caterpillar issue by short LEDs. As is
shown in Figure 8-12, the LED short caterpillar is caused by the voltage of the Vclamp on the line, so it can be
solved by adjusting the LSD_RM (see FC3 for more details) to let the voltage drop of the LED1-1 be smaller than
LED forward voltage.
8.4 Device Functional Modes
Figure 8-13 lists the device functional modes.
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Vcc Power Up
Initialization
PSin
Power Saving
Normal
PSout
UVLO
From all states
ISPin
ISPout
IREF Resistor Short
TSDin
TSDout
Thermal Shutdown
Figure 8-13. Functional Modes
•
•
•
•
•
Initialization: The device enters into Initialization when Vcc goes down to UVLO voltage. In this mode, all the
registers are reset. Entry can also be from any state.
Normal: The device enters the normal mode when Vcc is higher than UVLO threshold. The display process
is shown as below in normal mode.
Power Saving: The device automatically enters and gets out from the power save mode when it detects
the condition PSin and PSout. In this mode, all channels will turn off. PSin: after the device detects that the
display data of the next frame all equal to zero, it will enter to power save mode when the VSYNC comes.
PSout: after the device detects that there is non-zero display data of the next frame, it will get out from power
save mode immediately.
IREF Resistor Short Protection: The device automatically enters and gets out from the IREF Resistor Short
Protection mode when it detects the condition ISPin and ISPout. In this mode, all channels will turn off. ISPin:
the device detects that the reference voltage is smaller than 0.195 V. ISPout: the device detects that the
reference voltage is larger than 0.325 V.
Thermal Shutdown: The device automatically enters and gets out from the Thermal Shutdown mode when
it detects the condition TSDin and TSDout. In this mode, all channels will turn off. TSDin: the device detects
that the junction temperature exceeds 170° C. TSDout: the device detects that the junction temperature is
below 155° C.
8.5 Continuous Clock Series Interface
The continuous Clock Series Interface (CCSI) provides access to the programmable functions and registers,
SRAM data of the device. The interface contains two input digital pins. The pins are the serial data input (SIN)
and serial clock (SCLK). Moreover, there is an another wire called serial data output (SOUT) as the output digital
signal of the device. The SIN is set to HIGH when device is in idle status and the SCLK needs to be existent and
continuous all the time considering it is the clock source of internal Frequency Multiplier. The SOUT is used to
transmit the data or read the data of internal registers.
This protocol can support up to 32 devices cascaded in a data chain. The devices will receive the chip index
command after power up. The chip index command will configure addresses of the devices from 0x00 up to
0x1F according to the sequence that receives the command. Then the controller can communicate with all the
devices through the broadcast way or particular device through non-broadcast way.
The broadcast is mainly used to transmit function control commands. All the devices in a data chain will receive
the same data in this way. The non-broadcast is mainly used to transmit function control commands or display
data, and each device receives its own data in this way. These two ways are distinguished by the command
identification.
8.5.1 Data Validity
The data on DIN wire must be stable at rising edges of the SCLK.
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8.5.2 CCSI Frame Format
Figure 8-14 defines the format of the command and data transimission. There are four states in one frame.
• IDLE: SCLK is always existent and continuous, and DIN is always HIGH.
• START: DIN changes from HIGH to LOW after the IDLE states.
• DATA:
– Head_bytes: It is the command identifier, contains one 16-bit data and one check bit. It can be WRITE
COMMAND ID or READ COMMAND ID (see Register Maps for more details).
– Data_bytes_N: The Nth data-bytes, contains 3 × 17-bit data, each 17-bit data contains one 16-bit data
and one check bit. N is the number of devices cascaded in a data chain.
• END: The device recognizes continuous 18-bit HIGH on DIN, then returns to IDLE state.
• CHECK BIT: The check bit (17th bit) value is the NOT of 16th bit value, in order to avoid continuous 18-bit
HIGH (to distinguish with END).
SCLK
SIN
Head_bytes
Y...
Data_bytes_N
IDLE START
Data_bytes_1
End_bytes
DATA
END
IDLE
Figure 8-14. CCSI Frame
The IDLE state is not the necessary. That means the START state of next frame can connect to the END state of
current frame.
8.5.3 Write Command
Take m devices cascaded in a data chain for example.
8.5.3.1 Chip Index Write Command
The chip index is used to set the identification of the device cascaded in a data chain. When the first device
receives the chip index command, Head_bytes1, it sets the current address to 00h and meanwhile changes the
chip index command, Head_bytes2, then sends to the next device. When the device receives the Head_bytes2,
it sets the address to 01h and meanwhile changes the chip index command, Head_bytes3, then sends to the
next device. Likewise, all the cascaded devices get their unique identifications.
SOUT
Controller SCLK
SIN
Device_1
ST
Device_...
Head_bytes1
Device_m
END
ST
Head_bytes...
END
ST
Head_bytesm
END
Figure 8-15. Chip Index Write Command
8.5.3.2 VSYNC Write Command
The VSYNC is used to sync the display of each frame for the devices in a cascaded chain. The VSYNC is a
write-only command. The devices receive VSYNC command one time from the controller in each frame, and the
VSYNC command needs to be active for all devices at the same time.
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Since some devices receive the command earlier in the data chain, they need to wait until the last device
receives the command, then all the devices are active at that time. In order to realize such function, each device
needs to know its delay time from receiving VSYNC command to enabling VSYNC. The device uses some
register bits to restore the device number in a data chain. This number will minus the device identification, and
the result is the delay time of the device.
Since the sync function has been done by the device, the controller only needs to send the VSYNC command to
the first device in a data chain.
SOUT
Controller SCLK
SIN
Device_1
ST
Device_...
Head_bytes
Device_m
END
ST
Head_bytes
END
ST
END
Head_bytes
ST
Head_bytes
END
Figure 8-16. VSYNC Write Command
8.5.3.3 Soft_Reset Command
The Soft_Reset Command is used to reset all the function registers to the default value, except for SRAM data.
The format of this command is the same with VSYNC shown as VSYNC Write Command. The difference is the
headbytes.
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8.5.3.4 Data Write Command
The device implements two kinds of transmission formats, which are called broadcast and non-broadcast. With
broadcast way, the devices which are cascaded in a data chain receive the same data from the controller as
Data Write Command with Broadcast shows. With non-broadcast way, each device will receive its own data sent
from controller. The order of the data is the reverse of the order in which the device cascades as shown in Data
Write Command with Non-Broadcast.
For 48-bits RGB data, the Blue data is the first to be transmitted, then are the Green and the Red. Also, for all
bits in one frame, it is always the MSB transmitted first and the LSB transmitted last.
Here is the data write command with broadcast way. The devices copy to the internal registers after receiving the
data. Generally, it is used to write FC0-FC11 command and read LOD/LSD command.
SOUT
Controller SCLK
SIN
Device_1
ST
Device_...
Head_bytes
Device_m
END
Data
ST
Data
Head_bytes
ST
END
Head_bytes
END
Data
ST
Head_bytes
Data
END
Figure 8-17. Data Write Command With Broadcast
Figure 8-18 shows the timing diagram of the data write command with broadcast.
Figure 8-18. Data Write Command With Broadcast (Timing Diagram)
Here is the data write command with non-broadcast way. When the first device recognizes End_bytes, it cuts off
the last 51-bit (3×17-bit) data before End_bytes, and the left are shifted out from SOUT to the second device;
likewise, when the last device recognizes End_bytes from the former device, it cuts off the last 51-bit (3 × 17-bit)
data before End_bytes and the left are shifted out from SOUT. Generally, it is used for write SRAM command
(WRTGS), details about how to write a frame data into memory bank can be found in Write a Frame Data into
Memory Book.
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SOUT
Controller SCLK
SIN
Device_1
ST
Device_...
Head_bytes
Data_m
ST
Device_m
Data_...
Head_bytes
Data_1
Data_m
ST
END
Data_...
Head_bytes
END
Data_m
ST
END
Head_bytes
END
Figure 8-19. Data Write Command With Non-Broadcast
Figure 8-20 shows the timing diagram of the Data Write Command with Non-Broadcast.
Figure 8-20. Data Write Command with Non-Broadcast (Timing Diagram)
8.5.4 Read Command
The controller sends the read command. When the first device receives this command, it inserts its 48-bit
data before End_bytes, and meanwhile shifts out to the second device. When the second device receives this
command, it inserts its 48-bit data before End_bytes and meanwhile shifts out to the third device. The data of all
the device will be shifted out from the last device SOUT with this flow. The MSB is always transmitted first and
the LSB is transmitted last.
SOUT
Controller SCLK
SIN
Device_1
ST
Device_...
Head_bytes
Device_m
END
ST
Head_bytes
Data_1
ST
END
Head_bytes
Data_1
ST
Head_bytes
Data_...
Data_1
END
Data_...
Data_m
END
Figure 8-21. Data Read Command
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8.6 PWM Grayscale Control
8.6.1 Grayscale Data Storage and Display
8.6.1.1 Memory Structure Overview
The LP5890 implements a display memory unit to achieve high refresh rate and high contrast ratio in LED
display products. The internal display memory unit is divided into two BANKs: BANK A and BANK B. During the
normal operation, one BANK is selected to display the data of current frame, another is used to restore the data
of next frame. The BANK switcher is controlled by the BANK_SEL bit, which is an internal flag register bit.
After power on, BANK_SEL is initialized to 0, and BANK A is selected to restore the data of next frame.
Meanwhile, the data in BANK B is read out for display. When one frame has elapsed, the controller sends the
vertical synchronization (VSYNC) command to start the next frame. The BANK_SEL bit value is toggled and the
selection of the two BANKs reverses. Repeat this operation until all the frame images are displayed.
With this method, the LP5890 device can display the current frame image at a very high refresh rate. See Figure
8-22 for more details about the BANK-selection exchange operation.
R0-R15/G0-G15/B0-B15
R0-R15/G0-G15/B0-B15
PWM Generator
Timing Control
PWM Generator
Timing Control
48-bit
48-bit
Memory
BANK A
Memory
BANK B
Write Grayscale Data
for Next Frame
Read Grayscale Data for
Current Frame
BANK_SEL=0
Memory
BANK A
Memory
BANK B
Read Grayscale Data for
Current Frame
Write Grayscale Data
for Next Frame
BANK_SEL=1
VSYNC
VSYNC
48-bit
LSB
SIN
SCLK
48-bit
MSB
Common Shift Register
LSB
SOUT
MSB
SIN
SCLK
Common Shift Register
Select BANK A
SOUT
Select BANK B
Figure 8-22. Bank Selection Exchange Operation
8.6.1.2 Details of Memory Bank
Each memory BANK contains the frame-image grayscale data of all the 32 lines. Each line comprises sixteen
48-bit-width memory units. Each memory unit contains the grayscale data of the corresponding R/G/B channels.
Depending on the number of scan lines set in SCAN_NUM (FC0 bit 20 to bit 16), the total number of memory
units that must be written in one BANK is: 48 × the number of scan lines. For example, if the number of scan
lines is set to 32, then 1536 (32 × 48 = 1536) memory units must be written during each frame period.
Figure 8-23 shows the detailed memory structure of the LP5890 device.
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LSB
MSB
SIN
SCLK
Common Shift Register
SOUT
48-bit
Memory Units
R
Bit0
Bit1
Bit2
Bit0
Bit1
Bit2
Bit0
Bit1
Bit2
Bit0
Bit1
Bit2
Bit0
Bit1
Bit2
...
...
Bit0
Bit1
Bit2
...
Bit1
Bit2
Bit0
Bit1
Bit2
...
Bit0
Bit1
Bit2
Bit0
Bit1
Bit2
Bit0
Bit1
Bit2
...
Bit0
Bit1
Bit2
Bit0
Bit1
Bit2
Bit0
Bit1
Bit2
...
Bit1
Bit2
Bit0
Bit1
Bit2
Bit0
Bit1
Bit2
...
Bit16
Bit17
Bit18
Bit15
Bit16
Bit17
Bit18
Bit15
Bit16
Bit17
Bit18
...
...
...
...
Bit15
Bit16
Bit17
Bit18
Bit15
Bit16
Bit17
Bit18
Bit15
Bit16
Bit17
Bit18
...
...
...
...
Bit15
Bit16
Bit17
Bit18
Bit15
Bit16
Bit17
Bit18
Bit15
Bit16
Bit17
Bit18
...
...
...
...
Bit15
Bit16
Bit17
Bit18
Bit15
Bit16
Bit17
Bit18
Bit15
Bit16
Bit17
Bit18
...
...
...
...
Bit15
Bit16
Bit17
Bit18
Bit15
Bit16
Bit17
Bit18
Bit1
Bit2
...
...
...
...
B
...
...
...
...
Bit31
Bit32
Bit33
Bit34
Bit31
Bit32
Bit33
Bit34
Bit31
Bit32
Bit33
Bit34
...
...
...
...
Bit31
Bit32
Bit33
Bit34
Bit31
Bit32
Bit33
Bit34
Bit31
Bit32
Bit33
Bit34
...
Bit15
Bit16
Bit17
Bit18
Bit15
Bit16
Bit17
Bit18
Bit15
Bit16
Bit17
Bit18
...
...
Bit0
Bit15
...
Bit0
Bit0
G
...
...
...
...
Bit31
Bit32
Bit33
Bit34
Bit31
Bit32
Bit33
Bit34
Bit31
Bit32
Bit33
Bit34
...
...
...
...
Bit31
Bit32
Bit33
Bit34
Bit31
Bit32
Bit33
Bit34
Bit31
Bit32
Bit33
Bit34
...
...
...
...
Bit31
Bit32
Bit33
Bit34
Bit31
Bit32
Bit33
Bit34
Bit31
Bit32
Bit33
Bit34
Bit31
Bit32
Bit33
Bit34
Bit31
Bit32
Bit33
Bit34
...
Bit15
Bit16
Bit17
Bit18
Bit47 R0/G0/B0
...
...
...
...
Bit47 R0/G0/B0
Bit47 R1/G1/B1
Line0
Bit47 R15/G15/B15
Line1
...
Bit47 R0/G0/B0
...
...
...
...
Bit47 R0/G0/B0
...
...
...
...
Bit47 R0/G0/B0
Bit32
Bit33
Bit34
...
Bit47 R1/G1/B1
Line31
Bit47 R15/G15/B15
Bit47 R1/G1/B1
Line0
Bit47 R15/G15/B15
Bit47 R1/G1/B1
Line1
BANK B
Bit47 R15/G15/B15
...
...
Bit31
BANK A
Bit47 R15/G15/B15
...
...
...
...
...
...
...
...
BANK_SEL
Bit47 R1/G1/B1
...
...
...
...
...
...
...
...
...
CHANNEL_COUNT
LINE_COUNT
...
...
...
...
...
Bit47 R0/G0/B0
Bit47 R1/G1/B1
Line31
Bit47 R15/G15/B15
Figure 8-23. LP5890 Memory-unit Structure
8.6.1.3 Write a Frame Data into Memory Bank
After power on, the LP5890 internal flag BANK_SEL, and counters LINE_COUNT, CHANNEL_COUNT, are all
initialized to 0. Thus, the memory unit of channel R0/G0/B0, locating in line 0 of BANK A, is selected to restore
the data transimitted the first time after VSYNC command.
When the first WRTGS command is received, all the data in the common shift register is latched into the
memory unit of channel R0/G0/B0, locating in line 0 of BANK A. Then CHANNEL_COUNT increases by 1 and
LINE_COUNT stays the same. Thus, the memory unit of channel R1/G1/B1, locating in line 0 of BANK A, is
selected to restore the data transimitted the second time after VSYNC command.
When the second WRTGS command is received, all the data in the common shift register is latched into the
memory unit of channel R1/G1/B1, locating in line 0 of BANK A. Then CHANNEL_COUNT increases by 1 and
LINE_COUNT stays the same. Thus, the memory unit of channel R2/G2/B2, locating in line 0 of BANK A, is
selected to restore the data transimitted the third time after VSYNC command.
Repeat the grayscale-data-write operation until the 16th WRTGS command is received. Then
CHANNEL_COUNT is reset to 0 and LINE_COUNT increases by 1. Thus, the memory unit of channel
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R0/G0/B0, locating in line 1 of BANK A, is selected to restore the data transimitted the 17th time after VSYNC
command.
Repeat this operation for each line until the LINE_COUNT exceeds the number of scan lines set in the
SCAN_NUM (See FC0 register bit20-16 ) and all scan lines have been updated with new GS data, which means
one frame of GS data is restored into the memory BANK. Then the LINE_COUNT is reset to 0.
8.6.2 PWM Control for Display
In order to increase the refreash rate in time-multiplexing display system, an DS-PWM (Dynamic SpectrumPulse Width Modulation) algorithm is proposed in this device. One frame is divided into many segments shown
as below. Note that one frame is divided into n sub-periods, n is set by SUBP_NUM (FC0 register bit23-21),
and each sub-period is divided into 32 segments for 32 scan lines. Each segment contains GS GCLKs time for
grayscale data display and T_SW GCLKs time for switching lines. GS is configured by the SEG_LENGTH (FC1
register bit9-0 in Table 8-8), and T_SW is the line switch time, which is configured by the LINE_SWT (see FC1
register bit 40-37 in Table 8-8).
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Frame (display period)
Sub-period
SP0
SP1
SPn-1
Segment
SP0_L0
SP0_L1
SP0_L31
SP1_L0
SP1_L1
SP1_L31
Grayscale data display (GS × GCLK)
SPn-1_L0
SPn-1_L1
SPn-1_L31
Line switch (T_SW × GCLK)
Note that, SP0: Sub-period 0, L0: Scan line 0
Figure 8-24. DS-PWM Algorithm with 32 Scan Lines
The DS-PWM can not only increse the refresh rate meanwhile keep the same frame rate, but also decrease the
brightness loss in low grayscale, which can smoothly increase the sub-period number when the grayscale data
increases.
In order to achieve ultra-low luminance, the LED driver should have the ability to output a very short current
pulse (1 GCLK time), however, because of the parasitic capacitor of the LEDs, such pulse could not turn on the
LEDs. And the larger GCLK frequency is, the harder to turn on LEDs.
DS-PWM algorithm has a parameter called subperiod threshold, which is used to calculate when to change
subperiod number according to the giving grayscale data. Subperiod threshold defines the LED minimum turn-on
time, so as to conquer the current loss caused by LED parasitic capacitor. Subperiod threshold is configured by
the SUBP_TH_R/G/B (FC1 register bit24-10 in Table 8-8).
With DS-PWM algorithm, the brightness has smoothly increased with the gradient grayscale data.
8.7 Register Maps
Table 8-5. Register Maps
REGISTER NAME
TYPE
WRITE COMMAND
ID
READ COMMAND
ID
DESCRIPTION
FC0
R/ W
AA00h
AA60h
Common configuration
FC1
R/ W
AA01h
AA61h
Common configuration
FC2
R/ W
AA02h
AA62h
Common configuration
FC3
R/ W
AA03h
AA63h
Common configuration
FC4
R/ W
AA04h
AA64h
Common configuration
FC10
R/ W
AA0Ah
AA6Ah
Locate the line for LOD
FC11
R/ W
AA0Bh
AA6Bh
Locate the line for LSD
FC12
R
AA6Ch
Read the lines' warning of LOD
FC13
R
AA6Dh
Read the lines' warning of LSD
FC14
R
AA6Eh
Read the channel's warning of LOD
FC15
R
AA6Fh
Read the channel's warning of LSD
Chip Index
R/ W
AA10h
VSYNC
W
AAF0h
Write VSYNC command
Soft_Reset
W
AA80h
Reset the all the registers expect the SRAM
AA70h
Read/Write chip index
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Table 8-5. Register Maps (continued)
REGISTER NAME
TYPE
WRITE COMMAND
ID
SRAM
W
AA30h
READ COMMAND
ID
DESCRIPTION
Write or read the SRAM data
Table 8-6. Access Type Codes
Access Type
Code
Description
R
Read
W
Write
Read Type
R
Write Type
W
Reset or Default Value
-n
Value after reset or the default
value
8.7.1 FC0
FC0 is shown in FC0 Register and described in FC0 Register Field Descriptions.
Figure 8-25. FC0 Register
47
46
45
44
43
42
41
40
39
38
37
36
MOD_SIZE
RESERVED
GRP_DLY_B
GRP_DLY_G
GRP_DLY_R
R/W-00b
R-01b
R/W-000b
R/W-000b
R/W-000b
31
30
15
29
28
27
26
25
24
23
22
21
20
35
34
33
RESERVED
R-0b
19
18
FREQ_MUL
FREQ_
MOD
RESERVED
SUBP_NUM
SCAN_NUM
R/W-0111b
R/
W-0b
R-000b
R/W-000b
R/W-01111b
14
13
12
11
10
9
8
7
6
5
4
32
3
2
LODR
M_EN
PSP_MOD
PS_EN
RESERVED
PDC_E
N
RESERVED
CHIP_NUM
R/
W-0b
R/W-00b
R/
W-0b
R-000b
R/
W-1b
R-000b
R/W-00111b
R/W-00b
17
16
1
0
Table 8-7. FC0 Register Field Descriptions
Bit
Field
Type
Reset
Description
4-0
CHIP_NUM
R/W
00111b
Set the device number
00000b: 1 device
...
01111b: 16 devices
...
11111b: 32 devices
7-5
RESERVED
R
000b
PDC_EN
R/W
1b
RESERVED
R
000b
PS_EN
R/W
0b
Enable or disable the power saving mode
0b: disable
1b: enable
PSP_MOD
R/W
00b
Set the powering saving plus mode
00b: disable
01b: save power at high level
10b: save power at middle level
11b: save power at low level
8
11-9
12
14-13
34
Enable or disable pre-discharge function
0b: disable
1b: enable
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Table 8-7. FC0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
15
LODRM_EN
R/W
0b
Enable or disable the LED open load removal function
0b: disable
1b: enable
20-16
SCAN_NUM
R/W
01111b
Set the scan line number
00000b: 1 line
...
01111b: 16 lines
...
11111b: 32 lines
23-21
SUBP_NUM
R/W
000b
Set the subperiod number
000b: 16
001b: 32
010b: 48
011b: 64
100b: 80
101b: 96
110b: 112
111b: 128
26-24
RESERVED
R
000b
27
FREQ_MOD
R/W
0b
Set the GCLK multiplier mode
0b: low frequency mode, 40MHz to 80MHz
1b: high frequency mode, 80MHz to 160MHz
31-28
FREQ_MUL
R/W
0111b
Set the GCLK multiplier frequency
0000b: 1 x SCLK frequency
...
0111b: 8 x SCLK frequency
...
1111b: 16 x SCLK frequency
34-32
RESERVED
R
000b
37-35
GRP_DLY_R
R/W
000b
Set the Red group delay, forward PWM mode only
000b: no delay
001b: 1 GCLK
010b: 2 GCLK
011b: 3 GCLK
100b: 4 GCLK
101b: 5 GCLK
110b: 6 GCLK
111b: 7 GCLK
40-38
GRP_DLY_G
R/W
000b
Set the Green group delay, forward PWM mode only
000b: no delay
001b: 1 GCLK
010b: 2 GCLK
011b: 3 GCLK
100b: 4 GCLK
101b: 5 GCLK
110b: 6 GCLK
111b: 7 GCLK
43-41
GRP_DLY_B
R/W
000b
Set the Blue group delay, forward PWM mode only
000b: no delay
001b: 1 GCLK
010b: 2 GCLK
011b: 3 GCLK
100b: 4 GCLK
101b: 5 GCLK
110b: 6 GCLK
111b: 7 GCLK
45-44
RESERVED
R
01b
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Table 8-7. FC0 Register Field Descriptions (continued)
Bit
47-46
36
Field
Type
Reset
Description
MOD_SIZE
R/W
00b
Set the module size
00b: 2 devices stackable operation
01b: 1 device non-stackable operation, SCAN_NUM must Vf(R) + 0.35 V (10-mA constant current example), the VG = VB > Vf(G/B) + 0.35 V
(10-mA constant current example), and here Vf(R), Vf(G/B) are representative for the maximum forward voltage
of red, green/blue LEDs.
Also in order to simplify the power design, VCC can be connected to VR power rail.
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11 Layout
11.1 Layout Guidelines
•
•
•
•
•
•
Place the decoupling capacitor near the VCC/VR, VG/VB pins and GND plane.
Place the current programming resistor RIREF close to IREFpin and GND plane.
Route the GND thermal pad as widely as possible for large GND currents. Maximum GND current is
approximately 2 A for two devices (96-CH × 20 mA = 1.92 A).
The Thermal pad must be connected to GND plane because the pad is used as power ground pin internally.
There is a large current flow through this pad when all channels turn on. Furthermore, this pad should be
connected to a heat sink layer by thermal via to reduce device temperature. For more information about
suggested thermal via pattern and via size, see the PowerPAD™ Thermally Enhanced Package Application
Report.
Routing between the LED Anode side and the device OUTXn pin should be as short and straight as possible
to reduce wire inductance.
The line switch pins should be located in the middle of the matrix, which should be laid out as symmetrically
as possible.
11.2 Layout Example
In order to simplify the system power rails design, we suggest that VR, VCC use one power rail, and VG, VB use
another power rail. Figure 11-1 gives an example for power rails routing.
Connect the GND pin to thermal pad on board with the shortest wire and the thermal pad is connected to GND
plane with the vias, as many as possible to help the power dissipation.
32 RGB LEDs
GND
VR
VCC
C
VR
VR/VCC
C
GND
GND
TLC6983
GND
VG
VG
GND
VB
C
VB
GND
C
32 Lines
VG/VB
VB
VB
VG
C
VG
C
GND
GND
TLC6983
GND
GND
VR
VR
VCC
GND
GND
C
C
VR/VCC
Figure 11-1. Power Rails Routing Suggestion
Figure 11-2 gives an example for line routing. Connect the line switch to the center of the line bus, so as to
uniform the current flowing from the line switch to the left side and right side LEDs in white grayscale. With
this connection, the unbalance of the parasitic inductor from the routing will be the smallest and the display
performance will be better, especially in low grayscale condition.
56
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Figure 11-2. Line Routing Suggestion
Figure 11-3 gives an example for channel routing with the shortest wire. With this connection, the channel to the
LED path is the shortest, which can reduce the wire inductance, and be a benefit to the performance. However,
the data transmission sequence should be adjusted to follow the pins routing map. For example, R0 connects to
column 15 (LED15 ). The first data should be column 15 (LED15) rather than column 0 (LED0).
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Figure 11-3. Channel Routing Suggestion with Shortest Wire
Figure 11-4 gives an example for channel routing with pin number sequence. With this connection, the data
transmission sequence will be the same with pin number sequence. For example, R0 connects to column 0
(LED0 ). The first data will be column 0 (LED0). However, with this connection, the inductance for each channel
may be different, which might bring a slight difference for the worst case.
58
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Figure 11-4. Channel Routing Suggestion with Channel Order Sequence
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
60
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
LP5890RRFR
ACTIVE
VQFN
RRF
76
2000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
LP5890
LP5890ZXLR
ACTIVE
NFBGA
ZXL
96
2500
RoHS & Green
SNAGCU
Level-3-260C-168 HR
-40 to 85
LP5890
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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