TLC6984ZXLR

TLC6984 SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 TLC6984 48 Current Sources, 64 Scans, Common Cathode Matrix LED Display Driver 1 Features • • • • • • Separated VCC and VR/G/B power supply – VCC voltage range: 2.5 V – 5.5 V – VR/G/B voltage range: 2.5 V – 5.5 V 48 current source channels from 0.2 mA to 20 mA – Channel-to-channel accuracy: ±0.5% (typ.), ±2% (max.); device-to-device accuracy: ±0.5% (typ.), ±2% (max.) – Low knee voltage: 0.26 V (max.) when IOUT = 5 mA – 3-bits (8 steps) global brightness control – 8-bits (256 steps) color brightness control – Maximum 16-bits (65536 steps) PWM grayscale control 16 scan line switches with 190-mΩ RDS(ON) Ultra low power consumption – Independent VCC down to 2.5 V – Lowest ICC down to 3.6 mA with 50-MHz GCLK – Intelligent power saving mode with ICC down to 0.9mA Built-in SRAM to support 1 – 64 multiplexing – Single device with 16 multiplexing to support 48 × 16 LEDs or 16 × 16 RGB pixels – Dual devices stackable with 32 multiplexing to support 96 × 32 LEDs or 32 × 32 RGB pixels – Three devices stackable with 48 multiplexing to support 144 × 48 LEDs or 48 × 48 RGB pixels – Four devices stackable with 64 multiplexing to support 192 × 64 LEDs or 64 × 64 RGB pixels High speed and low EMI Continuous Clock Series Interface (CCSI) – Only three wires: SCLK / SIN / SOUT – External 25-MHz (max.) SCLK with dual-edge transmission mechanism (internal 50 MHz) • – Internal frequency multiplier to support high GCLK frequency Optimized display performance – Programmable scan line sequence – Upside and downside ghosting removal – Low grayscale enhancement – LED open, short, and weak short detection and removal 2 Applications • • Narrow Pixel Pitch (NPP) LED display Mini and micro-LED products 3 Description With the pixel density getting higher in narrow pixel pitch LED display or mini and micro-LED products, there are urgent demands for LED drivers to address those critical challenges. These challenges include ultra high integration to meet the strict board space limitation, ultra low power to minimize the system level power dissipation, new interface to enable high data refresh rate with low EMI impact, and excellent display performance to serve the growing needs of higher display quality. Device Information PART NUMBER TLC6984 (1) PACKAGE(1) BODY SIZE (NOM) VQFN (76) 9.00 mm × 9.00 mm BGA (96) 6.00 mm × 6.00 mm For all available packages, see the orderable addendum at the end of the data sheet. TLC6984 with Four Devices Stackable Connection An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Description (continued).................................................. 3 6 Pin Configuration and Functions...................................4 7 Specifications.................................................................. 6 7.1 Absolute Maximum Ratings........................................ 6 7.2 ESD Ratings............................................................... 6 7.3 Recommended Operating Conditions.........................6 7.4 Thermal Information....................................................6 7.5 Electrical Characteristics.............................................7 7.6 Timing Requirements................................................ 10 7.7 Switching Characteristics..........................................10 7.8 Typical Characteristics.............................................. 11 8 Detailed Description......................................................13 8.1 Overview................................................................... 13 8.2 Functional Block Diagram......................................... 14 8.3 Feature Description...................................................14 8.4 Device Functional Modes..........................................26 8.5 Continuous Clock Series Interface............................27 8.6 PWM Grayscale Control........................................... 33 8.7 Register Maps...........................................................36 9 Application and Implementation.................................. 51 9.1 Application Information............................................. 51 9.2 Typical Application.................................................... 51 10 Power Supply Recommendations..............................59 11 Layout........................................................................... 60 11.1 Layout Guidelines................................................... 60 11.2 Layout Example...................................................... 60 12 Device and Documentation Support..........................64 12.1 Documentation Support.......................................... 64 12.2 Receiving Notification of Documentation Updates..64 12.3 Support Resources................................................. 64 12.4 Trademarks............................................................. 64 12.5 Electrostatic Discharge Caution..............................64 12.6 Glossary..................................................................64 13 Mechanical, Packaging, and Orderable Information.................................................................... 65 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (March 2022) to Revision D (July 2022) Page • Updated the BGA package information throughout the document..................................................................... 1 • Changed the description of FREQ_MOD......................................................................................................... 37 • Changed the name of register field...................................................................................................................43 Changes from Revision B (March 2022) to Revision C (March 2022) Page • Updated the GCLK descriptions in the Features and Description (continued) sections..................................... 1 Changes from Revision A (December 2021) to Revision B (March 2022) Page • Changed data sheet status from "Advance Information" to "Production Data"...................................................1 Changes from Revision * (November 2021) to Revision A (December 2021) Page • First public release of data sheet........................................................................................................................1 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 5 Description (continued) The TLC6984 is a highly-integrated, common cathode matrix LED display driver with 48 constant current sources and 16 scanning FETs. Besides driving 16 × 16 and 32 × 32 RGB LED pixels as TLC6983, three TLC6984s are capable of driving 48 × 48 RGB LED pixels and stacking four TLC6984s can drive 64 × 64 RGB LED pixels. To achieve low-power consumption, the device supports separated power supplies for the red, green, and blue LEDs by its common cathode structure. Furthermore, the operation power of the TLC6984 is significantly reduced by ultra-low operation voltage range (Vcc down to 2.5 V) and ultra-low operation current (Icc down to 3.6 mA). The TLC6984 implements a high-speed, dual-edge transmission interface to support high device count daisychained and high-refresh rate while minimizing electrical-magnetic interference (EMI). The device supports up to 25-MHz SCLK (external) and 40-MHz to 160-MHz GCLK (internal, typical values) with different GCLK multiplier modes and frequencies. Meanwhile, the device integrates enhanced circuits and intelligent algorithms to solve the various display challenges in Narrow Pixel Pitch (NPP) LED display applications and mini and micro-LED products. These challenges include dim at the first scan line, upper and downside ghosting, non-uniformity in low grayscale, coupling, and caterpillar caused by open or short LEDs, which make the TLC6984 a perfect choice in such applications. The TLC6984 also implements LED open, weak-short, short detections and removals during operations and can also report this information out to the accompanying digital processor. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 3 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Line3 Line4 Line5 Line6 Line7 Line8 Line9 Line10 Line11 Line12 Line13 Line14 Line15 SCLK SIN SOUT 71 70 69 68 67 66 65 64 63 62 61 60 59 58 Line2 74 72 Line1 75 73 Line0 76 6 Pin Configuration and Functions R0 1 57 R15 G0 2 56 G15 B0 3 55 B15 R1 4 54 R14 G1 5 53 G14 B1 6 52 B14 GND 7 51 VG VCC 8 50 VG VR 9 49 VB VR 10 48 VB R2 11 47 R13 G2 12 46 G13 B2 13 45 B13 R3 14 44 R12 G3 15 43 G12 B3 16 42 B12 R4 17 41 R11 G4 18 40 G11 B4 19 39 B11 35 36 37 38 B10 G10 R10 34 G9 R9 33 B9 32 R8 30 B8 31 29 B7 G8 28 27 R7 G7 26 B6 25 G6 23 B5 24 22 G5 R6 21 R5 IREF 20 GND Figure 6-1. TLC6984 RRF Package 76-Pin VQFN With Exposed Thermal Pad Top View 1 2 3 4 5 6 7 8 9 10 11 A L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 B L2 R1 B0 G0 R0 NC SOU T SIN SCL K NC L14 C L1 G1 GND L15 D L0 B1 E GND GND F VCC G GND GND GND GND GND GND GND GND GND GND R15 R14 VG R2 R3 GND GND GND G15 G14 VG VR G2 G3 GND GND GND B15 B14 VB H VR B2 B3 R7 B8 B9 B10 R13 VB J IREF R4 G13 B13 K G4 B4 R6 G6 G7 G8 G9 G10 B11 R12 G12 L R5 G5 B5 B6 B7 R8 R9 R10 G11 R11 B12 Figure 6-2. TLC6984 ZXL Package 96-Pin BGA Top View 4 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Table 6-1. Pin Functions PIN I/O DESCRIPTION NAME RRF NO. ZXL NO. IREF 20 J1 I Pin for setting the maximum constant-current value. Connecting an external resistor between IREF and GND sets the maximum current for each constantcurrent output channel. When this pin is connected directly to GND, all outputs are forced off. The external resistor must be placed close to the device. VCC 8 F1 I Device power supply VR 9, 10 G1, H1 I Red LED power supply VG 51, 50 E11, F11 I Green LED power supply VB 49, 48 G11, H11 I Blue LED power supply R0-R15 1, 4, 11, 14, B5, B2,F2, F4, 17, 21, 24, J2, L1, K3, H5, 27, 32, 35, L6, L7, L8, L10, 38, 41, 44, K10, H10, E10, 47, 54, 57 E8 O Red LED constant-current output G0-G15 2, 5, 12, 15, B4, C2, G2, G4, 18, 22, 25, K1, L2, K4, K5, 28, 31, 34, K6, K7, K8, L9, 37, 40, 43, K11, J10, F10, 46, 53, 56 F8 O Green LED constant-current output B0-B15 3, 6, 13, 16, B3, D2, H2, H4, 19, 23, 26, K2, L3, L4, L5, 29, 30, 33, H6, H7, H8, K9, 36, 39, 42, L11, J11, G10, 45, 52, 55 G8 O Blue LED constant-current output LINE0LINE15 76, 75, 74, 73, 72, 71, 70, 69, 68, 67, 66, 65, 64, 63, 62, 61 D1, C1, B1, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, B11, C11 O Scan lines SCLK 60 B9 I Clock-signal input pin SIN 59 B8 I Serial-data input pin SOUT 58 B7 O Serial data output pin GND 7 C10, E1, E2, D5, D6, D7, D8, D10, D11, E1,E2, E4, E5, E6,E7, F5, F6, F7,G5, G6, G7 — Power-ground reference Thermal pad — — — The thermal pad and the GND pin must be connected together on the board. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 5 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 7 Specifications 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC –0.3 6 V VR/G/B –0.3 6 V IREF, SCLK, SIN, SOUT, VSYNC –0.3 6 V RX/GX/BX –0.3 6 V LINE0 to LINE15 –0.3 6 V Operating junction temperature, TJ –40 150 °C Storage temperature, Tstg –55 150 °C Voltage (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. 7.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) UNIT ±4000 Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) V ±1000 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VCC Device supply voltage VLEDR/G/B LED supply voltage VIH High level logic input voltage (SCLK, SIN, VSYNC) VIL Low level logic input voltage (SCLK, SIN, VSYNC) IOH High level logic output current (SOUT) IOL Low level logic output current (SOUT) ICH Constant output source current ILINE Line scan switch load current TA Ambient operating temperature NOM MAX UNIT 2.5 5.5 V 2.5 5.5 V 0.7 × VCC V 0.3 × VCC 0.2 V –2 mA 2 mA 20 mA 0 2 A –40 85 °C 7.4 Thermal Information TLC6984 THERMAL RRF (VQFN) ZXL (BGA) 76 PINS 96 PINS UNIT RθJA Junction-to-ambient thermal resistance 22.2 33.5 °C/W RθJC(top) Junction-to-case (top) thermal resistance 10.7 18.6 °C/W RθJB Junction-to-board thermal resistance 7.2 11.7 °C/W ψJT Junction-to-top characterization parameter 0.1 0.3 °C/W ψJB Junction-to-board characterization parameter 7.1 11.6 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance 1.7 (1) 6 METRIC(1) °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 7.5 Electrical Characteristics At VCC = VR = 2.8 V, VG/B = 3.8 V and TA = –40°C to +85°C; Typical values are at TA = 25°C (unless otherwise specified) PARAMETER TEST CONDITIONS VCC Device supply voltage VUVR Undervoltage restart VCC rising VUVF Undervoltage shutdown VCC falling VUV(HYS) Undervoltage shutdown hysteresis ICC Device supply current MIN TYP 2.5 MAX UNIT 5.5 V 2.3 V 2.0 V 0.1 V SCLK/SIN = 10 MHz, MPSM_EN = 1bit, Matrix PSM enable, internal GCLK off, GSn = 0000h, BC = 2h, CCR/G/B = 63h, PS_EN= 1h, VOUTn = floating, RIREF = 7.8 kΩ (In intelligent power save mode) 0.9 mA SCLK/SIN = 10 MHz, Standby enable, internal GCLK off, GSn = 0000h, BC = 2h, CCR/G/B = 63h, PS_EN= 1h, VOUTn = floating, RIREF = 7.8 kΩ (In intelligent power save mode) 0.9 mA SCLK/SIN = 10 MHz, PSP_MOD = 1bit, internal GCLK=50MHz, GSn = 0000h, BC = 2h, CCR/G/B = 63h, PS_EN= 1h, VOUTn = floating, RIREF = 7.8 kΩ (In power save mode) 3.6 mA SCLK = 10 MHz, internal GCLK = 50 MHz, GSn = 1FFFh, BC = 2h, CCR/G/B = 63h,VOUTn = floating, RIREF = 7.8 kΩ, ICH = 2 mA 3.6 mA SCLK = 10 MHz, internal GCLK = 100 MHz, GSn = 1FFFh, BC = 2h, CCR/G/B = 63h, VOUTn = floating, RIREF = 7.8 kΩ, ICH = 2 mA 4.9 mA VR/G/B LED supply voltage VIH High level input voltage (SCLK, SIN) VIL Low level input voltage (SCLK, SIN) VOH High level output voltage (SOUT) IOH = –2 mA at SOUT VOL Low level output voltage (SOUT) IOL = 2 mA at SOUT ILOGIC Logic pin current (SCLK, SIN) SCLK/SIN = VCC or GND RDS(ON) Scan switches' on-state resistance (LINE0 to LINE15) VCC = 2.8 V, TA= 25°C 190 mΩ Reference voltage SCLK/SIN = GND, internal GCLK= 0MHz, GSn = 0000h, BC = 2h, CCR/G/B = 63h, VOUTn = floating, RIREF = 7.8 kΩ 0.8 V VIREF 2.5 5.5 0.7 × VCC V V VCC-0.4 -1 0.3 × VCC V VCC V 0.4 V 1 uA Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 7 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 7.5 Electrical Characteristics (continued) At VCC = VR = 2.8 V, VG/B = 3.8 V and TA = –40°C to +85°C; Typical values are at TA = 25°C (unless otherwise specified) PARAMETER VKNEE ICH(LKG) ΔIERR(CC) 8 Channel knee voltage (R0-R15 / G0-G15 / B0-B15) Channel leakage current (R0R15 / G0-G15 / B0-B15) Constant-current channel to channel deviation (R0-R15 / G0G15 / B0-B15)(1) MAX UNIT VLEDR/G/B ≥ 2.8 V, all channel outputs on, output current at 1 mA TEST CONDITIONS MIN TYP 0.25 V VLEDR/G/B ≥ 2.8 V, all channel outputs on, output current at 5 mA 0.26 V VLEDR/G/B ≥ 2.8 V, all channel outputs on, output current at 10 mA 0.3 V VLEDR/G/B ≥ 2.8 V, IMAX = 1b, all channel outputs on, output current at 15 mA 0.37 V VLEDR/G/B ≥ 2.8 V, IMAX=1b, all channel outputs on, output current at 20 mA 0.41 V 1 uA Channel voltage at 0 V All CHn = on, BC = 00h, CC = 31h, VOUTn = (VLED-1)V, RIREF = 19.05 kΩ (ICH = 0.2-mA target), TA = 25°C, includes the VIREF tolerance, at same color grouped outputs of R0-R15 / G0-G15 / B0-B15 ±1 ±2.5 % All CHn = on, BC = 00h, CC = 7Dh, VOUTn = (VLED-1)V, RIREF = 19.05 kΩ (ICH = 0.5-mA target), TA = 25°C, includes the VIREF tolerance, at same color grouped outputs of R0-R15 / G0-G15 / B0-B15 ±0.5 ±1.5 % All CHn = on, BC = 00h, CC = FBh, VOUTn = (VLED-1)V, RIREF = 19.05 kΩ (ICH = 1-mA target), TA = 25°C, includes the VIREF tolerance, at same color grouped outputs of R0-R15 / G0-G15 / B0-B15 ±0.5 ±1.5 % All CHn = on, BC = 2h, CC = FBh, VOUTn = (VLED-1)V, RIREF = 7.8 kΩ (ICH = 5-mA target), TA = 25°C, includes the VIREF tolerance, at same color grouped outputs of R0-R15 / G0-G15 / B0-B15 ±0.5 ±2 % All CHn = on, BC = 6h, CC = A7h, VOUTn = (VLED-1)V, RIREF = 7.8 kΩ (ICH = 10-mA target), TA = 25°C, includes the VIREF tolerance, at same color grouped outputs of R0-R15 / G0-G15 / B0-B15 ±0.5 ±2 % All CHn = on, BC = 7h, CC = FBh, IMAX=1b, VOUTn = (VLED-1)V, RIREF = 6.8 kΩ (ICH = 20-mA target), TA = 25°C, includes the VIREF tolerance, at same color grouped outputs of R0-R15 / G0-G15 / B0B15 ±0.5 ±2.5 % Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 7.5 Electrical Characteristics (continued) At VCC = VR = 2.8 V, VG/B = 3.8 V and TA = –40°C to +85°C; Typical values are at TA = 25°C (unless otherwise specified) PARAMETER ΔIERR(DD) Constant-current device to device deviation (R0-R15 / G0G15 / B0-B15)(2) TYP MAX UNIT All CHn = on, BC = 00h, CC = 31h, VOUTn = (VLED-1)V, RIREF = 19.05 kΩ (ICH = 0.2-mA target), TA = 25°C, includes the VIREF tolerance, at same color grouped outputs of R0-R15 / G0-G15 / B0-B15 TEST CONDITIONS MIN ±1 ±2.5 % All CHn = on, BC = 00h, CC = 7Dh, VOUTn = (VLED-1)V, RIREF = 19.05 kΩ (ICH = 0.5-mA target), TA = 25°C, includes the VIREF tolerance, at same color grouped outputs of R0-R15 / G0-G15 / B0-B15 ±0.5 ±1.5 % All CHn = on, BC = 00h, CC = FBh, VOUTn = (VLED-1)V, RIREF = 19.05 kΩ (ICH = 1-mA target), TA = 25°C, includes the VIREF tolerance, at same color grouped outputs of R0-R15 / G0-G15 / B0-B15 ±0.5 ±1 % All CHn = on, BC = 2h, CC = FBh, VOUTn = (VLED-1)V, RIREF = 7.8 kΩ (ICH = 5-mA target), TA = 25°C, includes the VIREF tolerance, at same color grouped outputs of R0-R15 / G0-G15 / B0-B15 ±0.5 ±1.5 % All CHn = on, BC = 6h, CC = A7h, VOUTn = (VLED-1)V, RIREF = 7.8 kΩ (ICH = 10-mA target), TA = 25°C, includes the VIREF tolerance, at same color grouped outputs of R0-R15 / G0-G15 / B0-B15 ±0.5 ±2 % All CHn = on, BC = 7h, CC = FBh, IMAX=1b, VOUTn = (VLED-1)V, RIREF = 6.8 kΩ (ICH = 20-mA target), TA = 25°C, includes the VIREF tolerance, at same color grouped outputs of R0-R15 / G0-G15 / B0B15 ±0.5 ±2 % ΔIREG(LINE) Line regulation (R0-R15 / G0G15 / B0-B15)(3) VLED = 2.5 to 5.5 V, All CHn = on, VOUTn = (VLED-1)V, at same color grouped outputs of R0-R15 / G0-G15 / B0-B15 ±1 %/V ΔIREG(LOAD) Load regulation (R0-R15 / G0G15 / B0-B15)(4) VOUTn = (VLED-1)V to (VLED-3)V, VR=VG/B=VLED = 3.8 V, All CHn = on, at same color grouped outputs of R0-R15 / G0-G15 / B0-B15 ±1 %/V TTSD Thermal shutdown threshold 170 °C THYS Thermal shutdown hysteresis 15 °C (1) The deviation of each output in same color group (OUTR0-15 or OUTG0-15 or OUTB0-15) from the average of same color group ¿:%; = N + :0 (2) +:J F 1O × 100 + +:1 + ® + +:14 + +:15 16 constant current. The deviation is calculated by the formula. (X = R or G or B, n = 0-15) spacer The deviation of the average of constant-current in each color group from the ideal constant-current value. (X = R or G or B) : +:0 + +:1 + ® + +:14 + +:15 F Ideal Output Current 16 O × 100 ¿:%; = N Ideal Output Current Ideal current is calculated by the following equation: 8+4'( 1 + %%_4(KN %%_) KN %%_$) ++&'#._4(KN ) KN $) = × )#+0($%) × 4+4'( 256 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 9 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 spacer Line regulation is calculated by the following equation. (X = R or G or B, n = 0-15): IXn at VLED = 5.5 V − IXn at VLED = 2.5 V 100 ∆ %V = × 5.5 V − 2.5 V IXn at VLED = 2.5 V (3) (4) Load regulation is calculated by the following equation. (X = R or G or B, n = 0-15): IXn at VXn = 1 V − IXn at VXn = 3 V ∆ %V = × 3 V100 − 1 V IXn at VXn = 3 V spacer 7.6 Timing Requirements At VCC = VR = 2.8 V, VG/B = 3.8 V and TA = –40°C to +85°C; Typical values are at TA = 25°C (unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 25 MHz fSCLK Clock frequency (SCLK) tw(H1) High level pulse duration (SCLK) 18 ns tw(L1) Low level pulse duration (SCLK) 18 ns tsu(0) Setup time SIN to SCLK↑ 10 ns tsu(1) Setup time SIN to SCLK↓ 10 ns th(0) Hold time SCLK↑ to SIN↑↓ 2 ns th(1) Hold time SCLK↓ to SIN↑↓ 2 ns 7.7 Switching Characteristics At VCC = VR = 2.8 V, VG/B = 3.8 V and TA = –40°C to +85°C; Typical values are at TA = 25°C (unless otherwise specified) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tr Rise time (SOUT) VCC = 3.3 V, CSOUT = 30 pF 2 10 ns tf Fall time (SOUT) VCC = 3.3 V, CSOUT = 30 pF 2 10 ns tpd(0) Propagation delay SCLK↑ to SOUT↑↓, full temperature, CSOUT = 30 pF 3.5 14.2 ns tpd(1) Propagation delay SCLK↓ to SOUT↑↓, full temperature, CSOUT = 30 pF 3.5 14.2 ns tw(L1) (1) SCLK tw(H1) 50% tsu(0) SIN (1) th(0) tsu(1) th(1) 50% tpd(0) tpd(1) 90% SOUT 50% 10% tr tf (1). Input pulse rise and fall time is 2 ns typically. Figure 7-1. Timing and Switching Diagram (Dual Edge) 10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 7.8 Typical Characteristics 0.016 0.016 0.2 mA 1 mA 5 mA 10 mA 15 mA Output Current (A) 0.012 0.2 mA 1 mA 5mA 10 mA 15 mA 0.014 0.012 Output Current (A) 0.014 0.01 0.008 0.006 0.01 0.008 0.006 0.004 0.004 0.002 0.002 0 0 0 0.2 0.4 0.6 0.8 1 1.2 VLED - VCH (V) 1.4 1.6 1.8 2 0 Vcc = 2.8 V 11 0.6 0.8 1 1.2 VLED - VCH (V) 1.4 1.6 1.8 2 Figure 7-3. Channel Current vs (VLED-Vchannel) Voltage 1 -40oC 25oC 85oC 9 0.75 Constant Current Accuracy (%) 10 Output Current (mA) 0.4 Vcc = 5. 5 V Figure 7-2. Channel Current vs (VLED-Vchannel) Voltage 8 7 6 5 4 3 2 0.5 0.25 -40oC Min 25oC Min 85oC Min -40oC Max 25oC Max 85oC Max 0 -0.25 -0.5 -0.75 -1 1 -1.25 0 0 0.2 0.4 0.6 0.8 1 1.2 VLED - VCH (V) 1.4 1.6 1.8 0 2 Figure 7-4. Channel Current vs (VLED-Vchannel) Voltage 2 4 6 8 10 12 14 Output Current (mA) 16 18 20 Figure 7-5. Channel-to-Channel Accuracy vs Output Current 0.012 0.016 0.2 mA, BC = 00h 1 mA, BC = 02h 5 mA, BC = 02h 10 mA, BC = 06h 15 mA, BC = 06h 0.014 0.012 0.011 0.01 0.009 0.01 Icc (A) Output Current (A) 0.2 0.008 0.006 0.008 0.007 0.006 0.004 0.005 0.002 0.004 0 0 30 60 90 120 150 180 210 Color Control Code (Decimal) 240 Figure 7-6. Color Control Code vs Output Current 270 0.003 40 60 80 100 120 140 GCLK Frequency (MHz) 160 180 Figure 7-7. Icc Current vs GCLK Frequency Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 11 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 7.8 Typical Characteristics (continued) 4.68 4.66 4.64 Icc (mA) 4.62 4.6 4.58 4.56 4.54 4.52 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 Vcc Voltage (V) 4 4.2 4.4 4.6 GCLK = 80 MHz Figure 7-8. Icc Current vs Vcc Voltage 12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 8 Detailed Description 8.1 Overview The TLC6984 is a highly-integrated, common cathode LED-display driver with 48 constant current sources and 16 scanning FETs. A single TLC6984 is capable of driving 16 × 16 RGB LED pixels while stacking four TLC6984s can drive 64 × 64 RGB LED pixels. To achieve low-power consumption, the device supports separated power supplies for the red, green, and blue LEDs by its common cathode structure. Furthermore, the operation power of the TLC6984 is significantly reduced by ultra-low operation voltage range (VCC down to 2.5 V) and ultra-low operation current (ICC down to 3.6 mA). The TLC6984 supports per channel current from 0.2 mA to 20 mA, with typical 0.5% channel-to-channel current deviation and typical 0.5% device-to-device current deviation. The DC current value of all 48 channels is set by an external IREF resistor and can be adjusted by the 8-step global brightness control (BC) and the 256-step per-color group brightness control (CC_R/CC_G/CC_B). The TLC6984 implements a high-speed, dual-edge transmission interface to support high device count daisychained and high-refresh rate while minimizing electrical-magnetic interference (EMI). The TLC6984 supports up to 25-MHz SCLK (external) and up to 160-MHz GCLK (internal). Meanwhile, the device integrates enhanced circuits and intelligent algorithms to solve the various display challenges in Narrow Pixel Pitch (NPP) LED display applications and mini and micro-LED products: dim at the fist scan line, upper and downside ghosting, non-uniformity in low grayscale, coupling, caterpillar caused by open or short LEDs, which make the TLC6984 a perfect choice in such applications. The TLC6984 also implements LED open, weak-short, short detections and removals during operations and can also report this information out to the accompanying digital processor. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 13 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 8.2 Functional Block Diagram 8.3 Feature Description 8.3.1 Independent and Stackable Mode The TLC6984 can operate in two different modes: independent or stackable. In independent mode, a single TLC6984 can drive a 16 × 16 RGB LED matrix, while in stackable mode, up to four TLC6984s can be stacked together, which means the line switches of one device can be shared to the others. Stacking three TLC6984s can drive a 48 × 48 RGB LED matrix while stacking four TLC6984s can drive a 64 × 64 RGB matrix. The mode can be configured by the MOD_SIZE (see FC2 for more details). 8.3.1.1 Independent Mode Figure 8-1 shows an implementation of a 16 × 32 RGB LED matrix using two TLC6984s in independent mode. Each device is responsible for its own 16 ×16 RGB LED matrix which means that all the data for section A is stored in device 1 and the data for section B is stored in device 2. 14 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Figure 8-1. Two Devices in Independent Mode The unused line must be assigned to the last several lines of the device. For example, if there are only 14 scanning lines, then the two unused lines must be assigned to 1_LS14 and 1_LS15. 8.3.1.2 Stackable Mode Table 8-1 shows operating the TLC6984 in stackable mode. Table 8-1. Stackable Mode Mode Matrix Size Register Value Scan Sequence Mode1 16 × 32 000b D1, D2 independent Mode2 32 × 32 001b D1->D2 Mode3 48 × 48 010b D1->D2->D3 Mode4 48 × 48 011b D1->D3->D2 Mode5 48 × 64 100b D1->D2->D3 Mode6 48 × 64 101b D1->D3->D2 Mode7 64 × 64 110b D1->D2->D3->D4 Mode8 64 × 64 111b D1->D4->D2->D3 Figure 8-2 shows that device 2 must be rotated 180o relative to device 1. This action allows the position of line switches to be near the center column of the LED matrix for better routing. For device 1, the lines are connected sequentially (line switch 0 connected to scan line 1). However on device 2, it is connected in reverse order, with the 16th scan line is connected to line switch 15 and the 32th scan line is connected to line switch 0. Figure 8-2 shows the connection between two TLC6984 devices in stackable mode driving a 32 × 32 RGB LED pixels. The MOD_SIZE must be configured to 001b. Device1 supplies 16 line switches for the first 16 scan line, and device 2 supplies 16 line switches for scan line 17-32. The data for matrix sections A and C are stored in device 1, while matrix sections B and D data are stored in device 2. To make sure the scanning sequence is still from 1st line to 32nd line, the scan line switching order of the second device must be reversed, This configuration can be completed by the SCAN_REV (see FC4 for more details). Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 15 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Physical Line0 A 1_LS0 B ... ... Device1 32 Lines 1_LS15 Physical Line15 Physical Line16 C D 2_LS15 ... ... Device2 2_LS0 Physical Line31 32 RGBs Figure 8-2. Mode2 Diagram Figure 8-3. Mode3 and Mode4 Diagram Figure 8-4. Mode5 and Mode6 Diagram 16 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Figure 8-5. Mode7 and Mode8 Diagram When two TLC6984 devices are used in stackable mode, if there are unused line switches, these unused line switches must be the last line switches of the first or the second device. For example, if there are only 30 scanning lines, and if, SCAN_REV = '0'b, the unused line switches can be either of below, • 1_LS14, 1_LS15 • 2_LS14, 2_LS15 SCAN_REV = '1'b, the unused line switches can be either of below, • 1_LS14, 1_LS15 • 2_LS1, 2_LS0 If the unused line switches are 1_LS14, 1_LS15, the FC6-FC13 registers must be configured. If the unused line switches are 2_LS14, 2_LS15 when SCAN_REV = '0' or 2_LS1, 2_LS0 when SCAN_REV = '1', there is no need to configure FC6-FC13 registers. 8.3.2 Current Setting 8.3.2.1 Brightness Control (BC) Function The TLC6984 device is able to adjust the output current of all constant-current outputs simultaneously. This function is called global brightness control (BC). The global BC for all outputs is programmed with a 3-bit register, thus all output currents can be adjusted in 8 steps for a given current-programming resistor, RIREF. When the 3-bit BC register changes, the gain of output current, GAINBC changes as Table 8-2 below. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 17 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Table 8-2. Current Gain Versus BC Code BC Register (BC) Current Gain (GAINBC) 000b 24.17 001b 30.57 010b 49.49 011b (default) 86.61 100b 103.94 101b 129.92 110b 148.48 111b 173.23 The maximum output current per channel, IOUTSET, is determined by resistor R IREF, and the GAINBC. The voltage on IREF is typically 0.8 V. Use Equation 1 to calculate RIREF. For noise immunity purpose, suggest RIREF < 40 kΩ. 4+4'( (G×) = 8+4'( (8) 8+4'( (8) = × )#+0($%) ++4'( (I#) +1765'6 (I#) (1) 8.3.2.2 Color Brightness Control (CC) Function The TLC6984 device is able to adjust the output current of each of the three color groups R0-R15, G0-G15, and B0-B15 separately. This function is called color brightness control (CC). For each color, it has 8-bit data register, CC_R, CC_G, or CC_B. Thus, all color group output currents can be adjusted in 256 steps from 0% to 100% of the maximum output current, IOUTSET. Use Equation 2 to calculate the output current of each color, IOUT_R (or G or B). +176 _4(KN ) KN $) = +1765'6 × 1 + %%_4(KN %%_) KN %%_$) 256 (2) Table Table 8-3 shows the CC data versus the constant-current against IOUTSET. Table 8-3. CC Data vs Current Ratio CC Register (CC_R or CC_G or CC_B) Ratio of IOUTSET 0000 0000b 1/256 0.39% 0000 0001b 2/256 0.78% ... ... ... 0111 1111b (default) 128/256 50% ... ... ... 1111 1110b 255/256 99.61% 1111 1111b 256/256 100% 8.3.2.3 Choosing BC/CC for a Different Application BC is mainly used for global brightness adjustment to adapt to ambient brightness, such as between day and night, indoor and outdoor. • Suggested BC is 3h or 4h, which is in the middle of the range, allowing flexible changes in brightness up and down. • If the current of one color group (usually R LEDs) is close to the output maximum current (10 mA or 20 mA), to prevent the constant output current from exceeding the upper limit in case a larger BC code is input accidentally, choose the maximum BC value, 7h. 18 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 TLC6984 www.ti.com • SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 If the current of one color group (usually B LEDs) is close to the output minimum current (0.2 mA), to prevent the constant output current from exceeding the lower limit in case a lower BC code is input accidentally, choose the minimum BC code, 0h. CC can be used to fine tune the brightness in 256 steps. This action is suitable for white balance adjustment between RGB color group. To get a pure white color, the general requirement for the luminous intensity ratio of R, G, B LED is 5:3:2. Depending on the characteristics of the LED (Electro-Optical conversion efficiency), the current ratio of R, G, B LED is much different from this ratio. Usually, the Red LED needs the largest current. Choose 255d (the maximum value) CC code for the color group that needs the largest initial current, then choose proper CC code for the other two color groups according to the current ratio requirement of the LED used. 8.3.3 Frequency Multiplier The TLC6984 has an internal frequency multiplier to generate the GCLK by SCLK. The GCLK frequency can be configured by FREQ_MOD (See FC0 for more details) and FREQ_MUL (see FC0 for more details ) from 40 MHz to 160 MHz. As Figure 8-6 shows, if the GCLK frequency is not higher than 80 MHz, the GCLK_MOD is set to 0 to disable the bypass switch (enable the ½ divider), while the GCLK frequency is higher than 80 MHz, the GCLK_MOD is set to 1 to enable the bypass switch (disable the ½ divider). GCLK_MUL SCLK GCLK_MOD 1/2 GCLK Figure 8-6. Frequency Multiplier Block Diagram 8.3.4 Line Transitioning Sequence The TLC6984 defines a timing sequence of scan line transition, shown as Figure 8-7. T_SW is the total transitioning time. T_SW is broken up into four intervals: T0 is the time interval between the end of PWM time in current segment and the beginning of channel pre-discharge, T1 is the time interval between the beginning of the channel pre-discharge and the beginning of current line OFF, T2 is the time interval that the beginning of current line OFF and the beginning of next line ON, T3 is the time interval of the beginning of next line ON and the beginning of PWM time in next segment. Figure 8-7. Line Transitioning Sequence The line switch time T_SW equals to T0 + T1 + T2 + T3. T_SW can be configured by the LINE_SWT (see FC1 register bit 40-37 in FC1). Table 8-4 is the relation between LINE_SWT bits and the line switch time (GCLK numbers) with different internal GCLK frequency. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 19 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Table 8-4. Line Switch Time LINE_SW T GCLK Numbers T_SW (us, 40MHZ GCLK) T_SW (us, 60-MHZ GCLK) T_SW (us, 100-MHZ T_SW (us, 120-MHZ GCLK) GCLK) T_SW (us, 160MHZ GCLK) 0000b 45 1.125 0.7515 0.45 0.3735 0.2835 0001b 60 1.5 1.002 0.6 0.498 0.378 0010b 90 2.25 1.503 0.9 0.747 0.567 0011b 120 3 2.004 1.2 0.996 0.756 0100b 150 3.75 2.505 1.5 1.245 0.945 0101b 180 4.5 3.006 1.8 1.494 1.134 0110b 210 5.25 3.507 2.1 1.743 1.323 0111b 240 6 4.008 2.4 1.992 1.512 1000b 270 6.75 4.509 2.7 2.241 1.701 1001b 300 7.5 5.01 3 2.49 1.89 1010b 330 8.25 5.511 3.3 2.739 2.079 1011b 360 9 6.012 3.6 2.988 2.268 1100b 390 9.75 6.513 3.9 3.237 2.457 1101b 420 10.5 7.014 4.2 3.486 2.646 1110b 450 11.25 7.515 4.5 3.735 2.835 1111b 480 12 8.016 4.8 3.984 3.024 8.3.5 Protections and Diagnostics 8.3.5.1 Thermal Shutdown Protection The thermal shutdown (TSD) function turns off all IC constant-current outputs when the junction temperature (TJ) exceeds 170°C (typical). The function resumes normal operation when TJ falls below 155°C (typical). 8.3.5.2 IREF Resistor Short Protection The IREF resistor short protection (ISP) function prevents unwanted large currents from flowing through the constant-current output when the IREF resistor is shorted accidently. The TLC6984 device turns off all output channels when the IREF pin voltage is lower than 0.19 V (typical). When the IREF pin voltage goes higher than 0.325 V (typical), the TLC6984 device resumes normal operation. 8.3.5.3 LED Open Load Detection and Removal 8.3.5.3.1 LED Open Detection The LED open detection (LOD) function detects faults caused by an open circuit in any LED, or a short from OUTn to VLED with low impedance. This function was realized by comparing the OUTn voltage to the LOD detection threshold voltage level set by LODVTH_R/LODVTH_G/LODVTH_B (See FC3 for more details). If the OUTn voltage is higher than the programmed voltage, the corresponding output LOD bit is set to 1 to indicate an open LED. Otherwise, the output of that LOD bit is 0. LOD data output by the detection circuit are valid only during the OUTn turning on period. Figure 8-8 shows the equivalent circuit of LED open detection. 20 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Figure 8-8. LED Open Detection Circuit The LED open detection function records the position of the open LED, which contains the scan line number and relevant channel number. The scan line order is stored LOD_LINE_WARN register (see FC16, FC17 for more details), and the channel number is latched into the internal 48-bit LOD data register (see FC20 for more details) at the end of each segment. Figure 8-9 shows the bit arrangement of the LOD data register. Figure 8-9. Bit Arrangement in LOD Data Register 8.3.5.3.2 Read LED Open Information The LOD readback function must be enabled before read LED open information. This function is enabled by LOD_LSD_RB (see FC3 for more details). Figure 8-10 shows the steps to read LED open information. Wait at least one sub-period time between Step2 and Step3 command. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 21 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Figure 8-10. Steps to Read LED Open Information 8.3.5.3.3 LED Open Caterpillar Removal Figure 8-11 shows the caterpillar issue caused by open LED. Suppose the LED0-1 is an open LED. When line0 is chosen and the OUT1 is turned on, the OUT1 voltage is forced to approach to VLED because of the broken path of the current source. However, the voltage of the un-chosen lines are below the Vclamp which is much lower than VLED, causing all LEDs which connect to the channel OUT1, light unwanted. 22 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Figure 8-11. LED Open Caterpillar The TLC6984 implements circuits that can eliminate the caterpillar issue caused by open LEDs. The LED open caterpillar removal function is configured by LOD_RM_EN (see FC0 for more details). When LOD_RM_EN is set to 1b, the caterpillar removal function is enabled. The corresponding channel OUTn is turned off when scanning to line with open LED, The caterpillar issue is eliminated until device resets or LOD_RM_EN is set to 0b. The internal caterpillar elimination circuit can handle a maximum of three lines that have open LEDs fault condition. If there are open LEDs located in three or fewer lines, the TLC6984 is able to handle the open LEDs all in these lines. If there are open LEDs in more than three lines, the caterpillar issue is solved for the lines where the first three open LEDs were detected, but the open LEDs in the fourth and subsequent lines still cause the caterpillar issue. 8.3.5.4 LED Short and Weak Short Circuitry Detection and Removal 8.3.5.4.1 LED Short and Weak Short Detection The LED short detection (LSD) function detects faults caused by a short circuit in any LED. This function was realized by comparing the OUTn voltage to the LSD threshold voltage. If the OUTn voltage is lower than the Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 23 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 threshold voltage, the corresponding output LSD bit is set to 1 to indicate an short LED, otherwise, the output of that LSD bit is 0. LSD data output by the detection circuit are valid only during the OUTn turning on period. LSD weak short can be detected by adjusting threshold voltage, which level is set by LSDVTH_R/LSDVTH_G/ LSDVTH_B (See FC3 for more details). Figure 8-12 shows the equivalent circuit of LED short detection. Figure 8-12. LED Short Detection Circuit The LED short detection function records the position of the short LED, which contains the scan line order and relevant channel number. The scan line order is stored LSD_LINE_WARN register (see FC18 and FC19 for more details), and the channel number is latched into the internal 48-bit LSD data register (see FC21 for more details) at the end of each segment. Figure 8-13 shows the bit arrangement of the LSD data register. Figure 8-13. Bit Arrangement in the LSD Data Register 8.3.5.4.2 Read LED Short Information The LSD readback function must be enabled before reading LED Short information. This function is enabled by LOD_LSD_RB (see FC3 for more details). 24 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Figure 8-14 shows the steps to read LED Short information. Wait at least one sub-period time between Step2 and Step3 command. Figure 8-14. Steps to Read LED Short Information 8.3.5.4.3 LSD Caterpillar Removal Figure 8-15 shows the LSD caterpillar issue caused by short LED. Suppose the LED0-1 is a short LED. When it scans to the line1 and the OUT1 is turned off, the OUT1 voltage is the same with scan line0 voltage because of the short path of the LED0-1. At this time, there is a current path from the line0 to the GND through the LED1-1 and SW1-1, which causes LED1-1 light unwanted. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 25 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Figure 8-15. LED Short Caterpillar The TLC6984 device implements internal circuits that can eliminate the caterpillar issue by short LEDs. As is shown in Figure 8-15, the LED short caterpillar is caused by the voltage of the Vclamp on the line. So it can be solved by adjusting the LSD_RM_EN (see FC3 for more details) to let the voltage drop of the LED1-1 be smaller than LED forward voltage. 8.4 Device Functional Modes The device functional modes are shown in Figure 8-16. 26 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Figure 8-16. Functional Modes • • • • • Initialization: the device enters into Initialization when Vcc goes down to UVLO voltage. In this mode, all the registers are reset. Entry can also be from any state. Normal: the device enters the normal mode when Vcc is higher than UVLO threshold. The display process is shown as below in normal mode. Power saving: the device automatically enters and gets out from the power save mode when it detects the condition PSin and PSout. In this mode, all channels turn off. PSin: after the device detects that the display data of the next frame all equal to zero, it enters to power save mode when the VSYNC comes. PSout: after the device detects that there is non-zero display data of the next frame, it gets out from power save mode immediately. IREF Resistor Short Protection: the device automatically enters and gets out from the IREF resistor short protection mode when it detects the condition ISPin and ISPout. In this mode, all channels turn off. ISPin: the device detects that the reference voltage is smaller than 0.195 V ISPout: the device detects that the reference voltage is larger than 0.325 V. Thermal Shutdown: the device automatically enters and gets out from the thermal shutdown mode when it detects the condition TSDin and TSDout. In this mode, all channels turn off. TSDin: the device detects that the junction temperature exceeds 170° C TSDout: the device detects that the junction temperature is below 155° C. 8.5 Continuous Clock Series Interface The continuous clock series interface (CCSI) provides access to the programmable functions and registers, SRAM data of the device. The interface contains two input digital pins. the pins are the serial data input (SIN) and serial clock (SCLK). Moreover, there is an another wire called serial data output (SOUT) as the output digital signal of the device. The SIN is set to HIGH when device is in idle status and the SCLK must be existent and continuous all the time considering as the clock source of internal Frequency Multiplier, the SOUT is used to transmit the data or read the data of internal registers. This protocol can support up to 32 devices cascaded in a data chain. The devices receive the chip index command after power up. The chip index command configures addresses of the devices from 0x00 up to 0x1F according to the sequence that receives the command. Then the controller can communicate with all the devices through the broadcast way or particular device through non-broadcast way. The broadcast is mainly used to transmit function control commands. All the devices in a data chain receive the same data in this way. The non-broadcast is mainly used to transmit function control commands or display data, and each device receives its own data in this way. These two ways are distinguished by the command identification. Dual-edge is designed to support more devices cascaded in a data chain. 8.5.1 Data Validity The data on DIN wire must be stable at rising and falling edges of the SCLK in dual-edge transmission. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 27 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 8.5.2 CCSI Frame Format Figure 8-17 defines the format of the command and data transimission. There are four states in one frame. • IDLE: SCLK is always existent and continuous, and DIN is always HIGH. • START: DIN changes from HIGH to LOW after the IDLE states. • DATA: – Head_bytes: command identifier that contains one 16-bit data and one check bit. It can be WRITE COMMAND ID or READ COMMAND ID (see Register Maps for more details). – Data_bytes_N: The Nth data-bytes, contains 3 × 17-bit data, each 17-bit data contains one 16-bit data and one check bit. N is the number of devices cascaded in a data chain. • END: the device recognizes continuous 18-bit HIGH on DIN, then returns to IDLE state. • CHECK BIT: the check bit (17th bit) value is the NOT of 16th bit value, to avoid continuous 18-bit HIGH (to distinguish with END). SCLK SIN Head_bytes Y... Data_bytes_N IDLE START Data_bytes_1 End_bytes DATA END IDLE Figure 8-17. CCSI Frame The IDLE state is not the necessary, that means the START state of next frame can connect to the END state of current frame. 8.5.3 Write Command Take m devices cascaded in a data chain for example. 8.5.3.1 Chip Index Write Command The chip index is used to set the identification of the device cascaded in a data chain. When the first device receives the chip index command Head_bytes1, it sets the current address to 00h and meanwhile change the chip index command Head_bytes2, then sends to the next device. When the device receives the Head_bytes2, it sets the address to 01h and meanwhile changes the chip index command Head_bytes3, then sends to the next device, likewise, all the cascaded devices get their unique identifications. SOUT Controller SCLK SIN Device_1 ST Device_... Head_bytes1 Device_m END ST Head_bytes... END ST Head_bytesm END Figure 8-18. Chip Index Write Command 8.5.3.2 VSYNC Write Command The VSYNC is used to sync the display of each frame for the devices in a cascaded chain. The VSYNC is a write-only command. The devices receive VSYNC command one time from the controller in each frame, and the VSYNC command must be active for all devices at the same time. 28 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Because some devices receive the command earlier in the data chain, they must wait until the last device receives the command, then all the devices are active at that time. To realize such function, each device must know its delay time from receiving VSYNC command to enabling VSYNC. The device uses some register bits to restore the device number in a data chain. This number minuses the device identification, and the result is the delay time of the device. Because the sync function has been done by the device, the controller must only send the VSYNC command to the first device in a data chain. SOUT Controller SCLK SIN Device_1 ST Device_... Head_bytes Device_m END ST Head_bytes END ST END Head_bytes ST Head_bytes END Figure 8-19. VSYNC Write Command 8.5.3.3 MPSM Write Command The MPSM command is used to control the intelligent power save mode of devices in the same matrix. The device detects all zero data in a stackable module and receives MPSM command in current frame, then when VSYNC command comes, all devices in the same matrix turn off. After the device detects that there is non-zero display data of the next frame, it gets out from intelligent power save mode until MSPM command comes in current frame. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 29 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Figure 8-20. Design Procedure for MPSM Command 8.5.3.4 Standby Clear and Enable Command Standby clear command and standby enable command are used to control intelligent power save mode of devices in the same daisy chain. When the device receives standby enable command, it enters to intelligent power save mode right away and does not have to wait for other devices in a module or daisy chain. After the device receives standby enable command, it exits from intelligent power save mode immediately and does not wait for other devices in a module or daisy chain. 8.5.3.5 Soft_Reset Command The Soft_Reset Command is used to reset all the function registers to the default value, except for SRAM data. The format of this command is the same with VSYNC shown as VYSNC Write Command. The difference is the headbytes. 30 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 8.5.3.6 Data Write Command The device can receive the function control with broadcast and non-broadcast way, which depends on the configuration of the devices. If the cascaded devices have the same configuration, broadcast is used, if the cascaded devices have the different configurations, non-broadcast is used. The MSB is always transmitted first and the LSB transmitted last. For 48-bits RGB data, the Blue data must be transmitted first, then the Green, and last the Red data. For broadcast, the devices receive the same data. When devices recognize the broadcast command, they copy the data to the internal registers. Generally, broadcast is used for write FC0-FC13 command, LOD/LSD. Figure 8-21. Data Write Command with Broadcast Figure 8-22 shows the time diagram of the data write command with broadcast. SCLK 1 2 HB15 HB14 3 15 16 17 18 19 20 32 33 34 35 36 37 48 49 50 51 52 53 66 67 68 69 70 71 85 86 SIN HB0 CHECK B15 B14 B0 CHECK G15 G14 G0 CHECK R15 R14 B0 CHECK R0 CHECK SOUT HB15 HB14 HB0 CHECK B15 B14 G15 G14 G0 CHECK R15 R14 R0 CHECK Figure 8-22. Data Write Command with Broadcast (Timing Diagram) For non-broadcast, the devices receive the different data, the controller prepares the data as the figure shows. One pixel data is written to the corresponding device in each command. When the first device receives the END, it cuts off the last 51-bit (3 × 17 bit) data before the END, and the left are shifted out from SDO to the second device. Similarly, when the second device receives the END bytes from the former device, it cuts off the last 51-bit (3×17 bit) data before the END, and the left are shifted out to the next device. Generally, non-broadcast is used for write SRAM command (WRTGS), Details for how to write a frame data into memory bank can be found in Write a Frame Data into Memory Book. Figure 8-23. Data Write Command with Non-Broadcast Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 31 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Figure 8-24 shows the time diagram of the data write command with non-broadcast. SCLK 1 2 HB15 HB14 3 15 16 17 18 19 20 32 33 34 35 36 37 48 49 50 51 52 53 66 67 68 69 70 71 83 84 85 86 87 88 100 101 102 103 104 105 117 118 119 120 121 122 123 124 137 SIN HB0 CHECK 2B15 2B14 2B0 CHECK 2G15 2G14 2G0 CHECK 2R15 2R14 2R0 CHECK 1B15 1B14 1B0 CHECK 1G15 1G14 1G0 CHECK 1R15 1R14 1R0 CHECK SOUT HB15 HB14 HB0 CHECK 2B15 2B14 2B0 CHECK 2G15 2G14 2G0 CHECK 2R15 2R14 2R0 CHECK Figure 8-24. Data Write Command with Non-Broadcast (Timing Diagram) 8.5.4 Read Command The controller sends the read command. When the first device receives this command, it inserts its 48-bit data before End_bytes, and meanwhile shifts out to the second device. When the second device receives this command, it inserts its 48-bit data before End_bytes and meanwhile shifts out to the third device. The data of all the device shifts out from the last device SOUT with this flow. It is always the MSB transmitted first and the LSB transmitted last. Figure 8-25. Data Read Command 32 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 8.6 PWM Grayscale Control 8.6.1 Grayscale Data Storage and Display 8.6.1.1 Memory Structure Overview The TLC6984 implements a display memory unit to achieve high refresh rate and high contrast ratio in an LED display products. The internal display memory unit is divided into two BANKs: BANK A and BANK B. During the normal operation, one BANK is selected to display the data of current frame, another is used to restore the data of next frame. The BANK switcher is controlled by the BANK_SEL bit, which is an internal flag register bit. After power on, BANK_SEL is initialized to 0, and BANK A is selected to restore the data of next frame. Meanwhile, the data in BANK B is read out for display. When one frame has elapsed, the controller sends the vertical synchronization (VSYNC) command to start the next frame, the BANK_SEL bit value is toggled and the selection of the two BANKs reverses. Repeat this operation until all the frame images are displayed. With this method, the TLC6984 device can display the current frame image at a very high refresh rate. See Figure 8-26 for more details about the BANK-selection exchange operation. Figure 8-26. Bank Selection Exchange Operation 8.6.1.2 Details of Memory Bank Each memory BANK contains the frame-image grayscale data of all the 64 lines. Each line comprises 16 48-bit-width memory units. Each memory unit contains the grayscale data of the corresponding R/G/B channels. Depending on the number of scan lines set in SCAN_NUM (FC0 bit 21 to bit 16), the total number of memory units that must be written in one BANK is: 48 × the number of scan lines. For example, if the number of scan lines is set to 64, then 3072 (64 × 48 = 3072) memory units must be written during each frame period. Figure 8-27 shows the detailed memory structure of the TLC6984 device. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 33 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Figure 8-27. TLC6984 Memory-unit Structure 8.6.1.3 Write a Frame Data into Memory Bank After power on, the TLC6984 internal flag BANK_SEL, and counters LINE_COUNT, CHANNEL_COUNT, are all initialized to 0. Thus, the memory unit of channel R0/G0/B0, locating in line 0 of BANK A, is selected to restore the data transimitted the first time after VSYNC command. When the first WRTGS command is received, all the data in the common shift register is latched into the memory unit of channel R0/G0/B0, locating in line 0 of BANK A. Then CHANNEL_COUNT increases by 1 and LINE_COUNT stays the same. Thus, the memory unit of channel R1/G1/B1, locating in line 0 of BANK A, is selected to restore the data transimitted the second time after VSYNC command. When the second WRTGS command is received, all the data in the common shift register is latched into the memory unit of channel R1/G1/B1, locating in line 0 of BANK A. Then CHANNEL_COUNT increases by 1 and LINE_COUNT stays the same. Thus, the memory unit of channel R2/G2/B2, locating in line 0 of BANK A, is selected to restore the data transimitted the third time after VSYNC command. Repeat the grayscale-data-write operation until the 16th WRTGS command is received. Then CHANNEL_COUNT is reset to 0 and LINE_COUNT increases by 1. Thus, the memory unit of channel R0/G0/B0, locating in line 1 of BANK A, is selected to restore the data transimitted the 17th time after VSYNC command. 34 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Repeat this operation for each line until the LINE_COUNT exceeds the number of scan lines set in the SCAN_NUM (See FC0 register bit21-16 ) and all scan lines have been updated with new GS data, which means one frame of GS data is restored into the memory BANK. Then the LINE_COUNT is reset to 0. 8.6.2 PWM Control for Display To increase the refresh rate in time-multiplexing display system, an DS-PWM (Dynamic Spectrum- Pulse Width Modulation) algorithm is proposed in this device. One frame is divided into many segments shown as below. Note that one frame is divided into n sub-periods, n is set by SUBP_NUM (FC0 register bit24-22), and each sub-period is divided into 32 segments for 32 scan lines. Each segment contains GS GCLKs time for grayscale data display and T_SW GCLKs time for switching lines. GS is configured by the SEG_LENGTH (FC1 register bit9-0 in Table 8-8) , and T_SW is the line switch time, which is configured by the LINE_SWT (see FC1 register bit 40-37 in Table 8-8). Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 35 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Frame (display period) Sub-period SP0 SP1 SPn-1 Segment SP0_L0 SP0_L1 SP0_L31 SP1_L0 SP1_L1 SP1_L31 Grayscale data display (GS × GCLK) SPn-1_L0 SPn-1_L1 SPn-1_L31 Line switch (T_SW × GCLK) Note that, SP0: Sub-period 0, L0: Scan line 0 Figure 8-28. DS-PWM Algorithm with 32 Scan Lines The DS-PWM can not only increase the refresh rate meanwhile keep the same frame rate, but also decrease the brightness loss in low grayscale, which can smoothly increase the sub-period number when the grayscale data increases. To achieve ultra-low luminance, the LED driver must have the ability to output a very short current pulse (1 GCLK time). However, because of the parasitic capacitor of the LEDs, such pulse can not turn on the LEDs. And the larger GCLK frequency is, the harder to turn on LEDs. The DS-PWM algorithm has a parameter called sub-period threshold, which is used to calculate when to change sub-period number according to the giving grayscale data. Sub-period threshold defines the LED minimum turn-on time, so as to conquer the current loss caused by LED parasitic capacitor. Sub-period threshold is configured by the SUBP_TH_R/G/B (FC1 register bit24-10 in Table 8-8). With DS-PWM algorithm, the brightness has smoothly increased with the gradient grayscale data. 8.7 Register Maps Table 8-5. Register Maps 36 REGISTER NAME TYPE WRITE COMMAND ID READ COMMAND ID DESCRIPTION FC0 R/ W AA00h AA60h Common configuration FC1 R/ W AA01h AA61h Common configuration FC2 R/ W AA02h AA62h Common configuration FC3 R/ W AA03h AA63h Common configuration FC4 R/ W AA04h AA64h Common configuration FC14 R/ W AA0Eh AA6Eh Locate the line for LOD FC15 R/ W AA0Fh AA6Fh Locate the line for LSD FC16 R AAA0h Read the lines' warning of LOD from 64th ~ 49th line FC17 R AAA1h Read the lines' warning of LOD from 48th~1st line FC18 R AAA2h Read the lines' warning of LSD from 64th ~ 49th line FC19 R AAA3h Read the lines' warning of LSD from 48th~1st line FC20 R AAA4h Read the channel's warning of LOD Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Table 8-5. Register Maps (continued) REGISTER NAME WRITE COMMAND ID TYPE READ COMMAND ID DESCRIPTION AAA5h Read the channel's warning of LSD AA70h Read/Write chip index FC21 R Chip Index R/ W AA10h VSYNC W AAF0h Write VSYNC command MPSM W AA90h Write matrix PSM command SBY_CLR W AAB0h Write standby clear command SBY_EN W AAB1h Write standby enable command Soft_Reset W AA80h Reset the all the registers expect the SRAM SRAM W AA30h Write or read the SRAM data Table 8-6. Access Type Codes Access Type Code Description R Read W Write Read Type R Write Type W Reset or Default Value -n Value after reset or the default value 8.7.1 FC0 FC0 is shown in Figure 8-29 and described in Table 8-7. Figure 8-29. FC0 Register 47 46 45 44 43 42 41 40 39 38 37 LSD_R M_EN RESERVED GRP_DLY_B GRP_DLY_G GRP_DLY_R R/ W-0b R/W-01b R/W-000b R/W-000b R/W-000b 31 30 29 28 27 26 25 24 23 22 21 36 35 34 R/ W-0b 20 19 18 FREQ_ MOD RESERVED SUBP_NUM SCAN_NUM R/W-0111b R/ W-0b R/W-000b R/W-000b R/W-000000b 14 13 12 LODR M_EN PSP_MOD PS_EN R/ W-0b R/W-00b R/ W-0b 11 10 9 RESERVED R/ W-0b R/ W-0b 8 PDC_E N R/ W-0b R/ W-1b 7 6 5 RESERVED R/ W-0b R/ W-0b R/ W-0b 32 R/W-00b FREQ_MUL 15 33 RESERVED 4 3 2 17 16 1 0 CHIP_NUM R/W-00111b Table 8-7. FC0 Register Field Descriptions Bit Field Type Reset Description 4-0 CHIP_NUM R/W 00111b Set the device number 00000b: 1 device ... 01111b: 16 devices ... 11111b: 32 devices 7-5 RESERVED R/W 000b PDC_EN R/W 1b 8 Enable or disable pre-discharge function 0b: disable 1b: enable Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 37 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Table 8-7. FC0 Register Field Descriptions (continued) Bit Field Type Reset 11-9 RESERVED R/W 000b PS_EN R/W 0b Enable or disable the power saving mode 0b: disable 1b: enable PSP_MOD R/W 00b Set the powering saving plus mode 00b: disable 01b: enable, when GSn(including the extending) ≤ 1/4 segment_length, power saving during the off cycle. 10b: enable, when GSn(including the extending) ≤ 1/2 segment_length, power saving during the off cycle. 11b: enable, when GSn(including the extending) ≤ 7/8 segment_length, power saving during the off cycle. 15 LODRM_EN R/W 0b Enable or disable the LED open load removal function 0b: disable 1b: enable 21-16 SCAN_NUM R/W 000000b Set the scan line number 000000b: 1 line ... 001111b: 16 lines ... 011111b: 32 lines ... 111111b: 64 lines 24-22 SUBP_NUM R/W 000b Set the subperiod number 000b: 16 001b: 32 010b: 48 011b: 64 100b: 80 101b: 96 110b: 112 111b: 128 27-25 RESERVED R/W 000b 28 FREQ_MOD R/W 0b Set the GCLK multiplier mode 0b: high frequency mode, 80MHz to 160MHz 1b:low frequency mode, 40MHz to 80MHz 32-29 FREQ_MUL R/W 0111b Set the GCLK multiplier frequency 0000b: 1 x SCLK frequency ... 0111b: 8 x SCLK frequency ... 1111b: 16 x SCLK frequency 35-33 LINE_CHRG R/W 000b 38-36 GRP_DLY_R R/W 000b Set the Red group delay, forward PWM mode only 000b: no delay 001b: 1 GCLK 010b: 2 GCLK 011b: 3 GCLK 100b: 4 GCLK 101b: 5 GCLK 110b: 6 GCLK 111b: 7 GCLK 41-39 GRP_DLY_G R/W 000b Set the Green group delay, forward PWM mode only 000b: no delay 001b: 1 GCLK 010b: 2 GCLK 011b: 3 GCLK 100b: 4 GCLK 101b: 5 GCLK 110b: 6 GCLK 111b: 7 GCLK 12 14-13 38 Description Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Table 8-7. FC0 Register Field Descriptions (continued) Bit Field Type Reset Description 44-42 GRP_DLY_B R/W 000b Set the Blue group delay, forward PWM mode only 000b: no delay 001b: 1 GCLK 010b: 2 GCLK 011b: 3 GCLK 100b: 4 GCLK 101b: 5 GCLK 110b: 6 GCLK 111b: 7 GCLK 46-45 RESERVED R/W 01b 47 LSD_RM_EN R/W 0b Enable or disable short LED caterpillar 0b: disable 1b: enable Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 39 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 8.7.2 FC1 FC1 is shown in Figure 8-30 and described in Table 8-8. Figure 8-30. FC1 Register 47 46 45 44 RESE RVED 43 42 41 40 BLK_ADJ R-0b 30 29 28 27 38 37 36 LINE_SWT R/W-000000b 31 39 R/W-0111b 26 25 24 23 35 34 33 LG_ENH_B R/W-0000b 22 21 20 19 18 17 LG_ENH_G LG_ENH_R LG_STEP_B LG_STEP_G R/W-0000b R/W-0000b R/W-01001b R/W-01001b 15 14 LG_ST EP_G 13 12 11 10 9 8 7 32 LG_EN H_G 6 5 4 LG_STEP_R SEG_LENGTH R/W-01001b R/W-0'000'000'000b 3 2 1 16 0 Table 8-8. FC1 Register Field Descriptions 40 Bit Field Type Reset Description 9-0 SEG_LENGTH R/W 0'000'000'0 Set the GCLK number in each segment 00b 127d: 128 GCLK ... 1023d: 1024 GCLK others: 128 GCLK 14-10 LG_ENH_B R/W 01001b Adjust the smooth of the brightness in low grayscale 00000b: level 1 ... 01111b: level 16 ... 11111b: level 32 19-15 LG_ENH_G R/W 01001b Adjust the smooth of the brightness in low grayscale 00000b: level 1 ... 01111b: level 16 ... 11111b: level 32 24-20 LG_ENH_B R/W 01001b Adjust the smooth of the brightness in low grayscale 00000b: level 1 ... 01111b: level 16 ... 11111b: level 32 28-25 LG_STEP_R R/W 0000b Adjust low grayscale enhancement of red channels 0000b: level 0 ... 0111b: level 7 ... 1111b: level 15 32-29 LG_STEP_G R/W 0000b Adjust low grayscale enhancement of green channels 0000b: level 0 ... 0111b: level 7 ... 1111b: level 15 36-33 LG_STEP_B R/W 0000b Adjust low grayscale enhancement of blue channels 0000b: level 0 ... 0111b: level 7 ... 1111b: level 15 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Table 8-8. FC1 Register Field Descriptions (continued) Bit Field Type Reset Description 40-37 LINE_SWT R/W 0111b Set the scan line switch time. 0000b: 45 GCLK 0001b: 2x30 GCLK ... 0111b: 8x30 GCLK ... 1111b: 16x30 GCLK 46-41 BLK_ADJ R/W 000000b Set the black field adjustment 000000b: 0 GCLK ... 011111b: 31 GCLK ... 111111b: 63 GCLK RESERVED R 0b Reserved bit. 47 8.7.3 FC2 FC2 is shown in Figure 8-31 and described in Table 8-9. Figure 8-31. FC2 Register 47 46 MPSM _EN RESE RVED MOD_SIZE R/ W-0b R/ W-0b R/W-111b 31 30 45 44 29 28 43 42 27 13 39 R/ W-0b R/ W-1b R/ W-1b R/ W-1b 26 25 24 23 LG_COLOR_R R/W-0000b 14 40 11 10 9 37 36 35 7 33 LG_COLOR_B R/W-000b R/W-0000b 22 21 20 19 6 5 18 17 32 16 DE_COUPLE1_G R/W-0000b 8 34 RESERVED DE_COUPLE1_B R/W-0000b 12 38 SUBP_ CH_B_ CH_G_ CH_R_ MAX_2 IMMU IMMU IMMU 56 NITY NITY NITY LG_COLOR_G 15 41 R/W-0000b 4 3 2 1 DE_COUPLE1_R V_PDC_B V_PDC_G V_PDC_R R/W-0000b R/W-0110b R/W-0110b R/W-0110b 0 Table 8-9. FC2 Register Field Descriptions Bit Field Type Reset Description 3-0 V_PDC_R R/W 0110b Set the Red pre_discharge voltage (typical), the voltage value must not be higher than (VR-1.3 V). 0000b: 0.1 V 0001b: 0.2 V 0010b: 0.3 V 0011b: 0.4 V 0100b: 0.5 V 0101b: 0.6 V 0110b: 0.7 V 0111b: 0.8 V 1000b: 0.9 V 1001b: 1.0 V 1010b: 1.1 V 1011b: 1.3 V 1100b: 1.5 V 1101b: 1.7 V 1110b: 1.9 V 1111b: 2.1 V Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 41 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Table 8-9. FC2 Register Field Descriptions (continued) 42 Bit Field Type Reset Description 7-4 V_PDC_G R/W 0110b Set the Green pre_discharge voltage (typical), the voltage value must not be higher than (VG-1.3V). 0000b: 0.1 V 0001b: 0.2 V 0010b: 0.3 V 0011b: 0.4 V 0100b: 0.5 V 0101b: 0.6 V 0110b: 0.7 V 0111b: 0.8 V 1000b: 0.9 V 1001b: 1.0 V 1010b: 1.1 V 1011b: 1.3 V 1100b: 1.5 V 1101b: 1.7 V 1110b: 1.9 V 1111b: 2.1 V 11-8 V_PDC_B R/W 0110b Set the Blue pre_discharge voltage (typical), the voltage value must not be higher than (VB-1.3V). 0000b: 0.1V 0001b: 0.2 V 0010b: 0.3 V 0011b: 0.4 V 0100b: 0.5 V 0101b: 0.6 V 0110b: 0.7 V 0111b: 0.8 V 1000b: 0.9 V 1001b: 1.0 V 1010b: 1.1 V 1011b: 1.3 V 1100b: 1.5 V 1101b: 1.7 V 1110b: 1.9 V 1111b: 2.1 V 15-12 DE_COUPLE1_R R/W 0000b Set the Red dummy rising one-shot level 0000b: level 1 (lowest) ... 0111b: level 8 (middle) ... 1111b: level 16(highest) 19-16 DE_COUPLE1_G R/W 0000b Set the Green dummy rising one-shot level 0000b: level 1 (lowest) ... 0111b: level 8 (middle) ... 1111b: level 16(highest) 23-20 DE_COUPLE1_B R/W 0000b Set the Blue dummy rising one-shot level 0000b: level 1 (lowest) ... 0111b: level 8 (middle) ... 1111b: level 16(highest) 27-24 LG_COLOR_R R/W 0000b Set the Red rising one-shot level 0000b: level 1 (lowest) ... 0111b: level 8 (middle) ... 1111b: level 16(highest) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Table 8-9. FC2 Register Field Descriptions (continued) Bit Field Type Reset Description 31-28 LG_COLOR_G R/W 0000b Set the Green rising one-shot level 0000b: level 1 (lowest) ... 0111b: level 8 (middle) ... 1111b: level 16(highest) 35-32 LG_COLOR_B R/W 0000b Set the Blue rising one-shot level 0000b: level 1 (lowest) ... 0111b: level 8 (middle) ... 1111b: level 16(highest) 38-36 RESERVED R/W 000b 39 CH_R_IMMUNITY R/W 1b Set the immunity of the Red channels group 0b: high immunity 1b: low immunity 40 CH_G_IMMUNITY R/W 1b Set the immunity of the Green channels group 0b: high immunity 1b: low immunity 41 CH_B_IMMUNITY R/W 1b Set the immunity of the Blue channels group 0b: high immunity 1b: low immunity 42 SUBP_MAX_256 R/W 0b Set the maximum subperiod to 256. 0b: disable 1b: enable 45-43 MOD_SIZE R/W 111b Set the module size. 000b: 16x16 RGB pixels 001b:32x32 RGB pixels 010b:48x48 RGB pixels with D3 reverse, and scan sequence D1, D2, D3 48x48 RGB pixels with D3 reverse, and scan sequence D1, D3, D2 100b:48x64 RGB pixels with D3, D4 reverse, and scan sequence D1, D2, D3 101b:48x64 RGB pixels with D3,D4 reverse, and scan sequence D1, D3, D2 110b:64x64 RGB pixels with D3, D4 reserve, and scan seqeunce D1, D2, D3, D4 111b:64x64 RGB pixels with D3, D4 reverse,and scan sequence D1, D4, D2, D3 46 RESERVED R/W 0b 47 MPSM_EN R/W 0b Enable or disable matrix power saving mode. 0b: disable 1b: enable 8.7.4 FC3 FC3 is shown in Figure 8-32 and described in Table 8-10. Figure 8-32. FC3 Register 47 46 45 44 LSDVTH_B 15 30 14 42 41 LSDVTH_G R/W-000b 31 43 R/W-000b 29 13 28 27 40 39 38 LSDVTH_R 25 24 36 35 R/W-0111b 23 22 21 19 CC_G R/W-0111 1111b 10 9 8 7 6 5 4 32 R/W-011b 20 CC_B 11 33 BC R/W-0111 1111b 12 34 LSD_RM R/W-000b 26 37 3 18 17 16 2 1 0 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 43 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Figure 8-32. FC3 Register (continued) CC_R LOD_L RESE SD_RB RVED R/W-0111 1111b R/ W-0b R/ W-0b LODVTH_B LODVTH_G LODVTH_R R/W-00b R/W-00b R/W-00b Table 8-10. FC3 Register Field Descriptions 44 Bit Field Type Reset Description 1-0 LODVTH_R R/W 00b Set the Red LED open load detection threshold 00b: (VLEDR-0.2) V 01b: (VLEDR-0.5) V 10b: (VLEDR-0.9) V 11b: (VLEDR-1.2) V 3-2 LODVTH_G R/W 00b Set the Green LED open load detection threshold 00b: (VLEDG-0.2) V 01b: (VLEDG-0.5) V 10b: (VLEDG-0.9) V 11b: (VLEDG-1.2) V 5-4 LODVTH_B R/W 00b Set the Blue LED open load detection threshold 00b: (VLEDB-0.2) V 01b: (VLEDB-0.5) V 10b: (VLEDB-0.9) V 11b: (VLEDB-1.2) V 6 RESERVED R/W 0b 7 LOD_LSD_RB R/W 0b 15-8 CC_R R/W 0111 1111b Set the Red color brightness level 0000 0000b: level 0 (lowest) ... 0111 1111b: level 127 (middle) ... 1111 1111b: level 255 (highest) 23-16 CC_G R/W 0111 1111b Set the Green color brightness level 0000 0000b: level 0 (lowest) ... 0111 1111b: level 127 (middle) ... 1111 1111b: level 255 (highest) 31-24 CC_B R/W 0111 1111b Set the Blue color brightness level 0000 0000b: level 0 (lowest) ... 0111 1111b: level 127 (middle) ... 1111 1111b: level 255 (highest) 34-32 BC R/W 011b Enable or disable the LOD and LSD readback function 0b: disabled 01b: enabled Set the global brightness level 000b: level 0 (lowest) ... 011b: level 3 (middle) ... 111b: level 7 (highest) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Table 8-10. FC3 Register Field Descriptions (continued) Bit Field Type Reset Description 38-35 LSD_RM R/W 0111b Set the LED short removal level 0000b: level 1 0001b: level 2 0010b: level 3 0011b: level 4 0100b: level 5 0101b: level 6 0110b: level 7 0111b: level 8 1000b: level 9 1001b: level 10 1010b: level 11 1011b: level 12 1100b: level 13 1101b: level 14 1110b: level 15 1111b: level 16 41-39 LSDVTH_R R/W 000b Set the Red LED short/weak short circuitry detection threshold (typical) 000b: 0.2 V 001b: 0.4 V 010b: 0.8 V 011b: 1.0 V 100b: 1.2 V 101b: 1.4 V 110b: 1.6 V 111b: 1.8 V 44-42 LSDVTH_G R/W 000b Set the Green LED short/weak short circuitry detection threshold (typical) 000b: 0.2 V 001b: 0.4 V 010b: 0.8 V 011b: 1.2 V 100b: 1.6 V 101b: 2 V 110b: 2.4 V 111b: 2.8 V 47-45 LSDVTH_B R/W 000b Set the Blue LED short/weak short circuitry detection threshold (typical) 000b: 0.2 V 001b: 0.4 V 010b: 0.8 V 011b: 1.2 V 100b: 1.6 V 101b: 2 V 110b: 2.4 V 111b: 2.8 V 8.7.5 FC4 FC4 is shown in Figure 8-33 and described in Table 8-11. Figure 8-33. FC4 Register 47 31 34 33 32 RESERVED 46 DE_C OUPL E3_EN DE_COUPLE3 DE_C OUPL E2 FIRST_LINE_DIM CAUR SE_B CAUR SE_G CAUR SE_R R-000b R/ W-0b R/W-1000b R/ W-0b R/W-0000b R/ W-0b R/ W-0b R/ W-0b 18 17 16 FINE_ G FINE_ R 30 45 29 RESERVED 44 28 43 27 42 26 SR_ON_B 41 25 40 24 SR_ON_G 39 23 38 22 SR_ON_R 37 21 36 20 35 19 SR_OF SR_OF SR_OF FINE_ F_B F_G F_R B Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 45 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Figure 8-33. FC4 Register (continued) R/W-0000b 15 14 13 R/W-01b 12 11 10 RESE SCAN_ RVED REV R/ W-0b R/ W-1b R/W-01b R/W-01b 9 7 8 6 R/ W-0b R/ W-0b R/ W-0b R/ W-0b 5 4 3 2 R/ W-0b R/ W-0b 1 0 RESERVED IMAX LAST_ SOUT R/W-0000 0000 1111b R/ W-0b R/ W-0b Table 8-11. FC4 Register Field Descriptions Bit 46 Field Type Reset Description 0 LAST_SOUT R/W 0b Enable or disable the last device's SOUT cut-off function 0b: disabled, last chip's SOUT shift out 1b: enabled, last chip's SOUT cut off, except for READ command 1 IMAX R/W 0b Set the maximum current of each channel 0b: 10mA maximum 01b: 20 mA maximum 13-2 RESERVED R/W 0000 0000 1111b 14 SCAN_REV R/W 1b 15 RESERVED R/W 0b 16 FINE_R R/W 0b Enable the Red brightness compensation level fine range 0b: disable. 1b: enable. 17 FINE_G R/W 0b Enable the Green brightness compensation level fine range 0b: disable. 1b: enable. 18 FINE_B R/W 0b Enable the Blue brightness compensation level fine range 0b: disable. 1b: enable. 19 SR_OFF_R R/W 0b Slew rate control function when Red turns off operation 0b: slow slew rate. 1b: fast slew rate. 20 SR_OFF_G R/W 0b Slew rate control function when Green turns off operation 0b: slow slew rate. 1b: fast slew rate. 21 SR_OFF_B R/W 0b Slew rate control function when Blue turns off operation 0b: slow slew rate. 1b: fast slew rate. 23-22 SR_ON_R R/W 01b Slew rate control function when Red turns on operation 00b: the slower slew rate. 01b: slow slew rate. 10b: fast slew rate. 11b: the faster slew rate. 25-24 SR_ON_G R/W 01b Slew rate control function when Green turns on operation 00b: the slower slew rate. 01b: slow slew rate. 10b: fast slew rate. 11b: the faster slew rate. 27-26 SR_ON_B R/W 01b Slew rate control function when Blue turns on operation 00b: the slower slew rate. 01b: slow slew rate. 10b: fast slew rate. 11b: the faster slew rate. When 2 device stackable or 3 devices stackable, the scan lines PCB layout is reversed. For the proper scan and SRAM read sequence, SCAN_REV register is provided. 0b: the PCB layout sequence is L0-L15, L16-L31. 1b: the PCB layout sequence is L0-L15, L31-L16. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Table 8-11. FC4 Register Field Descriptions (continued) Bit Field Type Reset 31-28 RESERVED R/W 0000b 32 CAURSE_R R/W 0b Enable the Red brightness compensation level caurse tange 0b: disabled 1b: enabled 33 CAURSE_G R/W 0b Enable the Green brightness compensation level caurse tange 0b: disabled 1b: enabled 34 CAURSE_B R/W 0b Enable the Blue brightness compensation level caurse tange 0b: disabled 1b: enabled FIRST_LINE_DIM R/W 0000b Adjust the first line dim level 0000b: level 1 ... 0111b: level 8 ... 1111b: level 16 39 DE_COUPLE2 R/W 0b Decoupling between ON and OFF channels 0b: disabled 1b: enabled 43-40 DE_COUPLE3 R/W 1000b Set decoupling enhancement level 0000b: level 1 ... 0111b: level 8 ... 1111b: level 16 DE_COUPLE3_EN R/W 0b Enable decoupling enhancement 0b: disabled 1b: enabled RESERVED R/W 000b 38-35 44 47-45 Description 8.7.6 FC14 FC14 is shown in FC14 Register and described in FC14 Register Field Descriptions. Figure 8-34. FC14 Register 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 22 21 20 19 18 17 16 6 5 4 3 2 1 0 RESERVED R-0b 31 30 29 28 27 26 25 24 23 RESERVED R-0b 15 14 13 12 11 10 9 8 7 RESERVED LOD_LINE_CMD R-0b R/W-000000b Table 8-12. FC14 Register Field Descriptions Bit Field Type Reset Description 5-0 LOD_LINE_CMD R/W 000000b Locate the line with LED open load warnings: 000000b: Line 0 ... 011111b: Line 31 ... 111111b: Line 63 47-6 RESERVED R 0b Reserved bits Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 47 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 8.7.7 FC15 FC15 is shown in FC15 Register and described in FC15 Register Field Descriptions. Figure 8-35. FC15 Register 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 22 21 20 19 18 17 16 6 5 4 3 2 1 0 RESERVED R-0b 31 30 29 28 27 26 25 24 23 RESERVED R-0b 15 14 13 12 11 10 9 8 7 RESERVED LSD_LINE_CMD R-0b R/W-000000b Table 8-13. FC15 Register Field Descriptions Bit Field Type Reset Description 5-0 LSD_LINE_CMD R/W 000000b Locate the line with LED short circuitry warnings: 000000b: Line 0 ... 011111b: Line 31 ... 111111b: Line 63 47-6 RESERVED R 0b Reserved bits 8.7.8 FC16 FC16 is shown in FC16 Register and described in FC16 Register Field Descriptions. Figure 8-36. FC16 Register 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 22 21 20 19 18 17 16 6 5 4 3 2 1 0 RESERVED R-0b 31 30 29 28 27 26 25 24 23 RESERVED R-0b 15 14 13 12 11 10 9 8 7 LOD_LINE_WARN[63:48] R-0b Table 8-14. FC16 Register Field Descriptions Bit Field Type Reset Description 15-0 LOD_LINE_WARN[63:48] R 0b Read the line with LED open load warnings: Bit 0 = 0, Line 48 has no warning; Bit 0 = 1, Line 48 has warning ... Bit 15 = 0, Line 63 has no warning; Bit 15 = 1, Line 63 has warning 47-16 RESERVED R 0b Reserved bits 8.7.9 FC17 FC17 is shown in FC17 Register and described in FC17 Register Field Descriptions. Figure 8-37. FC17 Register 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 LOD_LINE_WARN[47:0] 48 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Figure 8-37. FC17 Register (continued) R-0b 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5 4 3 2 1 0 LOD_LINE_WARN[47:0] R-0b 15 14 13 12 11 10 9 8 7 6 LOD_LINE_WARN[47:0] R-0b Table 8-15. FC17 Register Field Descriptions Bit 47-0 Field Type Reset Description LOD_LINE_WARN[47:0] R 0b Read the line with LED open load warnings: Bit 0 = 0, Line 0 has no warning; Bit 0 = 1, Line 0 has warning ... Bit 47 = 0, Line 47 has no warning; Bit 47 = 1, Line 47 has warning 8.7.10 FC18 FC18 is shown in FC18 Register and described in FC18 Register Field Descriptions. Figure 8-38. FC18 Register 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 22 21 20 19 18 17 16 6 5 4 3 2 1 0 RESERVED R-0b 31 30 29 28 27 26 25 24 23 RESERVED R-0b 15 14 13 12 11 10 9 8 7 LSD_LINE_WARN[63:48] R-0b Table 8-16. FC18 Register Field Descriptions Bit Field Type Reset Description 16-0 LSD_LINE_WARN[63:48] R 0b Read the line with LED short circuitry warnings: Bit 0 = 0, Line 48 has no warning; Bit 0 = 1, Line 48 has warning ... Bit 15 = 0, Line 63 has no warning; Bit 15 = 1, Line 63 has warning 47-16 RESERVED R 0b Reserved bits 8.7.11 FC19 FC19 is shown in FC19 Register and described in FC19 Register Field Descriptions. Figure 8-39. FC19 Register 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 21 20 19 18 17 16 5 4 3 2 1 0 LSD_LINE_WARN[47:0] R-0b 31 30 29 28 27 26 25 24 23 22 LSD_LINE_WARN[47:0] R-0b 15 14 13 12 11 10 9 8 7 6 LSD_LINE_WARN[47:0] Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 49 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Figure 8-39. FC19 Register (continued) R-0b Table 8-17. FC19 Register Field Descriptions Bit 47-0 Field Type Reset Description LSD_LINE_WARN[47:0] R 0b Read the line with LED short circuitry warnings: Bit 0 = 0, Line 0 has no warning; Bit 0 = 1, Line 0 has warning ... Bit 47 = 0, Line 47 has no warning; Bit 47 = 1, Line 47 has warning 8.7.12 FC20 FC20 is shown in FC20 Register and described in FC20 Register Field Descriptions. Figure 8-40. FC20 Register 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 22 21 20 19 18 17 16 6 5 4 3 2 1 0 LOD_CH R-0b 31 30 29 28 27 26 25 24 23 LOD_CH R-0b 15 14 13 12 11 10 9 8 7 LOD_CH R-0b Table 8-18. FC20 Register Field Descriptions Bit 47-0 Field Type Reset Description LOD_CH R 0b Locate the LED opem load channel: Bit 0 = 0, CH 0 is normal; Bit 0 = 1, CH 0 is short circuitry ... Bit 47 = 0, CH 47 is normal; Bit 47 = 1, CH 47 is short circuitry 8.7.13 FC21 FC21 is shown in FC21 Register and described in FC21 Register Field Descriptions. Figure 8-41. FC21 Register 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 22 21 20 19 18 17 16 6 5 4 3 2 1 0 LSD_CH R-0b 31 30 29 28 27 26 25 24 23 LSD_CH R-0b 15 14 13 12 11 10 9 8 7 LSD_CH R-0b Table 8-19. FC21 Register Field Descriptions Bit 47-0 50 Field Type Reset Description LSD_CH R 0b Locate the LED short circuitry channel: Bit 0 = 0, CH 0 is normal; Bit 0 = 1, CH 0 is short circuitry ... Bit 47 = 0, CH 47 is normal; Bit 47 = 1, CH 47 is short circuitry Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality. 9.1 Application Information The TLC6984 integrates 48 constant current sources and 16 scanning FETs. A single TLC6984 is capable of driving 16 × 16 RGB LED pixels while stacking two TLC6984s can drive 32 × 32 RGB LED pixels. To achieve low power consumption, the TLC6984 supports separated power supplies for the red, green, and blue LEDs by its common cathode structure. The TLC6984 implements a high speed dual-edge transmission interface (up to 25 MHz) to support high device count daisy-chained and high refresh rate while minimizing electrical-magnetic interference (EMI). SCLK must be continuous, no matter there are data on SIN or not, because SCLK is not only used to sample the data on SIN, but also used as a clock source to generate GCLK by internal frequency multiplier. Based on dual-edge CCSI protocol, all the commands/FC registers/SRAM data are written from the SIN input terminal, and all the FC registers/ LED open and short flag can be read out from the SOUT output terminal. Moreover, the device supports up to 160-MHz GCLK frequency and can achieve 16-bit PWM resolution, with 3840 Hz or even higher refresh rate. Meanwhile, the TLC6984 integrates enhanced circuits and intelligent algorithms to solve the various display challenges in Narrow Pixel Pitch (NPP) LED display applications and mini and micro-LED products: dim at the first scan line, upper and downside ghosting, non-uniformity in low grayscale, coupling, caterpillar caused by open or short LEDs, which make the TLC6984 a perfect choice in such applications. The TLC6984 also implements LED open and weak, short and short detections and removals during operations and can also report this information out to the accompanying digital processor. 9.2 Typical Application The TLC6984 is typically connected in series in a daisy-chain to drive the LED matrix with only a few controller ports. Figure 9-1 shows a typical application diagram with two TLC6984 devices stackable connection to drive 32 × 32 RGB LED pixels. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 51 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Figure 9-1. TLC6984 With Dual Devices Stackable Connection 9.2.1 Design Requirements Taking 4K micro-LED televation for example, the resolution of the screen is 3840 × 2160, and the screen consists of many modules. The following sections show an example to build a LED display module with 240 × 180 pixels. The example uses the following values as the system design parameters. Table 9-1. TLC6984 Design Parameters DESIGN PARAMETER EXAMPLE VALUE VCC and VR 2.8 V VG and VB 3.8 V Maximum current per LED IRED = 3 mA, IGREEN = 2 mA, IBLUE = 1 mA PWM resolution 14 bits Frame rate 120 Hz Refresh rate 3840 Hz Display module size 240 × 180 pixels cascaded devices number 8 devices number per LED display module 96 9.2.1.1 System Structure To build an LED display module with 240 × 180 pixels, 96 TLC6984s are required. 52 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 240 Colume 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 30 x 30 pixels 180 Lines Figure 9-2. LED Display Module As shown in Figure 9-2, the total module can be divided into 48 32 × 32 matrix. Each matrix includes two devices with stackable connection. Note To achieve the best performance, TI suggests to distribute the redundant channels and lines to each 32 × 32 matrix. For this case, two Red/Green/Blue channels and two lines are not used in each matrix. And these unused pins can be floated. For the software, TI suggests zero data is to send to the unused channels. There is no must send the zero data to unused lines. 9.2.1.2 SCLK Frequency The SCLK frequency is determined by the data volume of one frame and frame rate. In this application, the data volume V_Data is 30 × 32 × 48 bits × 4 = 184.32 Kb, the frame rate is 120 Hz. Suppose the data transmission efficiency is 0.8, the minimum frequency of SCLK must be: fSCLK = V_Data × fframe / 0.8. So the minimum SCLK frequency is 13.83 MHz with dual-edge transmission. 9.2.1.3 Internal GCLK Frequency The internal GCLK frequency is configured by the Frequency Multiplier (FREQ_MUL), and is determined by the PWM resolution. The GCLK frequency can be calculated by the below equations: Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 53 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 f refresh _ rate N sub _ period f frame _ rate GS max 2K GSmax N GCLK _ Seg u N sub _ period 1 f frame _ rate § N GCLK _ Seg ¨ © fGCLK · TSW ¸ u N Scan _ line u N sub _ period ¹ TBlank (3) where • • • • • • • • • • frefresh_rate means the refresh rate fframe_rate means the frame rate K means the PWM resolution Nsub_period means the sub-period numbers within one frame NGCLK_seg means the GCLK number per segment (Line switch time excluded) fGCLK means GCLK frequency TSW means line switching time Nscan_line means the scan line number Tblank means the blank time in one frame, equals to 0 in ideal configuration GSmax means the maximum grayscale that the device can output in one frame Table 9-2 gives the values based on the system configuration and equation. Table 9-2. TLC6984 Design Parameters for GCLK Frequency Calculation DESIGN PARAMETER EXAMPLE VALUE Nsub_period 32 Nscan_line 30 TSW 1.5 µs Tblank 0 NGCLK_seg 512 GSmax 16383 fGCLK 71.3 MHz Considering SCLK frequency and FREQ_MUL, the SCLK can be 13.9 MHz, and FREQ_MUL can be 6. So the GCLK is 83.4 MHz. 9.2.1.4 Line Switch Time The line switch time is digitalized with the GCLK number and can be set by the LINE_SWT (Bit 40-37 in FC1 register). In this application, it is 1.5 us × 83.4 MHz = 125 GCLKs, so the LINE_SWT equals to 0011b (120 GCLKs), the actual line switch time is 1.44 us. 9.2.1.5 Blank Time Removal The TLC6984 has an algorithm to distribute the blank time into each subperiod to prevent the black field when taking photos or video. From Equation 3, 83.4-MHz GCLK frequency and 1.44-us line switch time, the calculated blank time is 1.059 ms ( 88280 GCLK ), which is too long and brings black field. Here are detailed steps of the algorithm. Step 1: Distribute blank time into each segment 54 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 When the blank GCLK number is larger than Nsub_period × Nscan_line, it can be distributed into each segment. In this application, the blank GCLK number is 88280, and Nsub_period × Nscan_line is 960, so the distributed GCLK number in each segment is 88280/960 = 91...920. These 91GCLKs can be used to increase PWM length or extend line switch time. If used to increase PWM length, the GCLK number in each segment is 512 + 91= 603, so the SEG_LENGTH ( Bit9-0 in FC1 register) is 1001011010b. Step 2: Distribute blank time into each sub-period If the left GCLK number is larger than Nsub_period, it can be distributed into each sub-period. In this application, the left GCLK is 697, the distributed GCLK number in each sub-period is 920/32=28...24. The BLK_ADJ (Bit46-41 in FC1 register) is 011100b. After distributing into each sub-period, the left GCLK number is 24, which is about 300 ns, this time is too short to bring black field. 9.2.1.6 BC and CC Select the reference current-setting resistor RIREF and configure a proper BC value to set the maximum current of the RGB LEDs (see Brightness Control (BC) Function for more details). Here the maximum current is 3 mA, BC value is 03h, according to equation Equation 1, the reference resistor value is 0.8 V/3 mA × 85.33 = 22.75 kΩ. Configure the CC_R/CC_G/CC_B registers to set the current of Red/ Green/Blue LED current to 3 mA/2 mA/1 mA (see Color Brightness Control (CC) Function for more details). Table 9-3 shows the reference current setting resistor RIREF, BC and CC_R/CC_G/CC_B register value. Table 9-3. Current Setting Value DESIGN PARAMETER EXAMPLE VALUE RIREF 22.75 kΩ BC 011 b CC_R 11111111 b CC_G 10101001 b CC_B 01010100 b Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 55 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 9.2.2 Detailed Design Procedure Figure 9-3 gives a detail design procedure for LED display. After power on and digital signals are ready, the first step for the controller is to send the chip index command to let the devices know their identifications. Then, the controller sends the configuration data to the FC registers. After this, it sends the VSYNC at the beginning of each frame and also sends the data to each device. The devices display the data of last frame when the VSYNC comes and meanwhile receive the data of current frame transmitted from controller. The registers can be read at anytime of the frame. Begin Power Supply, SCLK/SIN Ready Write Chip Index Configure the register during sending data Write FC Registers Write next frame SRAM Data in normal operation Write SRAM Wait for the end of current frame Write VSYNC Read Chip Index/FC/LOD/LSD Read registers during each time of the frame Figure 9-3. Design Procedure for LED Display 9.2.2.1 Chip Index Command The chip index is used to distribute the address of the devices in a data chain. Each device gets its unique address by this command. Details can be found in Chip Index Write Command. 9.2.2.2 FC Registers Settings Some bits of FC0, FC1, FC2, FC3 registers must be configured properly before the devices work normally. In this application, the registers value can be: Table 9-4. FC Registers Value FC Registers Register Value (BIN) Register Value (HEX) FC0 0010 0000 0000 0000 1011 1000 0101 1101 1000 0001 0000 0111 b 2000 B85D 8107h FC1 0010 1010 1110 0000 0000 0000 1001 0100 1010 0110 0011 0001 b 2AE0 0094 A631 h FC2 0000 1011 1000 0000 0000 0000 0000 0000 0000 1010 1010 0000 b 0B80 0000 0AA0 h FC3 0000 0000 0011 1011 0101 0100 1010 1001 1111 1111 0000 0000 b 003B 54A9 FF00 h FC6, FC7, FC8, FC9, FC10, FC11, FC12, FC13 registers are used for programmable scanning sequence function. 56 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 The controller can configure the FC by the data write command with broadcast mode (see Data Write Command for more detail). The FC0, FC1 registers are updated after the VSYNC command comes, and the other FC registers are updated right away regardless the VSYNC command. 9.2.2.3 Grayscale Data Write The channel grayscale data is written to SRAM of the device by the data write command with non-broadcast way. Details can be found in Data Write Command and Write a Frame Data into Memory Book. Data Write Flow is the data write flow for this application, P (i, j) is the data of pixel locating in i+ 1 row and j + 1 column. Suppose channel R15/G15/B15 of each device is not used and not connected, the channel R14/G14/B14 is connected to P (i, 0), the channel R13/G13/B13 is connected to P (i, 1),…, and channel R0/G0/B0 is connected to P (i, 14). The data of unused channel must be zero noting D_Zero in below figure, and D_Zero = 00000000000000001 00000000000000001 00000000000000001b. i=0 j=15 ST+HB+P(i, jx7)+P(i, jx6)+Y+P(i, jx1)+P(i,0)+END j=j-1 N Write one line data Write one frame data j=0 Y ST+HB+D_Zero+D_Zero+Y+D_Zero+D_Zero+END i=i+1 N i=30 Y Figure 9-4. Data Write Flow 9.2.2.4 VSYNC Command The VSYNC is used to sync the display of each frame for the devices in a cascaded chain. Details can be found in VSYNC Write Command. 9.2.2.5 LED Open and Short Read FC14, FC15, FC16, FC17, FC18, FC19, FC20, FC21 are the read command for LOD/LSD information. Details can be found in Read LED-open Information and Read LED-short Information. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 57 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 9.2.3 Application Curves 58 Figure 9-5. Line and Channel Waveform in One Frame (GSn=0xFFFFh) Figure 9-6. Line and Channel Waveform in One Subperiod (GSn=0xFFFFh) Figure 9-7. Line and Channel Waveform in One Frame (GSn=0x0001h) Figure 9-8. Line and Channel Waveform in One Frame (GSn=0x0001h) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 10 Power Supply Recommendations Decouple the VCC power supply voltage by placing a 0.1-μF ceramic capacitor close to VCC pin and GND plane. Depending on panel size, several electrolytic capacitors must be placed on the board equally distributed to get well regulated LED supply voltage VR/VG/VB. The ripple of the LED supply voltage must be less than 5% of their nominal value. Generally, the green and blue LEDs have the similar forward voltage and they can be supplied by the same power rail. Furthermore, the VR > Vf(R) + 0.35 V (10-mA constant current example), the VG = VB > Vf(G/B) + 0.35 V (10-mA constant current example), here Vf(R), Vf(G/B) are representative for the maximum forward voltage of red, green/blue LEDs. To simplify the power design, VCC can be connected to VR power rail. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 59 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 11 Layout 11.1 Layout Guidelines • • • • • • Place the decoupling capacitor near the VCC/VR, VG/VB pins and GND plane. Place the current programming resistor RIREF close to IREF pin and GND plane. Route the GND thermal pad as widely as possible for large GND currents. Maximum GND current is approximately 2 A for two devices (96-CH × 20 mA = 1.92 A). The Thermal pad must be connected to GND plane because the pad is used as power ground pin internally. There is a large current flow through this pad when all channels turn on. Furthermore, this pad must be connected to a heat sink layer by thermal via to reduce device temperature. For more information about suggested thermal via pattern and via size, see PowerPAD™ Thermally Enhanced Package application note. Routing between the LED Anode side and the device OUTXn pin must be as short and straight as possible to reduce wire inductance. The line switch pins must be located in the middle of the matrix, which must be laid out as symmetrically as possible. 11.2 Layout Example To simplify the system power rails design, we suggest that VR, VCC use one power rail, and VG, VB use another power rail. Figure 11-1 gives an example for power rails routing. Connect the GND pin to thermal pad on board with the shortest wire and the thermal pad is connected to GND plane with the vias, as many as possible to help the power dissipation. 32 RGB LEDs GND VR VCC C VR VR/VCC C GND GND TLC6983 GND VG VG GND VB C VB GND C 32 Lines VG/VB VB VB VG C VG C GND GND TLC6983 GND GND VR VR VCC GND GND C C VR/VCC Figure 11-1. Power Rails Routing Suggestion Figure 11-2 gives an example for line routing. Connect the line switch to the center of the line bus, so as to uniform the current flowing from the line switch to the left side and right side LEDs in white grayscale. With this connection, the unbalance of the parasitic inductor from the routing is the smallest and the display performance is better, especially in low grayscale condition. 60 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Figure 11-2. Line Routing Suggestion Figure 11-3 gives an example for channel routing with the shortest wire. With this connection, the channel to the LED path is the shortest, which can reduce the wire inductance, and be a benefit to the performance. However, the data transmission sequence must be adjusted to follow the pins routing map. For example, R0 connects to column 15 (LED15 ). The first data must be column 15 (LED15) rather than column 0 (LED0). Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 61 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Figure 11-3. Channel Routing Suggestion With Shortest Wire Figure 11-4 gives an example for channel routing with pin number sequence. With this connection, the data transmission sequence are the same with pin number sequence. For example, R0 connects to column 0 (LED0 ). The first data is column 0 (LED0). However, with this connection, the inductance for each channel can be different, which can bring a slight difference for the worst case. 62 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 Figure 11-4. Channel Routing Suggestion With Channel Order Sequence Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 63 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 12 Device and Documentation Support 12.1 Documentation Support 12.1.1 Related Documentation • Texas Instruments, PowerPAD™ Thermally Enhanced Package application note 12.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 Glossary TI Glossary 64 This glossary lists and explains terms, acronyms, and definitions. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 TLC6984 www.ti.com SLVSG10D – NOVEMBER 2021 – REVISED JULY 2022 13 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLC6984 65 PACKAGE OPTION ADDENDUM www.ti.com 16-Mar-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) TLC6984RRFR ACTIVE VQFN RRF 76 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 TLC6984 Samples TLC6984ZXLR ACTIVE NFBGA ZXL 96 2500 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 TLC6984 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of