OPA1632
SBOS286D – DECEMBER 2003 – REVISED MARCH 2022
OPA1632 High-Performance, Fully-Differential Audio Operational Amplifier
1 Features
3 Description
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The OPA1632 is a fully-differential amplifier (FDA)
designed to drive high-performance audio analog-todigital converters (ADCs) or as a pre-driver for ClassD amplifiers. It delivers superior audio quality, very
low noise, large output voltage swing and high current
drive. The OPA1632 has an excellent gain bandwidth
of 180 MHz and very fast slew rate of 72 V/μs which
helps to produce exceptionally low distortion. A very
low input voltage noise of 1.25 nV/√Hz further ensures
maximum signal-to-noise ratio and dynamic range.
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Superior sound quality
Ultra low distortion: 0.000028%
Low noise: 1.25 nV/√Hz
High speed:
– Slew rate: 72 V/μs
– Gain bandwidth product: 180 MHz
Fully differential architecture:
– Balanced input and output converts singleended input to balanced differential output
Wide supply range: ±2.5 V to ±15 V
Shutdown current: 0.85 mA (VS = ± 5 V)
Temperature range: –40°C to +85°C
2 Applications
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Professional audio mixer or control surface
Professional microphones and wireless systems
Professional speaker systems
Professional audio amplifier
Soundbar
Turntable
Professional video camera
Guitar and other instrument amplifier
Data aquisition (DAQ)
The flexibility of the fully differential architecture
allows for easy implementation of a single-ended
to fully-differential output conversion. Differential
output reduces even-order harmonics and minimizes
common-mode noise interference. The OPA1632
provides excellent performance when used to drive
high-performance audio ADCs such as the PCM1804.
A shutdown feature is included to save power when
the device is not being used.
The OPA1632 is characterized for operation from –
40°C to +85°C and is available in an SO-8 package
and a thermally-enhanced MSOP-8 PowerPAD™
package.
Device Information(1)
PART NUMBER
OPA1632
(1)
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
MSOP-PowerPAD (8)
3.00 mm × 3.00 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
.
V+
R2
1kW
3
8
VOCM
R5
40W
5
C3
2.7nF
2 OPA1632
1
4
6
R6
40W
C2
1nF
7
R4
270W
1/2
PCM1804
VCOM
(2.5V)
THD + Noise (%)
C1
1nF
R1
1kW
Balanced or
Single-Ended
Input
1E-3
R3
270W
RL = 600 W
RL = 2 kW
1E-4
Enable
0.1 mF
V-
Application Diagram
1E-5
10
100
1k
Frequency (Hz)
10k
100k
THD + Noise vs Frequency
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA1632
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SBOS286D – DECEMBER 2003 – REVISED MARCH 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics: OPA1632D.........................7
6.6 Electrical Characteristics: OPA1632DGN................... 9
6.7 Typical Characteristics: OPA1632D.......................... 11
6.8 Typical Characteristics: OPA1632DGN.....................13
7 Detailed Description......................................................15
7.1 Overview................................................................... 15
7.2 Functional Block Diagram......................................... 15
7.3 Feature Description...................................................15
7.4 Device Functional Modes..........................................16
8 Application and Implementation.................................. 17
8.1 Application Information............................................. 17
8.2 Typical Application.................................................... 18
9 Power Supply Recommendations................................20
10 Layout...........................................................................20
10.1 Layout Guidelines................................................... 20
10.2 Layout Example...................................................... 22
11 Device and Documentation Support..........................24
11.1 Documentation Support.......................................... 24
11.2 Third-Party Products Disclaimer............................. 24
11.3 Receiving Notification of Documentation Updates.. 24
11.4 Support Resources................................................. 24
11.5 Trademarks............................................................. 24
11.6 Electrostatic Discharge Caution.............................. 24
11.7 Export Control Notice.............................................. 24
11.8 Glossary.................................................................. 25
12 Mechanical, Packaging, and Orderable
Information.................................................................... 25
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (September 2015) to Revision D (March 2022)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Updated Features section...................................................................................................................................1
• Updated Applications section............................................................................................................................. 1
• Updated Description section...............................................................................................................................1
• Changed nominal body size for both SOIC and MSOP-PowerPAD packages in Description section................1
• Updated Pin Configuration and Functions section..............................................................................................4
• Added Supply turn-on/off dV/dT specification to Absolute Maximum Ratings table........................................... 5
• Added continuous input current specification to Absolute Maximum Ratings table............................................5
• Changed differential input voltage in Absolute Maximum Ratings table from ±3V to ±1.5V .............................. 5
• Changed charged-device model (CDM) reference from JESD22-C101 to JS-002 in ESD Ratings table......... 5
• Changed minimum temperature range from 0.4℃ to -40℃ in Recommended Operating Conditions table...... 5
• Updated thermal specifications for D package in Thermal Information table..................................................... 6
• Changed typical offset voltage vs temperature from ±5 μV°C to ± 2.5 μV°C in Electrical Characteristics:
OPA1632D table................................................................................................................................................. 7
• Changed PSRR minimum limit of 316 µV/V to maximum limit in Electrical Characteristics: OPA1632D table ...
7
• Changed typical input bias current limit from 2µA to 7.9µA in Electrical Characteristics: OPA1632D table....... 7
• Changed Max input bias current limit from 6µA to 14µA in Electrical Characteristics: OPA1632D table........... 7
• Changed typical input voltage noise from 1.3nV/√Hz to 1.25nV/√Hz in Electrical Characteristics: OPA1632D
table.................................................................................................................................................................... 7
• Changed typical input current noise from 0.4 pA/√Hz to 1.7 pA/√Hz in Electrical Characteristics: OPA1632D
table.................................................................................................................................................................... 7
• Changed input impedance spec to show both common-mode and differential impedances in Electrical
Characteristics: OPA1632D table....................................................................................................................... 7
• Changed SSBW at G = +2, RF = 602 Ω from 90 MHz to 104 MHz in Electrical Characteristics: OPA1632D
table.................................................................................................................................................................... 7
• Changed SSBW at G = +5, RF = 1.5 kΩ from 36 MHz to 46 MHz in Electrical Characteristics: OPA1632D
table.................................................................................................................................................................... 7
2
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SBOS286D – DECEMBER 2003 – REVISED MARCH 2022
Changed SSBW at G = +5, RF = 1.5 kΩ from 18 MHz to 24 MHz in Electrical Characteristics: OPA1632D
table.................................................................................................................................................................... 7
Changed typical Large-Signal Bandwidth from 800 kHz to 1.8 MHz in Electrical Characteristics: OPA1632D
table.................................................................................................................................................................... 7
Changed typical slew rate from 50 V/μs to 72 V/μs in Electrical Characteristics: OPA1632D table .................. 7
Changed typical rise/fall time from 100 ns to 69 ns in Electrical Characteristics: OPA1632D table................... 7
Changed typical settling time to 0.1% from 75 ns to 36 ns in Electrical Characteristics: OPA1632D table........ 7
Changed typical settling time to 0.01% from 200 ns to 49ns in Electrical Characteristics: OPA1632D table .... 7
Changed typical THD+N with Differential Input/Output and RL = 600 Ω from 0.0003% to 0.00003% in
Electrical Characteristics: OPA1632D table........................................................................................................7
Changed typical THD+N with Differential Input/Output and RL = 2kΩ from 0.000022% to 0.000028%
in Electrical Characteristics: OPA1632D table ...................................................................................................7
Changed typical THD+N with single-ended Input/Output and RL = 600Ω from 0.000059% to 0.000036%
in Electrical Characteristics: OPA1632D table ...................................................................................................7
Changed typical THD+N with single-ended Input/Output and RL = 2kΩ from 0.000043% to 0.000031%
in Electrical Characteristics: OPA1632D table ...................................................................................................7
Changed IMD at diferrential input/output and RL= 600Ω from 0.00008% to 0.000061% in Electrical
Characteristics: OPA1632D table....................................................................................................................... 7
Changed IMD at diferrential input/output and RL= 2kΩ from 0.00005% to 0.000061% in Electrical
Characteristics: OPA1632D table ...................................................................................................................... 7
Changed IMD at single-ended input/output and RL= 600Ω from 0.0001% to 0.00007% in Electrical
Characteristics: OPA1632D table ...................................................................................................................... 7
Changed IMD at single-ended input/output and RL= 2kΩ from 0.0007% to 0.000073% in Electrical
Characteristics: OPA1632D table ...................................................................................................................... 7
Removed specified operating voltage specifications from Electrical Characteristics: OPA1632D table ............7
Changed typical IQ from 14mA to 13mA in Electrical Characteristics: OPA1632D table.................................... 7
Changed title of Electrical Characteristics table to Electrical Characteristics: OPA1632DGN............................9
Changed test condition of power-down shutdown current from VENABLE = -15 V to VS = ±5 V, VENABLE = −5 V
for Electrical Characteristics: OPA1632DGN Package....................................................................................... 9
Added power-down shutdown current spec at VENABLE = -15 V for Electrical Characteristics: OPA1632DGN
table.................................................................................................................................................................... 9
Changed max specified operating voltage from ±16 V to ±15 V on Electrical Characteristics: OPA1632DGN
table to align with recommended operating conditions.......................................................................................9
Removed typical specified operating voltage from Electrical Characteristics: OPA1632DGN table...................9
Changed typical sinking short-circuit current from 85 mA to -85 mA on Electrical Characteristics:
OPA1632DGN table............................................................................................................................................9
Added new Typical Characteristics section for D package............................................................................... 11
Updated Fully-Differential Amplifiers section.................................................................................................... 15
Updated Feature Description section............................................................................................................... 15
Updated Output Common-Mode Voltage section............................................................................................. 17
Updated Resistor Matching section.................................................................................................................. 17
Updated Application Curves section.................................................................................................................19
Updated Power Supply Recommendations section..........................................................................................20
Updated the Power Dissipation and Thermal Considerations section..............................................................21
Updated Layout Example section..................................................................................................................... 22
Changed list of documentation in Related Documentation section.................................................................. 24
Changes from Revision B (January 2010) to Revision C (September 2015)
Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1
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SBOS286D – DECEMBER 2003 – REVISED MARCH 2022
5 Pin Configuration and Functions
VIN-
1
8
VIN+
VOCM
2
7
Enable
V+
3
6
V-
VOUT+
4
5
VOUT-
Figure 5-1. D or DGN(1) Package
8-Pin SOIC or MSOP-PowerPAD
Top View
Table 5-1. Pin Functions
PIN
DESCRIPTION
NO.
Enable
7
I
V+
3
I/O
Positive supply voltage pin
V-
6
I/O
Negative supply voltage pin
VIN+
8
I
Positive input voltage pin
VIN-
1
I
Negative input voltage pin
VOCM
2
I
Output common-mode control voltage pin
VOUT+
4
O
Positive output voltage pin
VOUT-
5
O
Negative output voltage pin
(1)
(2)
4
TYPE(2)
NAME
Active high enable pin
Solder the exposed DGN package thermal pad to a heat-spreading power or ground plane. This pad is electrically isolated from the
die, but must be connected to a power or ground plane and not floated.
I = input, O = output.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN
±VS
Supply Voltage
MAX
UNIT
±16.5
Supply turn-on/off dV/dT(3)
V
1.7
V/µs
VI
Input Voltage
±VS
V
IO
Output Current
150
mA
IIN
Continuous Input Current
10
mA
VID
Differential Input Voltage
±1.5
V
TJ
Maximum Junction Temperature
TSTG
(1)
(2)
(3)
150
°C
Operating Free-Air Temperature Range
–40
85
°C
Storage Temperature Range
–65
150
°C
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
The OPA1632 MSOP-8 package version incorporates a PowerPAD on the underside of the chip. This acts as a heatsink and must
be connected to a thermally-dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum
junction temperature, which can permanently damage the device. See TI technical brief SLMA002 for more information about using the
PowerPAD thermally-enhanced package.
Staying below this specification ensures that the edge-triggered ESD absorption devices across the supply pins remain off.
6.2 ESD Ratings
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
Charged-device model (CDM), ANSI/ESDA/JEDEC
JS-002(2)
Machine Model
(1)
(2)
VALUE
UNIT
±1000
V
±500
V
±200
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Supply voltage (V+ – V-)
TA
MIN
MAX
±2.5
±15
Single
5
30
C-suffix
0
70
-40
85
Dual
I-suffix
UNIT
V
°C
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SBOS286D – DECEMBER 2003 – REVISED MARCH 2022
6.4 Thermal Information
OPA1632
THERMAL
UNIT
D (SOIC)
DGN (MSOP-PowerPAD)
8 PINS
8 PINS
RθJA
126.3
59.8
°C/W
RθJC(top)
67.3
57.7
°C/W
RθJB
69.8
38.7
°C/W
ψJT
19.5
2.7
°C/W
ψJB
69.0
38.4
°C/W
RθJC(bot)
n/a
8.4
°C/W
(1)
6
METRIC(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SBOS286D – DECEMBER 2003 – REVISED MARCH 2022
6.5 Electrical Characteristics: OPA1632D
VS = ±15 V; RF = 390 Ω, RL = 800 Ω, and G = +1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±0.5
±3
UNIT
Offset Voltage
Input Offset
Voltage
vs temperature, dc
dVOS/dT
vs Power Supply, dc
PSRR
±2.5
mV
μV/°C
13
316
μV/V
7.9
14
μA
±100
±500
nA
Input Bias Current
Input Bias Current IB
Input Offset
Current
IOS
Noise
Input Voltage Noise
f = 10 kHz
1.25
nV/√Hz
Input Current Noise
f = 10 kHz
1.7
pA/√Hz
Input Voltage
(V−) +
1.5
Common-Mode Input Range
Common-Mode Rejection Ratio, dc
74
(V+) − 1
90
V
dB
Input Impedance
Input Impedance
Measured into each input terminal,
common-mode
215 || 1.4
MΩ || pF
Measured into each input terminal,
differential
10 || 3.1
kΩ || pF
Open-Loop Gain
Open-Loop Gain, dc
66
78
dB
Frequency Response
Small-Signal
Bandwidth
(VO = 100mVPP, Peaking < 0.5 dB)
G = +1, RF= 348 Ω
180
G = +2, RF = 602 Ω
104
G = +5, RF = 1.5 kΩ
46
MHz
G = +10, RF = 3.01 kΩ
24
Bandwidth for 0.1dB Flatness
G = +1, VO = 100 mVPP
40
Peaking at a Gain of 1
VO = 100 mVPP
0.5
dB
Large-Signal Bandwidth
G = +2, VO = 20 VPP
1.8
MHz
Slew Rate (25% to 75% )
G = +1
72
V/μs
Rise and Fall Time
G = +1, VO = 5-V Step
69
ns
36
ns
49
ns
Settling Time to
0.1%
0.01%
Differential Input/Output
Total Harmonic
Distortion + Noise
Single-Ended In/Differential Out
Differential Input/Output
Intermodulation
Distortion
Single-Ended In/Differential Out
Headroom
G = +1, VO = 2-V Step
RL = 600 Ω
RL = 2 kΩ
G = +1, f = 1 kHz, VO
= 3 VRMS
RL = 600 Ω
0.00003%
0.000028%
0.000036%
RL = 2 kΩ
0.000031%
RL = 600 Ω
0.000061%
G = +1, SMPTE/DIN, RL = 2 kΩ
VO = 2 VPP
RL = 600 Ω
0.000061%
RL = 2 kΩ
THD < 0.01%, RL = 2 kΩ
MHz
0.000073%
0.00007%
20
VPP
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SBOS286D – DECEMBER 2003 – REVISED MARCH 2022
6.5 Electrical Characteristics: OPA1632D (continued)
VS = ±15 V; RF = 390 Ω, RL = 800 Ω, and G = +1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Output
RL = 2 kΩ
Voltage Output Swing Low
(V−) + 1.6
RL = 1 kΩ
RL = 2 kΩ
Voltage Output Swing High
Short-Circuit
Current
ISC
Closed-Loop Output Impedance
RL = 1 kΩ
Sourcing
Sinking
G = +1, f = 100 kHz
V
(V−) +
3.5
(V+) - 1.6
V
V
(V+) −
3.5
V
50
85
−60
–85
mA
0.22
Ω
Enable Voltage Threshold
(V−) + 1.45
V
Disable Voltage Threshold
(V−) + 1.4
V
(1)
Power-Down
Shutdown Current
Turn-On Delay
Turn-Off Delay
VS = ±5V, VENABLE = −5 V
VENABLE = −15 V
Time for IQ to Reach 50%
0.85
mA
1.7
mA
2
μs
2
μs
Power Supply
Quiescent Current IQ
(1)
8
13
17.1
mA
Amplifier has internal 250-kΩ pull-up resistor to V+ pin. This enables the amplifier with no connection to shutdown pin.
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SBOS286D – DECEMBER 2003 – REVISED MARCH 2022
6.6 Electrical Characteristics: OPA1632DGN
VS = ±15 V; RF = 390 Ω, RL = 800 Ω, and G = +1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±0.5
±3
UNIT
Offset Voltage
Input Offset Voltage
vs Power Supply, dc
dVOS/dT
vs Power Supply, dc
PSRR
316
mV
±5
μV°C
13
μV/V
Input Bias Current
Input Bias Current
IB
Input Offset Current
IOS
2
6
μA
±100
±500
nA
Noise
Input Voltage Noise
f = 10 kHz
1.3
nV/√Hz
Input Current Noise
f = 10 kHz
0.4
pA/√Hz
Input Voltage
Common-Mode Input Range
(V−) + 1.5
Common-Mode Rejection Ratio, dc
74
(V+) − 1
90
V
dB
Input Impedance
Input Impedance (each input pin)
34 || 4
MΩ || pF
Open-Loop Gain
Open-Loop Gain, dc
66
78
dB
G = +1, RF= 348 Ω
180
MHz
G = +2, RF = 602 Ω
90
MHz
G = +5, RF = 1.5 kΩ
36
MHz
G = +10, RF = 3.01 kΩ
18
MHz
Bandwidth for 0.1dB Flatness
G = +1, VO = 100 mVPP
40
MHz
Peaking at a Gain of 1
VO = 100 mVPP
0.5
dB
Large-Signal Bandwidth
G = +2, VO = 20 VPP
800
kHz
Slew Rate (25% to 75% )
G = +1
50
V/μs
Frequency Response
Small-Signal Bandwidth
(VO = 100mVPP, Peaking < 0.5 dB)
Rise and Fall Time
Settling Time to
G = +1, VO = 5-V Step
100
ns
0.1%
G = +1, VO = 2-V Step
75
ns
0.01%
G = +1, VO = 2-V Step
200
ns
Differential Input/Output
Total Harmonic
Distortion + Noise
Intermodulation
Distortion
Differential Input/Output
Single-Ended In/Differential Out
RL = 600 Ω
G = +1, f = 1 kHz,
VO = 3 VRMS
0.0003%
RL = 2 kΩ
0.000022%
RL = 600 Ω
0.000059%
Single-Ended In/Differential Out
RL = 2 kΩ
0.000043%
Differential Input/Output
RL = 600 Ω
0.00008%
Differential Input/Output
RL = 2 kΩ
0.00005%
Single-Ended In/Differential Out
G = +1, SMPTE/DIN,
VO = 2 VPP
Single-Ended In/Differential Out
Headroom
RL = 600 Ω
0.0001%
RL = 2 kΩ
0.0007%
THD < 0.01%, RL = 2 kΩ
20.0
VPP
Output
Voltage Output Swing
Short-Circuit Current
ISC
Closed-Loop Output Impedance
RL = 2 kΩ
(V+) − 1.9
RL = 800 Ω
(V+) − 4.5
Sourcing
+50
85
Sinking
−60
-85
G = +1, f = 100 kHz
0.3
(V−) + 1.9
V
(V−) + 4.5
V
mA
Ω
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SBOS286D – DECEMBER 2003 – REVISED MARCH 2022
6.6 Electrical Characteristics: OPA1632DGN (continued)
VS = ±15 V; RF = 390 Ω, RL = 800 Ω, and G = +1 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Power-Down(1)
Enable Voltage Threshold
(V−) + 2
Disable Voltage Threshold
(V−) + 0.8
Shutdown Current
VENABLE = −15 V
Shutdown Current
VS = ±5 V, VENABLE = −5 V
Turn-On Delay
Time for IQ to Reach 50%
Turn-Off Delay
Time for IQ to Reach 50%
V
V
1.7
mA
0.85
mA
2
μs
2
μs
Power Supply
Specified Operating Voltage
Operating Voltage
Quiescent Current
±15
V
17.1
mA
±2.5
IQ
Per Channel
V
14
Temperature Range
Specified Range
–40
+85
°C
Operating Range
–40
+125
°C
Storage Range
–65
+150
°C
(1)
10
Amplifier has internal 50-kΩ pull-up resistor to V+ pin. This enables the amplifier with no connection to shutdown pin.
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SBOS286D – DECEMBER 2003 – REVISED MARCH 2022
6.7 Typical Characteristics: OPA1632D
at TA = 25°C, VS = ±15 V, RF = 348 Ω, G = +1 and RL = 2 kΩ (unless otherwise noted)
1E-3
RL = 600 W
RL = 2 kW
THD + Noise (%)
THD + Noise (%)
1E-3
1E-4
1E-5
10
100
1k
Frequency (Hz)
10k
RL = 600 W
RL = 2 kW
1E-4
1E-5
10
100k
VO = 3VRMS; Differential Input and Output
100
100k
Figure 6-2. THD + Noise vs Frequency
1E-1
RL = 600 W
RL = 2 kW
RL = 600 W
RL = 2 kW
1E-2
THD + Noise (%)
1E-2
THD + Noise (%)
10k
VO = 3VRMS; Single-ended Input to Differential Output
Figure 6-1. THD + Noise vs Frequency
1E-1
1k
Frequency (Hz)
1E-3
1E-4
1E-3
1E-4
1E-5
10m
100m
1
10
Differential Output Voltage (VRMS)
1E-5
10m
100
f = 1 kHz; Differential Input and Output
100
f = 1 kHz; Single-ended Input to Differential Output
Figure 6-3. THD + Noise vs Output Voltage
1E-2
100m
1
10
Differential Output Voltage (VRMS)
Figure 6-4. THD + Noise vs Output Voltage
1E-2
RL = 600 W
RL = 2 kW
IMD (%)
1E-3
IMD (%)
1E-3
RL = 600 W
RL = 2 kW
1E-4
1E-5
10m
1E-4
100m
1
10
Differential Output Voltage (Vpp)
100
SMPTE 4:1: 60Hz, 7kHz; DIN 4:1: 250Hz, 8kHz; Differential
Input and Output
Figure 6-5. Intermodulation Distortion vs Output Voltage
1E-5
10m
100m
1
10
Differential Output Voltage (Vpp)
100
SMPTE 4:1: 60Hz, 7kHz; DIN 4:1: 250Hz, 8kHz; Differential
Input and Output
Figure 6-6. Intermodulation Distortion vs Output Voltage
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6.7 Typical Characteristics: OPA1632D (continued)
at TA = 25°C, VS = ±15 V, RF = 348 Ω, G = +1 and RL = 2 kΩ (unless otherwise noted)
10
In - Current Noise (pA/Hz)
Vn - Voltage Noise - nV/Hz
10
1
10
100
1k
Frequency (Hz)
10k
1
100k
10
100
.
10k
.
Figure 6-7. Voltage Noise vs Frequency
Figure 6-8. Current Noise vs Frequency
100
VS = 5 V
VS = 15 V
10
5
0
-5
Output Impedance (W)
15
VO - Output Voltage (V)
1k
Frequency (Hz)
10
1
-10
-15
100
1k
10k
100k
RL (W)
0.1
100k
RF= 1kΩ ; G = +2
10M
Frequency (Hz)
100M
1G
.
Figure 6-9. Output Voltage vs Differential Load Resistance
12
1M
Figure 6-10. Output Impedance vs Frequency
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6.8 Typical Characteristics: OPA1632DGN
at TA = 25°C, VS = ±15 V, and RL = 2 kΩ (unless otherwise noted)
0.001
Gain = +1
RF = 348W
VO = 3VRMS
Differential I/O
THD + Noise (%)
THD + Noise (%)
0.001
0.0001
RL = 600W
Gain = +1
RF = 348W
VO = 3VRMS
Single-Ended Input
Differential Output
0.0001
RL = 600W
RL = 2kW
RL = 2kW
0.00001
0.00001
10
100
1k
10k
100k
10
100
Frequency (Hz)
Figure 6-11. THD + Noise vs Frequency
THD + Noise (%)
0.01
RL = 600W
0.001
RL = 2kW
0.001
RL = 600W
Gain = +1
RF = 348W
f = 1kHz
Single-Ended Input
Differential Output
0.0001
0.0001
0.1
1
10
0.00001
0.01
100
Differential Output Voltage (VRMS)
0.01
0.01
RL = 600W
IMD (%)
IMD (%)
0.1
0.001
0.00001
0.01
0.1
RL = 2kW
10
10
100
RL = 600W
0.001
0.0001
1
1
Figure 6-14. THD + Noise vs Output Voltage
0.1
Gain = +1
RF = 348W
Differential I/O
SMPTE 4:1; 60Hz, 7kHz
DIN 4:1; 250Hz, 8kHz
0.1
RL = 2kW
Differential Output Voltage (VRMS)
Figure 6-13. THD + Noise vs Output Voltage
0.0001
100k
Figure 6-12. THD + Noise vs Frequency
Gain = +1
RF = 348W
f = 1kHz
Differential I/O
0.00001
0.01
10k
0.01
THD + Noise (%)
0.1
1k
Frequency (Hz)
100
Gain = +1
RF = 348W
Single-Ended Input
Differential Output
SMPTE 4:1; 60Hz, 7kHz
DIN 4:1; 250Hz, 8kHz
0.00001
0.01
Differential Output Voltage (VPP)
Figure 6-15. Intermodulation Distortion vs Output Voltage
0.1
RL = 2kW
1
10
100
Differential Output Voltage (VPP)
Figure 6-16. Intermodulation Distortion vs Output Voltage
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6.8 Typical Characteristics: OPA1632DGN (continued)
at TA = 25°C, VS = ±15 V, and RL = 2 kΩ (unless otherwise noted)
10
In (pA/ÖHz)
Vn (nV/ÖHz)
10
1
0.1
1
10
100
1k
10k
10
100k
100
VCC = ±15V
VCC = ±5V
5
VO (V)
Output Impedance (W)
10
100
RF = 1kW
G = +2
0
VCC = ±5V
-5
-10
-15
100
100k
VCC = ±5V
10
1
VCC = ±15V
1k
10k
100k
0.1
100k
RL (W)
1M
10M
100M
1G
Frequency (Hz)
Figure 6-19. Output Voltage vs Differential Load Resistance
14
10k
Figure 6-18. Current Noise vs Frequency
Figure 6-17. Voltage Noise vs Frequency
15
1k
Frequency (Hz)
Frequency (Hz)
Figure 6-20. Output Impedance vs Frequency
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7 Detailed Description
7.1 Overview
7.1.1 Fully-Differential Amplifiers
The OPA1632 is a fully differential amplifier (FDA). Differential signal processing offers a number of performance
advantages in high-speed analog signal processing systems, including immunity to external common-mode
noise, suppression of even-order non-linearities, and increased dynamic range. FDAs not only serve as the
primary means of providing gain to a differential signal chain, but also provide a monolithic solution for
converting single-ended signals into differential signals allowing for easy, high-performance processing. For
more information on the basic theory of operation for FDAs, refer to the Fully Differential Amplifiers application
note.
7.2 Functional Block Diagram
V+
Output Buffer
VIN−
x1
VOUT+
C
VIN+
R
Vcm Error
+
_
R
C
x1
VOUT−
Output Buffer
V+
30 kW
V−
30 kW
V−
VOCM
7.3 Feature Description
Figure 7-1 and Figure 7-2 depict the differences between the operation of the OPA1632 in two different modes.
FDAs can work with differential input or can be implemented as single in/differential out.
RG
RG
RF
RF
V+
V+
VSource
–
–
+
VSource
VOCM
–
+
VOUT+
+
VOCM
VOUT-
VOUT-
V-
VRG
–
+
VOUT+
RG
RF
Figure 7-1. Amplifying Differential Input Signals
RF
Figure 7-2. Amplifying Single-ended Input Signals
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7.4 Device Functional Modes
7.4.1 Shutdown Function
The shutdown (enable) function of the OPA1632 is referenced to the negative supply of the operational amplifier.
A valid logic low (< 0.8 V above negative supply) applied to the enable pin (pin 7) disables the amplifier output.
Voltages applied to pin 7 that are greater than 2 V above the negative supply place the amplifier output in an
active state, and the device is enabled. If pin 7 is left disconnected, an internal pull-up resistor enables the
device. Turn-on and turn-off times are approximately 2 μs each.
Quiescent current is reduced to approximately 0.85 mA when the amplifier is disabled. When disabled, the
output stage is not in a high-impedance state. Thus, the shutdown function cannot be used to create a
multiplexed switching function in series with multiple amplifiers.
16
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
8.1.1 Output Common-Mode Voltage
The output common-mode voltage pin sets the dc output voltage of the OPA1632. A voltage applied to the VOCM
pin from a low-impedance source can be used to directly set the output common-mode voltage. If the VOCM pin
is left floating it defaults to the mid-rail voltage, defined as:
V+ + V−
2
(1)
To minimize common-mode noise, connect a 0.1-uF bypass capacitor to the VOCM pin. Output common-mode
voltage causes additional current to flow in the feedback resistor network. Since this current is supplied by the
output stage of the amplifier, this creates additional power dissipation. For commonly-used feedback resistance
values, this current is easily supplied by the amplifier. The additional internal power dissipation created by
this current may be significant in some applications and may dictate use of the MSOP PowerPAD package to
effectively control self-heating.
8.1.1.1 Resistor Matching
Resistor matching is important in FDAs to maintain good output balance. An ideal differential output signal
implies the two outputs of the FDA should be exactly equal in amplitude and shifted 180° in phase. Any
imbalance in amplitude or phase between the two output signals results in an undesirable common-mode signal
at the output. The output balance error is a measure of how well the outputs are balanced and is defined as the
ratio of the output common-mode voltage to the output differential signal.
Output Balance Error =
VOUT + − VOUT −
2
VOUT + − VOUT −
(2)
At low frequencies, resistor mismatch is the primary contributor to output balance errors. Additionally CMRR,
PSRR, and HD2 performance diminish if resistor mismatch occurs. Therefore, it is recommended to use 1%
tolerance resistors or better to optimize performance. See Table 8-1 for recommended resistor values to use for
a particular gain.
Table 8-1. Recommended Resistor Values
Gain (V/V)
RG (Ω)
RF (Ω)
1
390
390
2
374
750
5
402
2010
10
402
4020
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8.2 Typical Application
Figure 8-1 shows the OPA1632 used as a differential-output driver for the PCM1804 high-performance audio
ADC.
V+
+8V to +16V
10mF
+
0.1mF
R3
270W
C1
1nF
R1
1kW
Balanced or +
Single- Ended
Input -
R2
1kW
3
8
VOCM
R5
40W
5
C3
2.7nF
2 OPA1632
1
6
7
4
R6
40W
C2
1nF
1/2
PCM1804
VCOM
(2.5V)
R4
270W
Enable
(1)
OPA134
1kW
0.1mF
0.1mF
10mF
+
-8V to -16V
V-
Figure 8-1. ADC Driver for Professional Audio
8.2.1 Design Requirements
Table 8-2 shows example design parameters and values for the typical application design example in Figure 7-1.
Table 8-2. Design Parameters
DESIGN PARAMETERS
18
VALUE
Supply voltage
±2.5 V to ±15 V
Amplifier topology
Voltage feedback
Output control
DC coupled with output common
mode control capability
Filter requirement
500 kHz, Multiple feedback low
pass filter
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8.2.2 Detailed Design Procedure
Supply voltages of ±15 V are commonly used for the OPA1632. The relatively low input voltage swing
by the ADC allows use of lower power-supply voltage, if desired. Power supplies as low as ±8 V can
in this application with excellent performance. This reduces power dissipation and heat rise. Power
should be bypassed with 10-μF tantalum capacitors in parallel with 0.1-μF ceramic capacitors to avoid
oscillations and instability.
required
be used
supplies
possible
The VCOM reference voltage output on the PCM1804 ADC provides the proper input common-mode reference
voltage (2.5 V). This VCOM voltage is buffered with op amp A2 and drives the output common-mode voltage pin
of the OPA1632. This biases the average output voltage of the OPA1632 to 2.5 V.
The signal gain of the circuit is generally set to approximately 0.25 to be compatible with commonly-used audio
line levels. Gain can be adjusted, if necessary, by changing the values of R1 and R2. The feedback resistor
values (R3 and R4) should be kept relatively low, as indicated, for best noise performance.
R5, R6, and C3 provide an input filter and charge glitch reservoir for the ADC. The values shown are generally
satisfactory. Some adjustment of the values may help optimize performance with different ADCs.
It is important to maintain accurate resistor matching on R1/R2 and R3/R4 to achieve good differential signal
balance. Use 1% resistors for highest performance. When connected for single-ended inputs (inverting input
grounded, as shown in Figure 8-1), the source impedance must be low. Differential input sources must have
well-balanced or low source impedance.
Capacitors C1, C2, and C3 should be chosen carefully for good distortion performance. Polystyrene,
polypropylene, NPO ceramic, and mica types are generally excellent. Polyester and high-K ceramic types such
as Z5U can create distortion.
8.2.3 Application Curves
1E-1
1E-1
RL = 600 W
RL = 2 kW
1E-2
THD + Noise (%)
THD + Noise (%)
1E-2
1E-3
1E-4
1E-5
10m
RL = 600 W
RL = 2 kW
1E-3
1E-4
100m
1
10
Differential Output Voltage (VRMS)
100
Figure 8-2. THD + Noise vs Output Voltage
1E-5
10m
100m
1
10
Differential Output Voltage (VRMS)
100
Figure 8-3. THD + Noise vs Output Voltage
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9 Power Supply Recommendations
The OPA1632 device was designed to be operated on power supplies ranging from ±2.5 V to ±15 V. Single
power supplies ranging from 5 V to 30 V can also be used. TI recommends using a power-supply accuracy
of 5%, or better. When operated on a board with high-speed digital signals, it is important to provide isolation
between digital signal noise and the analog input pins. The OPA1632 is connected to power supplies through
pin 3 (V+) and pin 6 (V-). Each supply pin should be decoupled to GND as close to the device as possible with
a low-inductance, surface-mount ceramic capacitor of approximately 10 nF. When vias are used to connect the
bypass capacitors to a ground plane the vias should be configured for minimal parasitic inductance. One method
of reducing via inductance is to use multiple vias. For broadband systems, two capacitors per supply pin are
advised.
To avoid undesirable signal transients, the OPA1632 device should not be powered on with large inputs signals
present. Careful planning of system power on sequencing is especially important to avoid damage to ADC inputs
when an ADC is used in the application.
10 Layout
10.1 Layout Guidelines
1. The PowerPAD is electrically isolated from the silicon and all leads. Connecting the PowerPAD to any
potential voltage between the power-supply voltages is acceptable, but it is recommended to tie to ground
because it is generally the largest conductive plane.
2. Prepare the PCB with a top-side etch pattern, as shown in Figure 10-1. There should be etch for the leads
as well as etch for the thermal pad.
3. Place five holes in the area of the thermal pad. These holes should be 13 mils (0,03302 cm) in diameter.
Keep them small so that solder wicking through the holes is not a problem during reflow.
4. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. These
vias help dissipate the heat generated by the OPA1632 IC, and may be larger than the 13-mil diameter
vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be
soldered so that wicking is not a problem.
5. Connect all holes to the internal ground plane.
6. When connecting these holes to the plane, do not use the typical web or spoke via connection methodology.
Web connections have a high thermal resistance connection that is useful for slowing the heat transfer
during soldering operations. This makes the soldering of vias that have plane connections easier. In this
application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the
holes under the OPA1632 PowerPAD package should make their connection to the internal plane with a
complete connection around the entire circumference of the plated-through hole.
7. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five
holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This
prevents solder from being pulled away from the thermal pad area during the reflow process.
8. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
With these preparatory steps in place, the IC is simply placed in position and runs through the solder reflow
operation as any standard surface-mount component. This results in a part that is properly installed.
Single or Dual
68mils ´ 70mils (0,1727cm ´ 0,1778cm)
(via diameter = 13mils (0,03302cm)
Figure 10-1. PowerPAD PCB Etch and Via Pattern
20
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10.1.1 PowerPAD Design Considerations
The OPA1632 is available in a thermally-enhanced PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which the die is mounted (see Figure 10-2(a) and Figure 10-2(b)).
This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package
(see Figure 10-2(c)). Because this thermal pad has direct thermal contact with the die, excellent thermal
performance can be achieved by providing a good thermal path away from the thermal pad.
DIE
(a) Side View
Thermal
Pad
DIE
(b) End View
(c) Bottom View
Figure 10-2. Views of the Thermally-Enhanced Package
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad must be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat-dissipating device.
Soldering the PowerPAD to the printed circuit board (PCB) is always required, even with applications that have
low power dissipation. It provides the necessary thermal and mechanical connection between the lead frame die
pad and the PCB.
10.1.2 Power Dissipation and Thermal Considerations
The OPA1632 does not have thermal shutdown protection. Take care to assure that the maximum junction
temperature is not exceeded. Excessive junction temperature can degrade performance or cause permanent
damage. For best performance and reliability, assure that the junction temperature does not exceed 125°C.
The thermal characteristics of the device are dictated by the package and the circuit board. Maximum power
dissipation for a given package can be calculated using the following formula:
PDMax =
TMax - TA
qJA
where:
•
•
•
•
•
•
PDMax is the maximum power dissipation in the amplifier (W)
TMax is the absolute maximum junction temperature (°C)
TA is the ambient temperature (°C)
θJA = θJC + θCA
θJC is the thermal coefficient from the silicon junctions to the case (°C/W)
θCA is the thermal coefficient from the case to ambient air (°C/W)
For systems where heat dissipation is more critical, the OPA1632 is offered in an MSOP-8 with PowerPAD. The
thermal coefficient for the MSOP PowerPAD (DGN) package is substantially improved over the traditional SO
package. Maximum power dissipation levels are depicted in Figure 10-3 for the two packages. The data for the
DGN package assume a board layout that follows the PowerPAD layout guidelines.
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Maximum Power Dissipation (W)
3.5
SO-8 (D) Package
MSOP-8 DGN Package
3
2.5
2
1.5
1
0.5
0
-40
-15
10
35
Ambient Temperature (C
60
85
Figure 10-3. Maximum Power Dissipation vs Ambient Temperature
10.2 Layout Example
RG–
RF+
VIN
RT–
V+
CBYP
RO+
–
+
VOCM
FDA
CL
–
+
PD
RO–
V+
CBYP
V–
RG+
RS+
RT+
RF–
Figure 10-4. Representative Schematic for Example Layout
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RS+
VIN
RT+
3
V+
8
Enable
7
V–
6
VOUT+
VOUT–
CL
RF–
VOCM
RF+
RO+
VIN+
2
4
Vias to connect supply pins to
CBYP. Place CBYP capacitors on
the other side of the PCB as
close to the vias as possible.
VIN–
Place the feedback resistors, RF±, gain
resistors, RG±, and the isolation
resistors, RO±, as close to the device
pins as possible to minimize parasitics
5
RO–
1
RG+
Remove GND and Power plane
under output and inverting pins to
minimize stray PCB capacitance
RG–
RT–
Ground and power plane exist on
inner layers.
Ground and power plane removed
from inner layers. Ground fill on
outer layers also removed.
Figure 10-5. Example Layout
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Fully Differential Amplifiers application note
• Texas Instruments, TI Precision Labs - Fully Differential Amplifiers video series
• Texas Instruments, Maximizing Signal Chain Distortion Performance Using High Speed Amplifiers application
note
• Texas Instruments, Analog Audio Amplifier Front-end Reference Design with Improved Noise and Distortion
• Texas Instruments, Public Announcement Audio Reference Design utilizing best in class Boost Controller
• Texas Instruments, Motherboard/controller for the AMC1210 reference design
• Texas Instruments, TPA6120A2 Stereo, 9.0 to 33.0-V, analog input headphone amplifier with 128 dB dynamic
range
• Texas Instruments, OPA2863 Dual, low-power, 110-MHz, 12-V, RRIO voltage feedback amplifier
• Texas Instruments, OPA2834 Ultra-low power, 50MHz rail-to-rail out, negative rail in, voltage-feedback op
amp
11.2 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
PowerPAD™ is a trademark of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Export Control Notice
Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as
defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled
product restricted by other applicable national regulations, received from disclosing party under nondisclosure
obligations (if any), or any direct product of such technology, to any destination to which such export or re-export
is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S.
Department of Commerce and other competent Government authorities to the extent required by those laws.
24
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11.8 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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2-Jul-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
OPA1632D
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
OPA
1632
Samples
OPA1632DG4
ACTIVE
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
OPA
1632
Samples
OPA1632DGN
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
1632
Samples
OPA1632DGNG4
ACTIVE
HVSSOP
DGN
8
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
1632
Samples
OPA1632DGNR
ACTIVE
HVSSOP
DGN
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
1632
Samples
OPA1632DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
OPA
1632
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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