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OPA180-Q1, OPA2180-Q1
SBOS861A – JUNE 2017 – REVISED JUNE 2018
OPAx180-Q1 0.1-μV/°C Drift, Low-Noise, Rail-to-Rail Output, 36-V,
Zero-Drift Operational Amplifiers
1 Features
3 Description
•
•
The OPA180-Q1 and OPA2180-Q1 operational
amplifiers (op amps) use TI's proprietary zero-drift
techniques to simultaneously provide low offset
voltage (75 μV), and near zero-drift over time and
temperature. These miniature, high-precision, lowquiescent-current op amps offer high input
impedance and rail-to-rail output swing within 18 mV
of the rails. The input common-mode range includes
the negative rail. Single- or dual-supplies ranging
from 4 V to 36 V (±2 V to ±18 V) can be used.
1
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– OPA180-Q1 Device Temperature Grade 1:
–40°C to +125°C Ambient Operating
Temperature Range
– OPA2180-Q1 Device Temperature Grade 2:
–40°C to +105°C Ambient Operating
Temperature Range
– Device HBM ESD Classification Level 1C
– Device CDM ESD Classification Level C5
– Wide Supply Range: ±2 V to ±18 V
– Low Offset Voltage: 75 μV (Maximum)
– Zero Drift: 0.1 μV/°C
– Low Noise: 10 nV/√Hz
– Very Low 1/f Noise
– Excellent DC Precision:
– PSRR: 126 dB
– CMRR: 114 dB
– Open-Loop Gain (AOL): 120 dB
– Quiescent Current: 525 μA (Maximum)
– Rail-to-Rail Output:
Input Includes Negative Rail
– Low Bias Current: 250 pA (Typical)
– RFI Filtered Inputs
– MicroSIZE Packages
The single-channel and dual-channel versions are
offered in VSSOP-8 packages. The single package
offering (OPA180-Q1) is specified from –40°C to
+125°C, and the dual package (OPA2180-Q1) is
specified from –40°C to +105°C.
Device Information(1)
DEVICE NAME
PACKAGE
BODY SIZE (NOM)
OPA180-Q1
VSSOP (8)
3.00 mm × 3.00 mm
OPA2180-Q1
VSSOP (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
space
space
space
Low Noise
(Peak-to-Peak Noise = 250 nV)
•
•
•
•
•
Automotive Precision Current Measurements
Onboard Chargers (OBC)
Battery Management Systems (BMS)
Motor Control
Traction Inverters
50 nV/div
2 Applications
Time (1 s/div)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA180-Q1, OPA2180-Q1
SBOS861A – JUNE 2017 – REVISED JUNE 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6
7.1
7.2
7.3
7.4
7.5
7.6
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information: OPA180-Q1 ............................ 7
Thermal Information: OPA2180-Q1 .......................... 7
Electrical Characteristics: VS = ±2 V to ±18 V (VS =
4 V to 36 V)................................................................ 8
7.7 Typical Characteristics: Table of Graphs ................ 10
7.8 Typical Characteristics ............................................ 11
8
Detailed Description ............................................ 15
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
15
15
16
18
Application and Implementation ........................ 19
9.1 Application Information............................................ 19
9.2 Typical Applications ................................................ 19
10 Power Supply Recommendations ..................... 23
11 Layout................................................................... 24
11.1 Layout Guidelines ................................................. 24
11.2 Layout Example .................................................... 24
12 Device and Documentation Support ................. 25
12.1
12.2
12.3
12.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
13 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
Changes from Original (June 2017) to Revision A
Page
•
Added OPA180-Q1 and OPA4180-Q1 device temperature grades to Features list ............................................................. 1
•
Changed OPA2180-Q1 device temperature grade from grade 1 to grade 2 in Features list................................................. 1
•
Changed OPA2180-Q1 ambient operating temperature range from "–40°C to +105°C" to "–40°C to +125°C" in
Features list ............................................................................................................................................................................ 1
•
Changed OPA180-Q1 and OPA4180-Q1 operating temperature from "–40°C to +105°C" to "–40°C to +125°C" in
Description section ................................................................................................................................................................. 1
•
Changed input offset voltage drift temperature range from TA = –40°C to 105°C to TA = –40°C to +125°C in
Electrical Characteristics table ............................................................................................................................................... 8
•
Changed power supply rejection ratio temperature range from TA = –40°C to 105°C to TA = –40°C to +125°C in
Electrical Characteristics table ............................................................................................................................................... 8
•
Changed OPA180-Q1 input bias current temperature range from TA = –40°C to 105°C to TA = –40°C to +125°C in
Electrical Characteristics table ............................................................................................................................................... 8
•
Changed OPA180-Q1 input offset current temperature range from TA = –40°C to 105°C to TA = –40°C to +125°C in
Electrical Characteristics table ............................................................................................................................................... 8
•
Changed common-mode rejection ratio temperature range from TA = –40°C to 105°C to TA = –40°C to +125°C in
Electrical Characteristics table ............................................................................................................................................... 8
•
Changed open-loop voltage gain temperature range from TA = –40°C to 105°C to TA = –40°C to +125°C in Electrical
Characteristics table ............................................................................................................................................................... 8
•
Changed voltage output swing from rail temperature range from TA = –40°C to 105°C to TA = –40°C to +125°C in
Electrical Characteristics table ............................................................................................................................................... 9
•
Changed quiescent current temperature range from TA = –40°C to 105°C to TA = –40°C to +125°C in Electrical
Characteristics table ............................................................................................................................................................... 9
•
Changed operating temperature from "–40°C to +105°C" to " –40°C to +125°C" in Feature Description section .............. 16
•
Updated Figure 34 ............................................................................................................................................................... 22
2
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Product Folder Links: OPA180-Q1 OPA2180-Q1
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SBOS861A – JUNE 2017 – REVISED JUNE 2018
5 Device Comparison Table
Table 1. Zero-Drift Amplifier Portfolio
VERSION
Single
Dual
Quad
PRODUCT
OFFSET VOLTAGE
(µV)
OFFSET VOLTAGE DRIFT
(µV/°C)
BANDWIDTH
(MHz)
OPA188-Q1(4 V to 36 V)
25
0.085
2
OPA180-Q1 (4 V to 36 V)
75
0.35
2
OPA333 (5 V)
10
0.05
0.35
OPA378 (5 V)
50
0.25
0.9
OPA735 (12 V)
5
0.05
1.6
OPA2188-Q1 (4 V to 36 V)
25
0.085
2
OPA2180-Q1 (4 V to 36 V)
75
0.35
2
OPA2333 (5 V)
10
0.05
0.35
OPA2378 (5 V)
50
0.25
0.9
OPA2735 (12 V)
5
0.05
1.6
OPA4188 (4 V to 36 V)
25
0.085
2
OPA4180 (4 V to 36 V)
75
0.35
2
OPA4330 (5 V)
50
0.25
0.35
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OPA180-Q1, OPA2180-Q1
SBOS861A – JUNE 2017 – REVISED JUNE 2018
www.ti.com
6 Pin Configuration and Functions
OPA180-Q1 DGK Package
8-Pin VSSOP
Top View
(1)
NC(1)
1
8
NC(1)
-IN
2
7
V+
+IN
3
6
OUT
V-
4
5
NC(1)
NC- no internal connection
Pin Functions: OPA180-Q1
PIN
NAME
DESCRIPTION
NO.
–IN
2
Inverting input
+IN
3
Noninverting input
NC
1, 5, 8
No connection
OUT
6
Output
V–
4
Negative power supply
V+
7
Positive power supply
4
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SBOS861A – JUNE 2017 – REVISED JUNE 2018
OPA2180-Q1 DGK Package
8-Pin VSSOP
Top View
OUT A
1
-IN A
2
+IN A
3
V-
4
A
B
8
V+
7
OUT B
6
-IN B
5
+IN B
Pin Functions: OPA2180-Q1
PIN
DESCRIPTION
NAME
NO.
–IN A
2
Inverting input, channel A
+IN A
3
Noninverting input, channel A
–IN B
6
Inverting input, channel B
+IN B
5
Noninverting input, channel B
OUT A
1
Output, channel A
OUT B
7
Output, channel B
V–
4
Negative power supply
V+
8
Positive power supply
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OPA180-Q1, OPA2180-Q1
SBOS861A – JUNE 2017 – REVISED JUNE 2018
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Supply voltage
Voltage
Signal input terminals
(V–) – 0.5
Current
Output short-circuit (2)
Junction temperature
Tstg
Storage temperature
(1)
(2)
UNIT
V
(V+) + 0.5
V
±10
mA
Continuous
Operating temperature
TJ
MAX
±20, ±40
(single-supply)
–55
–65
125
°C
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Short-circuit to ground, one amplifier per package.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002
(1)
UNIT
±1500
Charged-device model (CDM), per AEC Q100-011
V
±750
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted), RL = 10 kΩ connected to VS / 2, and VCOM = VOUT = VS /
2, (unless otherwise noted)
MIN
Supply voltage [(V+) – (V–)]
Operating temperature
6
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Single-supply
Bipolar-supply
NOM
MAX
UNIT
4.5
36
V
±2.25
±18
V
–40
125
°C
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: OPA180-Q1 OPA2180-Q1
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SBOS861A – JUNE 2017 – REVISED JUNE 2018
7.4 Thermal Information: OPA180-Q1
OPA180-Q1
THERMAL METRIC (1)
DGK (VSSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
180.4
°C/W
RθJC(top)
RθJB
Junction-to-case(top) thermal resistance
67.9
°C/W
Junction-to-board thermal resistance
102.1
°C/W
ψJT
Junction-to-top characterization parameter
10.4
°C/W
ψJB
Junction-to-board characterization parameter
100.3
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Thermal Information: OPA2180-Q1
OPA2180-Q1
THERMAL METRIC (1)
DGK (VSSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
159.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
37.4
°C/W
RθJB
Junction-to-board thermal resistance
48.5
°C/W
ψJT
Junction-to-top characterization parameter
1.2
°C/W
ψJB
Junction-to-board characterization parameter
77.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2017–2018, Texas Instruments Incorporated
Product Folder Links: OPA180-Q1 OPA2180-Q1
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OPA180-Q1, OPA2180-Q1
SBOS861A – JUNE 2017 – REVISED JUNE 2018
7.6
www.ti.com
Electrical Characteristics: VS = ±2 V to ±18 V (VS = 4 V to 36 V)
at TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCOM = VOUT = VS / 2, (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VIO
Input offset voltage
dVIO/dT
Input offset voltage drift
PSRR
Power-supply rejection ratio
15
75
TA = –40°C to +125°C
0.1
0.35
μV/°C
VS = 4 V to 36 V
VCM = VS / 2
0.1
0.5
μV/V
0.5
μV/V
TA = –40°C to +125°C,
VS = 4 V to 36 V
VCM = VS / 2
4 (1)
Long-term stability
Channel separation, DC
μV
μV
1
μV/V
INPUT BIAS CURRENT
OPA2180-Q1
IIB
±0.25
OPA2180-Q1:
TA = –40°C to +105°C
Input bias current
18
OPA180-Q1
±0.25
OPA180-Q1:
TA = –40°C to +125°C
18
OPA2180-Q1
IIO
±0.5
OPA2180-Q1:
TA = –40°C to +105°C
Input offset current
6
OPA180-Q1
OPA180-Q1:
TA = –40°C to +125°C
6
±1
nA
±5
nA
±1.7
nA
±6
nA
±2
nA
±2.5
nA
±3.4
nA
±3
nA
NOISE
Input voltage noise
ƒ = 0.1 Hz to 10 Hz
en
Input voltage noise density
ƒ = 1 kHz
0.25
10
nV/√Hz
in
Input current noise density
ƒ = 1 kHz
10
fA/√Hz
μVPP
INPUT VOLTAGE RANGE
VCM
Common-mode voltage range
CMRR
Common-mode rejection ratio
V–
(V+) – 1.5
V
(V–) < VCM < (V+) – 1.5 V
104
114
dB
TA = –40°C to +125°C
(V–) + 0.5 V < VCM < (V+) – 1.5 V
100
104
dB
INPUT IMPEDANCE
zid
Differential
100 || 6
MΩ || pF
zic
Common-mode
6 || 9.5
1012 Ω || pF
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
(V–) + 500 mV < VO < (V+) – 500 mV
RL = 10 kΩ
110
120
dB
TA = –40°C to +125°C
(V–) + 500 mV < VO < (V+) – 500 mV
RL = 10 kΩ
104
114
dB
FREQUENCY RESPONSE
GBW
Gain bandwidth product
SR
Slew rate
2
MHz
G=1
0.8
V/μs
0.1%
VS = ±18 V, G = 1, 10-V step
22
μs
0.01%
VS = ±18 V, G = 1, 10-V step
30
μs
1
μs
ts
Settling time
tor
Overload recovery time
VIN × G = VS
THD+N
Total harmonic distortion + noise
ƒ = 1 kHz, G = 1, VOUT = 1 VRMS
(1)
8
0.0001%
1000-hour life test at 125°C demonstrated randomly distributed variation in the range of measurement limits, or approximately 4 μV.
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SBOS861A – JUNE 2017 – REVISED JUNE 2018
Electrical Characteristics: VS = ±2 V to ±18 V (VS = 4 V to 36 V) (continued)
at TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCOM = VOUT = VS / 2, (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
No load
Voltage output swing from rail
IOS
Short-circuit current
ro
Output resistance (open loop)
CLOAD
Capacitive load drive
8
18
mV
RL = 10 kΩ
250
300
mV
TA = –40°C to +125°C
RL = 10 kΩ
325
360
mV
ƒ = 2 MHz, IO = 0 mA
120
Ω
1
nF
±18
mA
POWER SUPPLY
VS
Operating voltage range
±2 (or 4)
450
IQ
Quiescent current (per amplifier)
TA = –40°C to +125°C
IO = 0 mA
±18 (or 36)
V
525
μA
600
μA
TEMPERATURE
Specified range
–40
105
°C
Operating range
–40
105
°C
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OPA180-Q1, OPA2180-Q1
SBOS861A – JUNE 2017 – REVISED JUNE 2018
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7.7 Typical Characteristics: Table of Graphs
Table 2. Characteristic Performance Measurements
DESCRIPTION
FIGURE
IB and IOS vs Common-Mode Voltage
Figure 1
Input Bias Current vs Temperature
Figure 2
Output Voltage Swing vs Output Current (Maximum Supply)
Figure 3
CMRR vs Temperature
Figure 4
0.1-Hz to 10-Hz Noise
Figure 5
Input Voltage Noise Spectral Density vs Frequency
Figure 6
Open-Loop Gain and Phase vs Frequency
Figure 7
Open-Loop Gain vs Temperature
Figure 8
Open-Loop Output Impedance vs Frequency
Figure 9
Small-Signal Overshoot vs Capacitive Load (100-mV Output Step)
Figure 10, Figure 11
No Phase Reversal
Figure 12
Positive Overload Recovery
Figure 13
Negative Overload Recovery
Figure 14
Small-Signal Step Response (100 mV)
Figure 15, Figure 16
Large-Signal Step Response
Figure 17, Figure 18
Large-Signal Settling Time (10-V Positive Step)
Figure 19
Large-Signal Settling Time (10-V Negative Step)
Figure 20
Short-Circuit Current vs Temperature
Figure 21
Maximum Output Voltage vs Frequency
Figure 22
Channel Separation vs Frequency
Figure 23
EMIRR IN+ vs Frequency
Figure 24
10
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SBOS861A – JUNE 2017 – REVISED JUNE 2018
7.8 Typical Characteristics
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
4000
500
IIB+
+IIB
400
IIB and IIO (pA)
IIO
Input Bias Current (pA)
IIO
300
IIB-
3000
-IIB
200
100
0
-100
2000
1000
0
-1000
-200
-2000
-300
-20
-15
-10
-5
0
5
10
15
-55
20
-35
5
-15
45
65
85
105
125
Figure 2. Input Bias Current vs Temperature
20
19
18
17
16
15
14
-14
-15
-16
-17
-18
-19
-20
Common-Mode Rejection Ratio (mV/V)
Figure 1. IIB and IIO vs Common-Mode Voltage
Output Voltage (V)
25
Temperature (°C)
VCM (V)
-40°C
85°C
125°C
40
(V-) < VCM < (V+) - 1.5 V
35
(V-) + 0.5 V < VCM < (V+) - 1.5 V
30
25
20
15
10
5
0
0
2
4
6
8
10
12
14
16
18
20
22
24
-55
-35
-15
Output Current (mA)
5
25
45
65
85
105
125
Temperature (°C)
VSUPPLY = ±2 V
Figure 3. Output Voltage Swing vs Output Current
(Maximum Supply)
Figure 4. CMRR vs Temperature
50 nV/div
Voltage Noise Density (nV/ÖHz)
100
10
1
Time (1 s/div)
0.1
1
Peak-to-Peak Noise = 250 nV
Figure 5. 0.1-Hz to 10-Hz Noise
10
100
1k
10k
100k
Frequency (Hz)
Figure 6. Input Voltage Noise Spectral Density vs Frequency
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Typical Characteristics (continued)
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
180
140
VSUPPLY = 4 V, RL = 10 kW
90
60
40
2
AOL (mV/V)
Phase (°)
80
45
20
VSUPPLY = 36 V, RL = 10 kW
2.5
135
100
Gain (dB)
3
Gain
Phase
120
1.5
1
0
−20
10
100
1k
10k
100k
Frequency (Hz)
1M
10M
0.5
0
100M
0
G007
-55
-35
-15
5
25
45
65
85
105
125
Temperature (°C)
Figure 7. Open-Loop Gain and Phase vs Frequency
Figure 8. Open-Loop Gain vs Temperature
10k
40
ROUT = 0 W
35
ROUT = 25 W
ROUT = 50 W
30
Overshoot (%)
ZO (W)
1k
100
10
25
20
15
G=1
18 V
ROUT
10
Device
1
RL
-18 V
5
CL
0
1m
1
10
100
1k
10k
100k
1M
10M
0
100 200 300 400 500 600 700 800 900 1000
Frequency (Hz)
Capacitive Load (pF)
RL = 10 kΩ
Figure 9. Open-Loop Output Impedance vs Frequency
Figure 10. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
40
ROUT = 0 W
35
Device
ROUT = 50 W
30
25
-18 V
37 VPP
Sine Wave
(±18.5 V)
5 V/div
Overshoot (%)
18 V
ROUT = 25 W
20
15
RI = 10 kW
10
RF = 10 kW
G = -1
18 V
ROUT
Device
5
CL
VI
VO
-18 V
0
0
Time (100 ms/div)
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
RL = 10 kΩ
Figure 11. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
12
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Figure 12. No Phase Reversal
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SBOS861A – JUNE 2017 – REVISED JUNE 2018
Typical Characteristics (continued)
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
VI
VO
20 kW
20 kW
18 V
Device
5 V/div
5 V/div
2 kW
VO
VI
-18 V
2 kW
18 V
VI
-18 V
G = -10
G = -10
VO
VI
Time (5 ms/div)
Time (5 ms/div)
G=1
+18 V
Figure 14. Negative Overload Recovery
20 mV/div
Figure 13. Positive Overload Recovery
20 mV/div
VO
Device
RI
= 2 kW
RF
= 2 kW
18 V
Device
Device
-18 V
RL
CL
CL
-18 V
G = -1
Time (20 ms/div)
Time (1 ms/div)
RL = 10 kΩ
RL = 10 kΩ
CL = 10 pF
Figure 16. Small-Signal Step Response (100 mV)
5 V/div
5 V/div
Figure 15. Small-Signal Step Response
(100 mV)
Time (50 ms/div)
G=1
CL = 10 pF
Time (50 ms/div)
RL = 10 kΩ
CL = 10 pF
Figure 17. Large-Signal Step Response
G = –1
RL = 10 kΩ
CL = 10 pF
Figure 18. Large-Signal Step Response
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Typical Characteristics (continued)
10
10
8
8
6
6
4
12-Bit Settling
2
0
-2
(±1/2 LSB = ±0.024%)
-4
-6
D from Final Value (mV)
D from Final Value (mV)
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, unless otherwise noted.
4
0
-2
-6
-8
-10
-10
10
20
30
40
50
(±1/2 LSB = ±0.024%)
-4
-8
0
12-Bit Settling
2
60
0
10
20
30
Time (ms)
40
50
60
Time (ms)
G = –1
G = –1
Figure 19. Large-Signal Settling Time (10-V Positive Step)
Figure 20. Large-Signal Settling Time (10-V Negative Step)
30
15
20
12.5
Output Voltage (VPP)
VS = ±15 V
ISC (mA)
10
ISC, Source
0
ISC, Sink
-10
10
Maximum output voltage without
slew-rate induced distortion.
7.5
VS = ±5 V
5
2.5
-20
VS = ±2.25 V
0
-30
-55
-35
-15
5
25
45
65
85
105
1k
125
10k
Figure 21. Short-Circuit Current vs Temperature
10M
Figure 22. Maximum Output Voltage vs Frequency
Channel A to B
Channel B to A
-70
140
-80
120
EMIRR IN+ (dB)
Channel Separation (dB)
1M
160
-60
-90
-100
-110
-120
100
80
60
40
-130
20
-140
-150
1
10
100
1k
10k
100k
1M
10M
100M
0
10M
100M
Frequency (Hz)
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1G
10G
Frequency (Hz)
Figure 23. Channel Separation vs Frequency
14
100k
Frequency (Hz)
Temperature (°C)
Figure 24. EMIRR IN+ vs Frequency
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8 Detailed Description
8.1 Overview
The OPAx180-Q1 family of operational amplifiers combine precision offset and drift with excellent overall
performance, making them designed for many precision applications. The precision offset drift of only 0.1 µV/°C
provides stability over the entire temperature range. In addition, the devices offer excellent overall performance
with high CMRR, PSRR, and AOL. As with all amplifiers, applications with noisy or
high-impedance power supplies require decoupling capacitors close to the device pins. In most cases, 0.1-µF
capacitors are adequate.
8.2 Functional Block Diagram
V+
C2
CHOP1
GM1
Notch
Filter
CHOP2
GM2
GM3
OUT
+IN
-IN
C1
GM_FF
V-
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8.3 Feature Description
8.3.1 Operating Characteristics
The OPAx180-Q1 family of amplifiers is specified for operation from 4 V to 36 V (±2 V to ±18 V). Many of the
specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are presented in the Typical Characteristics.
8.3.2 EMI Rejection
The OPAx180-Q1 family uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI
interference from sources such as wireless communications and densely populated boards with a mix of analog
signal chain and digital components. EMI immunity can improve with circuit design techniques; the OPAx180-Q1
family benefits from these design improvements. Texas Instruments has developed the ability to accurately
measure and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from
10 MHz to 6 GHz. Figure 25 shows the results of this testing on the OPAx180-Q1 family . For more detailed
information, see the EMI Rejection Ratio of Operational Amplifiers application report, available for download from
www.ti.com.
160
140
EMIRR IN+ (dB)
120
100
80
60
40
20
0
10M
100M
1G
10G
Frequency (Hz)
Figure 25. OPAx180-Q1 EMIRR Testing
8.3.3 Phase-Reversal Protection
The OPAx180-Q1 family has an internal phase-reversal protection. Many op amps exhibit a phase reversal when
the input is driven beyond the linear common-mode range. This condition is most often encountered in
noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the
output to reverse into the opposite rail. The input of the OPAx180-Q1 prevents phase reversal with excessive
common-mode voltage. Instead, the output limits into the appropriate rail. This performance is shown in
Figure 26.
18 V
Device
5 V/div
-18 V
37 VPP
Sine Wave
(±18.5 V)
VI
VO
Time (100 ms/div)
Figure 26. No Phase Reversal
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Feature Description (continued)
8.3.4 Capacitive Load and Stability
The dynamic characteristics of the OPAx180-Q1 are optimized for a range of common operating conditions. The
combination of low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier and
can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated from the output.
The simplest way to achieve this isolation is to add a small resistor (for example, ROUT equal to 50 Ω) in series
with the output. Figure 27 and Figure 28 illustrate graphs of small-signal overshoot versus capacitive load for
several values of ROUT. See the Feedback Plots Define Op Amp AC Performance, application report, available
for download from the TI website, for details of analysis techniques and application circuits.
40
40
ROUT = 0 W
ROUT = 0 W
35
ROUT = 50 W
ROUT = 25 W
ROUT = 50 W
30
Overshoot (%)
30
Overshoot (%)
35
ROUT = 25 W
25
20
15
G=1
18 V
ROUT
10
-18 V
20
15
RI = 10 kW
10
Device
5
25
RL
RF = 10 kW
G = -1
18 V
ROUT
CL
Device
5
CL
-18 V
0
0
0
100 200 300 400 500 600 700 800 900 1000
0
100 200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
RL = 10 kΩ
Capacitive Load (pF)
100-mV output
step
100-mV output
step
RL = 10 kΩ
Figure 27. Small-Signal Overshoot Versus Capacitive Load
Figure 28. Small-Signal Overshoot Versus Capacitive Load
8.3.5 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress.
These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the output
pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
These ESD protection diodes also provide in-circuit, input overdrive protection, as long as the current is limited to
10 mA as stated in the Absolute Maximum Ratings table. Figure 29 shows how a series input resistor may be
added to the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier
input and the value must be kept to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10 mA max
VIN
5 kW
VOUT
Device
Figure 29. Input Current Protection
An ESD event produces a short duration, high-voltage pulse that is transformed into a short duration, highcurrent pulse as the pulse discharges through a semiconductor device. The ESD protection circuits are designed
to provide a current path around the operational amplifier core to protect the core from damage. The energy
absorbed by the protection circuitry is then dissipated as heat.
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Feature Description (continued)
When the operational amplifier connects into a circuit, the ESD protection components are intended to remain
inactive and not become involved in the application circuit operation. However, circumstances may arise when an
applied voltage exceeds the operating voltage range of a given pin. If this condition occurs, there is a risk that
some of the internal ESD protection circuits may be biased on, and conduct current. Any such current flow
occurs through ESD cells and rarely involves the absorption device.
If there is an uncertainty about the ability of the supply to absorb this current, external zener diodes may be
added to the supply pins. The zener voltage must be selected so the diode does not turn on during normal
operation.
However, the zener voltage must be low enough so that the zener diode conducts if the supply pin begins to rise
above the safe operating supply voltage level.
8.4 Device Functional Modes
The OPAx180-Q1, and OPA2180-Q1 devices are powered on when the supply is connected. These devices can
operate as a single-supply operational amplifier or dual-supply amplifier depending on the application. In singlesupply operation with V– at ground (0 V), V+ can be any value between 4 V and 36 V. In dual-supply operation,
the supply voltage difference between V– and V+ is from 4 V to 36 V. Typical examples of dual-supply
configuration are ±5 V, ±10 V, ±15 V, and ±18 V. However, the supplies must not be symmetrical. Less common
examples are V– at –3 V and V+ at 9 V, or V– at –16 V and V+ at 5 V. Any combination where the difference
between V– and V+ is at least 4 V and no greater than 36 V is within the normal operating capabilities of these
devices.
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9 Application and Implementation
9.1 Application Information
The OPAx180-Q1 family offers excellent DC precision and AC performance. These devices operate up to 36-V
supply rails and offer rail-to-rail output, ultra-low offset voltage, offset voltage drift and 2-MHz bandwidth. These
features make the OPAx180-Q1 a robust, high-performance amplifier for high-voltage industrial applications.
9.2 Typical Applications
These application examples highlight a few of the circuits where the OPAx180-Q1 family can be used.
9.2.1 Bipolar ±10-V Analog Output from a Unipolar Voltage Output DAC
This design is used for conditioning a unipolar digital-to-analog converter (DAC) into an accurate bipolar signal
source using the OPAx180-Q1 family and three resistors. The circuit is designed with reactive load stability in
mind, and is compensated to drive nearly any conventional capacitive load associated with long cable lengths.
RG1
RFB
CCOMP
VREF
RG2
VOUT
+
DAC8560
RISO
CLOAD
Device
Copyright © 2017, Texas Instruments Incorporated
Figure 30. Circuit Schematic
9.2.1.1 Design Requirements
The design requirements are as follows:
• DAC Supply Voltage: 5-V DC
• Amplifier Supply Voltage: ±15-V DC
• Input: 3-Wire, 24-Bit SPI
• Output: ±10-V DC
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Typical Applications (continued)
9.2.1.2 Detailed Design Procedure
9.2.1.2.1 Component Selection
DAC: For convenience, devices with an external reference option or devices with accessible internal references
are desirable in this application because the reference creates an offset. The DAC selection in this design must
primarily be based on DC error contributions typically described by offset error, gain error, and integral
nonlinearity error. Occasionally, additional specifications are provided that summarize end-point errors of the
DAC typically called zero-code and full-scale errors. For AC applications, slew rate and settling time may require
additional consideration.
Amplifier: Amplifier input offset voltage (VIO) is a key consideration for this design. VIO of an operational amplifier
is a typical data sheet specification, but in-circuit performance is affected by drift over temperature, the commonmode rejection ratio (CMRR), and power-supply rejection ratio (PSRR). Consideration must be given to these
parameters. For AC operation, additional considerations must be made for slew rate and settling time. Input bias
current (IIB) is also a factor, but typically the resistor network is implemented with sufficiently small resistor values
that the effects of input bias current are negligible.
Passive: Resistor matching for the op-amp resistor network is critical for the success of this design; components
with tight tolerances must be selected. For this design, 0.1% resistor values are implemented, but this constraint
may be adjusted based on application-specific design goals. Resistor matching contributes to offset error and
gain error in this design; see Bipolar ±10V Analog Output from a Unipolar Voltage Output DAC for further details.
The tolerance of the RISOand CCOMP stability components is not critical, and 1% components are acceptable.
9.2.1.3 Application Curves
Figure 31. Full-Scale Output Waveform
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Typical Applications (continued)
Figure 32. DC Transfer Characteristic
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, refer to TI Precision Design TIPD125, Bipolar ±10V Analog Output from a Unipolar Voltage Output DAC
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9.2.2 Discrete INA + Attenuation
The OPAx180-Q1 family can be used as a high-voltage, high-impedance front-end for a precision, discrete
instrumentation amplifier with attenuation. The INA159 in Figure 33 provides the attenuation that allows this
circuit to simply interface with 3.3-V or 5-V analog-to-digital converters (ADCs).
15 V
U2
½
OPA2180-Q1
VOUTP
3.3 V
VDIFF / 2
VCM
10
R5
1 kW
-15 V
Ref 2
RG
500 W
+
Ref 1
R7
1 kW
U1
INA159
VOUT
Sense
-15 V
-VDIFF / 2
U5
½
OPA2180-Q1
VOUTN
15 V
Copyright © 2017, Texas Instruments Incorporated
Figure 33. Discrete INA + Attenuation for ADC With a 3.3-V Supply
9.2.3 RTD Amplifier
The OPAx180-Q1 is excellent for use in analog linearization of resistance temperature detectors (RTDs). The
circuit below (Figure 34) combines the precision of the OPAx180-Q1 amplifier and the precision reference of the
REF5050 to linearize a Pt100 RTD.
15 V
(5 V)
Out
REF5050
In
1 µF
R2
49.1 k
1 µF
R1
4.99 k
GND
R3
60.4 k
GND
±
VOUT
+
OPA2180-Q1
RTD
Pt100
0°C = 0 V
200°C = 5 V
R5
105.8 k
R4
1k
GND
Copyright © 2017, Texas Instruments Incorporated
(1) R5 provides positive-varying excitation to linearize output.
Figure 34. RTD Amplifier with Linearization
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10 Power Supply Recommendations
The OPAx180-Q1 family is specified for operation from 4 V to 36 V (±2 V to ±18 V); many specifications apply
from –40°C to +105°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in Layout
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see Layout .
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11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are typically devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Take care to physically
separate digital and analog grounds, paying attention to the flow of the ground current.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If it is not possible to keep the input traces separate, it is much better to cross the sensitive
trace perpendicular as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As shown in Figure 35, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
11.2 Layout Example
Run the input traces
as far away from
the supply lines
as possible
Place components close
to device and to each
other to reduce parasitic
errors
VS+
RF
NC
NC
GND
±IN
V+
VIN
+IN
OUTPUT
V±
NC
Use a low-ESR,
ceramic bypass
capacitor
RG
GND
VS±
GND
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
Figure 35. Operational Amplifier Board Layout for Noninverting Configuration
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12 Device and Documentation Support
12.1 Related Links
Table 3 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
OPA180-Q1
Click here
Click here
Click here
Click here
Click here
OPA2180-Q1
Click here
Click here
Click here
Click here
Click here
12.2 Trademarks
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA180QDGKRQ1
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 105
180
OPA2180QDGKRQ1
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 105
2180
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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