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OPA192-Q1, OPA2192-Q1
SBOS850 – DECEMBER 2017
OPAx192-Q1 36-V Precision, Rail-to-Rail Input/Output,
Low-Offset Voltage, Low-Input Bias Current Op Amp With e-trim™
1 Features
3 Description
•
•
The OPAx192-Q1 family (OPA192-Q1 and OPA2192Q1) is a new generation of 36-V, e-trim operational
amplifiers. The OPAx192-Q1 family of operational
amplifiers use e-trim™, a method of package-level
trim for offset and offset temperature drift
implemented during the final steps of manufacturing
after the plastic molding process. This method
minimizes the influence of inherent input transistor
mismatch, as well as errors induced during package
molding.
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified with the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
– Device HBM ESD Classification Level 3A
– Device CDM ESD Classification Level 4A
Low Offset Voltage: ±5 µV
Low Offset Voltage Drift: ±0.2 µV/°C
Low Noise: 5.5 nV/√Hz at 1 kHz
High Common-Mode Rejection: 140 dB
Low Bias Current: ±5 pA
Rail-to-Rail Input and Output
Wide Bandwidth: 10 MHz GBW
High Slew Rate: 20 V/µs
Low Quiescent Current: 1 mA per Amplifier
Wide Supply: ±2.25 V to ±18 V, 4.5 V to 36 V
EMI/RFI Filtered Inputs
Differential Input Voltage Range to Supply Rail
High Capacitive-Load-Drive Capability: 1 nF
Industry-Standard Package:
– Single and Dual Channel in VSSOP-8
These devices offer outstanding dc precision and ac
performance, including rail-to-rail input/output, low
offset (±5 µV, typical), low offset drift (±0.2 µV/°C,
typical), and 10-MHz bandwidth.
Unique features such as differential input-voltage
range to the supply rail, high output current (±65 mA),
high capacitive-load drive of up to 1 nF, and high
slew rate (20 V/µs) make the OPAx192-Q1 a robust,
high-performance operational amplifier for highvoltage industrial applications.
The OPAx192-Q1 family of op amps is available in an
8-pin VSSOP package and is specified from –40°C to
+125°C.
Device Information(1)
PART NUMBER
2 Applications
OPA192-Q1
•
•
•
•
OPA2192-Q1
Motor Control for Automotive
Traction Inverter
On-Board Charger
Precision Current Sensing
PACKAGE
VSSOP (8)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
OPAx192-Q1 Maintains Ultra-Low Input Offset Voltage Over Temperature
100
66 Typical Units Shown
75
VOS ( V)
50
25
0
±25
±50
±75
±100
±75
±50
±25
0
25
50
75
Temperature (ƒC)
100
125
150
C001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA192-Q1, OPA2192-Q1
SBOS850 – DECEMBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
8.2 Functional Block Diagram ....................................... 21
8.3 Feature Description................................................. 22
8.4 Device Functional Modes........................................ 28
1
1
1
2
3
5
9
9.1 Application Information............................................ 29
9.2 Typical Applications ................................................ 29
10 Power-Supply Recommendations ..................... 33
11 Layout................................................................... 33
6.1
6.2
6.3
6.4
6.5
6.6
Absolute Maximum Ratings ..................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information: OPA192-Q1 ............................ 6
Thermal Information: OPA2192-Q1 .......................... 6
Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8
V to 36 V) ................................................................... 7
6.7 Electrical Characteristics: VS = ±2.25 V to ±4 V (VS =
4.5 V to 8 V)............................................................... 9
6.8 Typical Characteristics ............................................ 11
6.9 Typical Characteristics ............................................ 12
7
Parameter Measurement Information ................ 19
8
Detailed Description ............................................ 21
Application and Implementation ........................ 29
11.1 Layout Guidelines ................................................. 33
11.2 Layout Example .................................................... 34
12 Device and Documentation Support ................. 35
12.1
12.2
12.3
12.4
12.5
12.6
12.7
7.1 Input Offset Voltage Drift......................................... 19
Device Support......................................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
35
35
35
35
36
36
36
13 Mechanical, Packaging, and Orderable
Information ........................................................... 36
8.1 Overview ................................................................. 21
4 Revision History
2
DATE
REVISION
NOTES
December 2017
*
Initial release
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SBOS850 – DECEMBER 2017
5 Pin Configuration and Functions
OPA192-Q1 DGK Package
8-Pin VSSOP
Top View
NC – No internal connection.
Pin Functions: OPA192-Q1
PIN
NAME
OPA192-Q1
I/O
DESCRIPTION
DGK (VSSOP)
+IN
3
I
Noninverting input
–IN
2
I
Inverting input
NC
1, 5, 8
—
No internal connection (can be left floating)
OUT
6
O
Output
V+
7
—
Positive (highest) power supply
V–
4
—
Negative (lowest) power supply
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SBOS850 – DECEMBER 2017
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OPA2192-Q1 DGK Package
8-Pin VSSOP
Top View
Pin Functions: OPA2192-Q1
PIN
NAME
OPA2192-Q1
I/O
DESCRIPTION
DGK (VSSOP)
+IN A
3
I
Noninverting input, channel A
+IN B
5
I
Noninverting input, channel B
+IN C
—
I
Noninverting input, channel C
+IN D
—
I
Noninverting input, channel D
–IN A
2
I
Inverting input, channel A
–IN B
6
I
Inverting input, channel B
–IN C
—
I
Inverting input, channel C
–IN D
—
I
Inverting input, channel D
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
OUT C
—
O
Output, channel C
OUT D
—
O
Output, channel D
V+
8
—
Positive (highest) power supply
V–
4
—
Negative (lowest) power supply
4
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SBOS850 – DECEMBER 2017
6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage, VS = (V+) – (V–)
Signal input pins
Common-mode
Voltage
(V–) – 0.5
V
±10
mA
Continuous
Latch-up per JESD78D
Class 1
Operating range
–55
150
Junction
150
Storage, Tstg
(2)
V
(V+) – (V–) + 0.2
Current
(1)
UNIT
±20
(40, single-supply)
(V+) + 0.5
Differential
Output short circuit (2)
Temperature
MAX
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
UNIT
OPA192-Q1
V(ESD)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002 (1)
±4000
Charged device model (CDM), per AEC Q100-011
±500
Human body model (HBM), per AEC Q100-002 (1)
±4000
Charged device model (CDM), per AEC Q100-011
±500
V
OPA2192-Q1
V(ESD)
(1)
Electrostatic discharge
V
AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage, VS = (V+) – (V–)
Specified temperature
NOM
MAX
UNIT
4.5 (±2.25)
36 (±18)
V
–40
+125
°C
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SBOS850 – DECEMBER 2017
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6.4 Thermal Information: OPA192-Q1
OPA192-Q1
THERMAL METRIC (1)
DGK (VSSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
180.4
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
67.9
°C/W
Junction-to-board thermal resistance
102.1
°C/W
ψJT
Junction-to-top characterization parameter
10.4
°C/W
ψJB
Junction-to-board characterization parameter
100.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: OPA2192-Q1
OPA2192-Q1
THERMAL METRIC
(1)
DGK (VSSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
158
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
48.6
°C/W
RθJB
Junction-to-board thermal resistance
78.7
°C/W
ψJT
Junction-to-top characterization parameter
3.9
°C/W
ψJB
Junction-to-board characterization parameter
77.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBOS850 – DECEMBER 2017
6.6 Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V)
at TA = 25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±5
±25
±8
±50
±10
±75
±10
±40
TA = 0°C to 85°C
±25
±150
TA = –40°C to 125°C
±50
±250
TA = 0°C to 85°C
±0.1
±0.8
TA = –40°C to 125°C
±0.2
±1.0
±0.3
±1.0
µV/V
±5
±20
pA
±5
nA
±20
pA
±2
nA
OFFSET VOLTAGE
TA = 0°C to 85°C
VOS
Input offset voltage
TA = –40°C to 125°C
VCM = (V+) – 1.5 V
dVOS/dT
Input offset voltage drift
PSRR
Power-supply rejection
ratio
TA = –40°C to 125°C
µV
µV/°C
INPUT BIAS CURRENT
IB
IOS
Input bias current
Input offset current
TA = –40°C to 125°C
±2
TA = –40°C to 125°C
NOISE
En
Input voltage noise
en
Input voltage noise
density
(V–) – 0.1 V < VCM < (V+) – 3 V
f = 0.1 Hz to 10 Hz
1.30
(V+) – 1.5 V < VCM < (V+) + 0.1 V
f = 0.1 Hz to 10 Hz
4
(V–) – 0.1 V < VCM < (V+) – 3 V
(V+) – 1.5 V < VCM < (V+) + 0.1 V
f = 100 Hz
µVPP
10.5
f = 1 kHz
5.5
f = 100 Hz
32
f = 1 kHz
nV/√Hz
12.5
NOISE (continued)
in
Input current noise
density
f = 1 kHz
1.5
fA/√Hz
INPUT VOLTAGE
VCM
Common-mode voltage
range
(V–) – 0.1
(V–) – 0.1 V < VCM < (V+) – 3 V
CMRR
Common-mode
rejection ratio
(V+) – 1.5 V < VCM < (V+)
TA = –40°C to 125°C
TA = –40°C to 125°C
(V+) – 3 V < VCM < (V+) – 1.5 V
(V+) + 0.1
120
140
114
126
100
120
86
100
V
dB
See Typical Characteristics
INPUT IMPEDANCE
ZID
Differential
ZIC
Common-mode
100 || 1.6
1 || 6.4
MΩ || pF
1013Ω || pF
OPEN-LOOP GAIN
(V–) + 0.6 V < VO < (V+) – 0.6 V,
RLOAD = 2 kΩ
AOL
Open-loop voltage gain
(V–) + 0.3 V < VO < (V+) – 0.3 V,
RLOAD = 10 kΩ
TA = –40°C to 125°C
TA = –40°C to 125°C
120
134
114
126
126
140
120
134
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Electrical Characteristics: VS = ±4 V to ±18 V (VS = 8 V to 36 V) (continued)
at TA = 25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
GBW
Unity gain bandwidth
SR
Slew rate
G = 1, 10-V step
To 0.01%
ts
Settling time
To 0.001%
Overload recovery time
VIN × G = VS
THD+N
Total harmonic
distortion + noise
G = 1, f = 1 kHz, VO = 3.5 VRMS
Crosstalk
MHz
20
V/µs
V S = ±18 V, G = 1, 10-V
step
1.4
V S = ±18 V, G = 1, 5-V step
0.9
V S = ±18 V, G = 1, 10-V
step
2.1
V S = ±18 V, G = 1, 5-V step
tOR
10
µs
1.8
200
ns
0.00008%
OPA2192-Q1 at dc
150
OPA2192-Q1 at f = 100 kHz
130
dB
OUTPUT
No load
Positive rail
Voltage output swing
from rail
VO
Short-circuit current
CLOAD
Capacitive load drive
ZO
Open-loop output
impedance
15
95
110
RLOAD = 2 kΩ
430
500
5
15
RLOAD = 10 kΩ
95
110
RLOAD = 2 kΩ
430
500
No load
Negative rail
ISC
5
RLOAD = 10 kΩ
±65
mV
mA
See Typical Characteristics
f = 1 MHz, IO = 0 A; see Figure 29
375
Ω
POWER SUPPLY
IQ
Quiescent current per
amplifier
IO = 0 A
1
TA = –40°C to 125°C, IO = 0 A
1.2
1.5
mA
TEMPERATURE
Thermal protection (1)
(1)
8
140
°C
For a detailed description of thermal protection, see Thermal Protection .
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SBOS850 – DECEMBER 2017
6.7 Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = 4.5 V to 8 V)
at TA = 25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
±5
±25
±8
±50
±10
±75
UNIT
OFFSET VOLTAGE
VCM = (V+) – 3 V
TA = 0°C to 85°C
TA = –40°C to 125°C
VOS
Input offset voltage
(V+) – 3.5 V < VCM < (V+) – 1.5 V
VCM = (V+) – 1.5 V
dVOS/dT
Input offset voltage drift
PSRR
Power-supply rejection
ratio
VCM = (V+) – 3 V
µV
See Common-Mode Voltage Range
±10
±40
TA = 0°C to 85°C
±25
±150
TA = –40°C to 125°C
±50
±250
TA = 0°C to 85°C
±0.1
±0.8
TA = –40°C to 125°C
±0.2
±1.1
±0.5
±3
VCM = (V+) – 1.5 V, TA = –40°C to 125°C
TA = –40°C to 125°C, VCM = VS / 2 – 0.75 V
±1
µV
µV/°C
µV/V
INPUT BIAS CURRENT
IB
IOS
Input bias current
Input offset current
±5
TA = –40°C to 125°C
±2
TA = –40°C to 125°C
±20
pA
±5
nA
±20
pA
±2
nA
NOISE
En
Input voltage noise
(V–) – 0.1 V < VCM < (V+) – 3 V, f = 0.1 Hz to 10 Hz
(V–) – 0.1 V < VCM < (V+) – 3 V
en
Input voltage noise density
(V+) – 1.5 V < VCM < (V+) + 0.1 V
in
1.30
(V+) – 1.5 V < VCM < (V+) + 0.1 V, f = 0.1 Hz to 10 Hz
Input current noise density
µVPP
4
f = 100 Hz
10.5
f = 1 kHz
5.5
f = 100 Hz
32
f = 1 kHz
12.5
f = 1 kHz
1.5
nV/√Hz
fA/√Hz
INPUT VOLTAGE
VCM
Common-mode voltage
range
(V–) – 0.1
(V–) – 0.1 V < VCM < (V+) – 3 V
CMRR
Common-mode rejection
ratio
(V+) – 1.5 V < VCM < (V+)
TA = –40°C to 125°C
TA = –40°C to 125°C
(V+) – 3 V < VCM < (V+) – 1.5 V
(V+) + 0.1
94
110
90
104
100
120
84
100
V
dB
See Typical Characteristics
INPUT IMPEDANCE
ZID
Differential
ZIC
Common-mode
100 || 1.6
1 || 6.4
MΩ || pF
1013Ω || pF
OPEN-LOOP GAIN
(V–) + 0.6 V < VO < (V+) – 0.6 V,
RLOAD = 2 kΩ
AOL
Open-loop voltage gain
(V–) + 0.3 V < VO < (V+) – 0.3 V,
RLOAD = 10 kΩ
TA = –40°C to 125°C
TA = –40°C to 125°C
110
120
100
114
110
126
110
120
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Electrical Characteristics: VS = ±2.25 V to ±4 V (VS = 4.5 V to 8 V) (continued)
at TA = 25°C, VCM = VOUT = VS / 2, and RLOAD = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
FREQUENCY RESPONSE
GBW
Unity gain bandwidth
SR
Slew rate
G = 1, 10-V step
ts
Settling time
To 0.01%
tOR
Overload recovery time
Crosstalk
10
MHz
20
V/µs
1
µs
VIN× G = VS
200
ns
OPA2192-Q1 at dc
150
OPA2192-Q1 f = 100 kHz
130
VS = ±3 V, G = 1, 5-V step
dB
OUTPUT
No load
Positive rail
Voltage output swing from
rail
VO
Short-circuit current
CLOAD
Capacitive load drive
ZO
Open-loop output
impedance
15
95
110
RLOAD = 2 kΩ
430
500
5
15
RLOAD = 10 kΩ
95
110
RLOAD = 2 kΩ
430
500
No load
Negative rail
ISC
5
RLOAD = 10 kΩ
±65
mV
mA
See Typical Characteristics
f = 1 MHz, IO = 0 A; see Figure 29
375
Ω
POWER SUPPLY
IQ
Quiescent current per
amplifier
IO = 0 A
1
TA = –40°C to 125°C
1.2
1.5
mA
TEMPERATURE
Thermal protection (1)
(1)
10
140
°C
For a detailed description of thermal protection, see Thermal Protection .
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SBOS850 – DECEMBER 2017
6.8 Typical Characteristics
Table 1. Table of Graphs
DESCRIPTION
FIGURE
Offset Voltage Production Distribution
Figure 1 to Figure 6
Offset Voltage Drift Distribution
Figure 7 to Figure 8
Offset Voltage vs Temperature
Figure 9
Offset Voltage vs Common-Mode Voltage
Figure 10 to Figure 12
Offset Voltage vs Power Supply
Figure 13
Open-Loop Gain and Phase vs Frequency
Figure 14
Closed-Loop Gain and Phase vs Frequency
Figure 15
Input Bias Current vs Common-Mode Voltage
Figure 16
Input Bias Current vs Temperature
Figure 17
Output Voltage Swing vs Output Current (maximum supply)
Figure 18
CMRR and PSRR vs Frequency
Figure 19
CMRR vs Temperature
Figure 20
PSRR vs Temperature
Figure 21
0.1-Hz to 10-Hz Noise
Figure 22
Input Voltage Noise Spectral Density vs Frequency
Figure 23
THD+N Ratio vs Frequency
Figure 24
THD+N vs Output Amplitude
Figure 25
Quiescent Current vs Supply Voltage
Figure 26
Quiescent Current vs Temperature
Figure 27
Open Loop Gain vs Temperature
Figure 28
Open Loop Output Impedance vs Frequency
Figure 29
Small Signal Overshoot vs Capacitive Load (100-mV Output Step)
Figure 30, Figure 31
No Phase Reversal
Figure 32
Positive Overload Recovery
Figure 33
Negative Overload Recovery
Figure 34
Small-Signal Step Response (100 mV)
Figure 35, Figure 36
Large-Signal Step Response
Settling Time
Figure 37
Figure 38 to Figure 41
Short-Circuit Current vs Temperature
Figure 42
Maximum Output Voltage vs Frequency
Figure 43
Propagation Delay Rising Edge
Figure 44
Propagation Delay Falling Edge
Figure 45
Crosstalk vs Frequency
Figure 46
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6.9 Typical Characteristics
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, (unless otherwise noted)
50
22
18
40
16
Amplifiers (%)
Percentage of Amplifiers (%)
Distribution Taken From 190 Amplifiers
Distribution Taken From 4715 Amplifiers
20
14
12
10
8
30
20
6
10
4
Offset Voltage (µV)
Offset Voltage ( V)
C013
C032
TA = 125°C
TA = 25°C
Figure 1. Offset Voltage Production Distribution at 25°C
Distribution Taken From 190 Amplifiers
70
60
50
50
40
30
40
30
20
20
10
10
0
0
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
35
40
45
50
Amplifiers (%)
60
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
35
40
45
50
Offset Voltage (µV)
Offset Voltage (µV)
TA = 85°C
Figure 3. Offset Voltage Production Distribution at 85°C
Figure 4. Offset Voltage Production Distribution at 0°C
50
50
40
35
35
25
75
50
25
0
0
5
0
-25
5
-50
10
-75
15
10
Offset Voltage (µV)
Offset Voltage (µV)
TA = –25°C
TA = –40° C
75
20
15
50
20
30
25
25
0
30
-75
Amplifiers (%)
40
Figure 5. Offset Voltage Production Distribution at –25°C
12
Distribution Taken From 190 Amplifiers
45
-50
Distribution Taken From 190 Amplifiers
45
Amplifiers (%)
TA = 0°C
-25
Amplifiers (%)
Figure 2. Offset Voltage Production Distribution at 125°C
Distribution Taken From 190 Amplifiers
70
75
50
25
0
-25
-50
0
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7
8
9
10
0
-75
2
Figure 6. Offset Voltage Production Distribution at –40°C
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Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, (unless otherwise noted)
50
30
Distribution Taken From 75 Amplifiers
Distribution Taken From 75 Amplifiers
25
20
Amplifiers (%)
30
20
15
10
10
Offset Voltage Drift (µV/ƒC)
0.8
0.6
0.7
0.4
0.5
0.2
0.3
0
0.1
-0.2
-0.1
-0.4
-0.3
-0.6
-0.5
-0.8
0
1.1
0.9
0.7
0.5
0.3
0.1
-0.1
-0.3
-0.7
-0.9
-1.1
0
-0.5
5
-0.7
Amplifiers (%)
40
Offset Voltage Drift (µV/ƒC)
OPA192-Q1IDGK and OPA2192-Q1IDGK
TA = –40°C to +125°C
OPA192-Q1IDGK and OPA2192-Q1IDGK
TA = 0°C to 85°C
Figure 7. Offset Voltage Drift Distribution
Figure 8. Offset Voltage Drift Distribution
100
50
190 Typical Units Shown
5 Typical Units Shown
75
25
25
VOS ( V)
VOS ( V)
50
0
±25
0
VCM = -18.1 V
±50
±25
±75
±100
±75
±50
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
±20
±15
±10
±5
0
5
10
15
VCM (V)
C001
Figure 9. Offset Voltage vs Temperature
20
C001
Figure 10. Offset Voltage vs Common-Mode Voltage
200
100
5 Typical Units Shown
150
75
5 Typical Units Shown
VCM = +18.1 V
100
25
VCM = -18.1 V
50
VOS(μV)
VOS ( V)
50
0
±25
±50
P-Channel
N-Channel
±50
±100
±75
±100
12.5
0
VCM = +2.35 V
VCM = -2.35 V
±150
Transition
13.5
14.5
15.5
VCM (V)
16.5
17.5
18.5
Transition
P-Channel
±200
±2.5 ±2.0 ±1.5 ±1.0 ±0.5 0.0 0.5
N-Channel
1.0
1.5
2.0
2.5
VCM (V)
C001
VS = ±2.25 V
Figure 11. Offset Voltage vs Common-Mode Voltage
Figure 12. Offset Voltage vs Common-Mode Voltage
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Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, (unless otherwise noted)
50
180
140.0
10 Typical Units Shown
40
120.0
30
Gain (dB)
10
0
±10
135
80.0
Phase
60.0
90
40.0
Phase (ƒ)
VOS(μV)
Open-loop Gain
100.0
20
±20
45
20.0
±30
0.0
±40
±50
0.0
2.0
4.0
6.0
8.0
10.0 12.0 14.0 16.0 18.0 20.0
±20.0
1
10
100
VSUPPLY (V)
VS = ±2.25 V to ±18 V
1M
0
10M 100M
CLOAD = 15 pF
Figure 13. Offset Voltage vs Power Supply
60.0
Figure 14. Open-Loop Gain and Phase vs Frequency
20
G = -100
G = +1
G = -1
G = -10
15
Input Bias Current (pA)
40.0
Gain (dB)
1k
10k 100k
Frequency (Hz)
20.0
0.0
IB-
10
5
0
IB+
±5
±10
±15
±20.0
1000
10k
100k
1M
±20
±18.0
10M
Frequency (Hz)
Figure 15. Closed-Loop Gain and Phase vs Frequency
18.0
C001
Figure 16. Input Bias Current vs Common-Mode Voltage
(V-) + 5
IB+
IB Ios
5000
(V-) + 4
+125°C
4000
(V-) + 3
3000
Vout (V)
Input Bias Current (pA)
9.0
VCM (V)
6000
2000
(V-) + 2
-40°C
(V-) + 1
1000
(V-)
Ios
0
(V-) - 1
±1000
±75
±50
±25
0
25
50
75
100
125
150
Temperature (ƒC)
Figure 17. Input Bias Current vs Temperature
14
0.0
±9.0
C003
175
0
10
20
30
40
Iout (mA)
C001
50
60
70
80
C001
Figure 18. Output Voltage Swing vs Output Current
(Maximum Supply)
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Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, (unless otherwise noted)
Common-Mode Rejection Ratio (µV/V)
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
160.0
140.0
120.0
100.0
80.0
60.0
+PSRR
40.0
CMRR
20.0
-PSRR
10
8
6
4
VS = ±2.25 V, VCM = V+ - 3 V
2
0
±2
VS = ±18 V, VCM = 0 V
±4
±6
±8
±10
0.0
1
10
100
1k
10k
100k
±75
1M
Frequency (Hz)
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
C012
Figure 19. CMRR and PSRR vs Frequency
150
C001
Figure 20. CMRR vs Temperature
0.8
0.6
0.4
400 nV/div
Power-Supply Rejection Ratio (µV/V)
1
0.2
0
-0.2
-0.4
-0.6
-0.8
Peak-to-Peak Noise = VRMS × 6.6 = 1.30 Vpp
-1
±75
±50
±25
0
25
50
75
100
125
Time (1 s/div)
150
Temperature (ƒC)
C001
C001
Figure 21. PSRR vs Temperature
Figure 22. 0.1-Hz to 10-Hz Noise
Total Harmonic Distortion + Noise (%)
Voltage Noise Density (nV/rtHz)
VCM = V+ - 100 mV
N-Channel Input
100
10
VCM = 0 V
P-Channel Input
1
10
100
1k
10k
G = +1 V/V, RL = 2 kΩ
G = -1 V/V, RL = 10 kΩ
0.01
-80
G = -1 V/V, RL = 2 kΩ
0.001
-100
0.0001
-120
0.00001
1
0.1
-60
G = +1 V/V, RL = 10 kΩ
100k
Frequency (Hz)
-140
10
100
1k
10k
Frequency (Hz)
C002
VOUT = 3.5 VRMS
Figure 23. Input Voltage Noise Spectral Density
vs Frequency
Total Harmonic Distortion + Noise (dB)
0.1
1000
BW = 80 kHz
Figure 24. THD+N Ratio vs Frequency
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Typical Characteristics (continued)
-60
0.01
-80
0.001
-100
0.0001
-120
G = +1 V/V, RL = 10 kΩ
G = +1 V/V, RL = 2 kΩ
G = -1 V/V, RL = 10 kΩ
G = -1 V/V, RL = 2 kΩ
0.00001
0.01
0.1
1.2
1.1
IQ (mA)
0.1
Total Harmonic Distortion + Noise (dB)
Total Harmonic Distortion + Noise (%)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, (unless otherwise noted)
0.9
-140
1
1.0
0.8
10
0
4
8
12
Output Amplitude (VRMS)
16
20
24
28
32
36
Supply Voltage (V)
C001
f = 1 kHz, BW = 80 kHz
Figure 25. THD+N vs Output Amplitude
Figure 26. Quiescent Current vs Supply Voltage
3.0
1.2
Vs = 4.5 V
Vs = 36 V
2.0
1.1
AOL (µV/V)
IQ (mA)
1.0
Vs = ±18 V
1
Vs = ±2.25 V
0.0
±1.0
0.9
±2.0
±3.0
0.8
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
±75
150
±50
±25
0
25
50
75
100
125
150
Temperature (ƒC)
C001
RL = 10 kΩ
Figure 28. Open-Loop Gain vs Temperature
Figure 27. Quiescent Current vs Temperature
50
10k
45
+ 18 V
35
1k
Overshoot (%)
Output Impedance ( )
40
100
-
+
+
-
30
R ISO
OP A192-Q1
V IN
CL
-18 V
25
20
R ISO = 0 0Ω
15
R ISO = 25 25
Ω
10
R ISO = 50 Ω50
5
0
10
0
1
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
10p
RI = 1 kΩ
Figure 29. Open-Loop Output Impedance vs Frequency
16
100p
1n
Capacitive Load (F)
C016
RF = 1 kΩ
G = –1
Figure 30. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
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Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, (unless otherwise noted)
50
-
-
RISO
OPA192-Q1
+
+
35
VIN
CL
-
30
VOUT
OPA192-Q1
RL
+
+
-
37 VPP -18 V
Sine Wave
(±18.5V)
-18 V
5 V/div
Overshoot (%)
40
VIN
+ 18 V
+ 18 V
45
25
20
15
VOUT
RISO = 0 Ω0
RISO = 25
25 Ω
RISO = 50
50 Ω
10
5
0
10p
100p
1n
Time (200 μs/div)
Capacitive Load (F)
G=1
Figure 31. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
Figure 32. No Phase Reversal
+ 18 V
VOUT
-
+
OP A192-Q1
OP A192-Q1
V OUT
+
V IN
-
VOUT
-18 V
5 V/div
5 V/div
-
-
+
V OUT
+
V IN
+ 18 V
- 18 V
VIN
VIN
Time (200 ns/div)
RI = 1 kΩ
Time (200 ns/div)
RF = 10 kΩ
G = –10
RI = 1 kΩ
Figure 33. Positive Overload Recovery
G = –10
RF = 10 kΩ
Figure 34. Negative Overload Recovery
+ 18 V
+
-
20 mV/div
20 mV/div
V IN
+ 18 V
-
OP A192-Q1
+
CL
- 18 V
OPA192-Q1
+
VIN
+
-18 V
RL
CL
-
Time (120 ns/div)
Time (100 ns/div)
CL = 10 pF
RL = 1 kΩ
G=1
Figure 35. Small-Signal Step Response (100 mV)
CL = 10 pF
G = –1
Figure 36. Small-Signal Step Response (100 mV)
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Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, (unless otherwise noted)
2 V/div
Output Delta from Final Value (mV)
4
+ 18 V
-
+
OP A192-Q1
+
V IN
-
CL
-18 V
3
2
1
0
-1
0.01% Settling = ±1 mV
-2
-3
Step Applied at t = 0
-4
0
Time (300 ns/div)
RL = 1 kΩ
CL = 10 pF
0.25
0.5
0.75
G = –1
1
1.25
1.5
1.75
2
Time (μs)
G=1
Figure 38. Settling Time (10-V Positive Step)
Figure 37. Large-Signal Step Response
4
Output Delta from Final Value (mV)
Output Delta from Final Value (mV)
4
3
2
1
0
0.01% Settling = ±500 μV
-1
-2
-3
Step Applied at t = 0
3
2
1
0
-1
0.01% Settling = ±1 mV
-2
-3
Step Applied at t = 0
-4
-4
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
0
1.8
0.2
0.4
0.6
0.8
G=1
1.2
1.4
1.6
1.8
2
G=1
Figure 39. Settling Time (5-V Positive Step)
Figure 40. Settling Time (10-V Negative Step)
4
80
ISC, Source
3
2
ISC, Sink
60
1
ISC (mA)
Output Delta from Final Value (mV)
1
Time (μs)
Time (μs)
0
0.01% Settling = ±500 μV
-1
-2
40
20
-3
Step Applied at t = 0
-4
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
±75
±50
±25
Time (μs)
0
25
50
75
100
125
150
Temperature (ƒC)
C001
G=1
Figure 41. Settling Time (5-V Negative Step)
18
Figure 42. Short-Circuit Current vs Temperature
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Typical Characteristics (continued)
at TA = 25°C, VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF, (unless otherwise noted)
30
Maximum output voltage without
slew-rate induced distortion.
VS = ±15 V
Overdrive = 100 mV
Output Voltage (5 V/div)
Output Voltage (VPP)
25
20
15
VS = ±5 V
10
VS = ±2.25 V
5
tpLH = 0.97 s
VOUT Voltage
0
10k
100k
1M
Time (200 ns/div)
10M
Frequency (Hz)
C025
C033
Figure 43. Maximum Output Voltage vs Frequency
Figure 44. Propagation Delay Rising Edge
-100
VOUT Voltage
Crosstalk (db)
Output Voltage (1 V/div)
-80
tpLH = 1.1 s
Overdrive = 100 mV
-120
-140
-160
-180
1k
Time (200 ns/div)
10k
Figure 45. Propagation Delay Falling Edge
100k
1M
Frequency (Hz)
C026
Figure 46. Crosstalk vs Frequency
7 Parameter Measurement Information
7.1 Input Offset Voltage Drift
The OPAx192-Q1 family of operational amplifiers is manufactured using TI’s e-trim technology. Each amplifier
input offset voltage and input offset voltage drift is trimmed in production, thereby minimizing errors associated
with input offset voltage and input offset voltage drift. The e-trim technology is a TI proprietary method of
trimming internal device parameters during either wafer probing or final testing. When trimming input offset
voltage drift the systematic or linear drift error on each device is trimmed to zero. This results in the remaining
errors associated with input offset drift are minimal and are the result from only nonlinear error sources.
Figure 47 illustrates this concept.
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Input Offset Voltage Drift (continued)
Input Offset Voltage
VOS Before e-trim
VOS After e-trim
Linear component of drift
Linear component of drift
Temperature
Figure 47. Input Offset Before and After Drift Trim
Figure 48 shows six typical units.
75
6 Typical Units Shown
50
31
VOS ( V)
25
0
±25
-3 1
±50
±75
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
C001
Figure 48. Input Offset Voltage Drift vs Temperature for Six Typical Units
20
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SBOS850 – DECEMBER 2017
8 Detailed Description
8.1 Overview
The OPAx192-Q1 family of operational amplifiers use e-trim, a method of package-level trim for offset and offset
temperature drift implemented during the final steps of manufacturing after the plastic molding process. This
method minimizes the influence of inherent input transistor mismatch, as well as errors induced during package
molding. The trim communication occurs on the output pin of the standard pinout, and after the trim points are
set, further communication to the trim structure is permanently disabled. The Functional Block Diagram shows
the simplified diagram of the OPAx192-Q1 with e-trim.
Unlike previous e-trim op amps, the OPAx192-Q1 uses a patented two-temperature trim architecture to achieve a
very low offset voltage of 25 µV (maximum) and low voltage offset drift of 0.5 µV/°C (maximum) over the full
specified temperature range. This level of precision performance at wide supply voltages makes these amplifiers
useful for high-impedance industrial sensors, filters, and high-voltage data acquisition.
8.2 Functional Block Diagram
OPAx192-Q1
NCH Input
Stage
IN+
36-V
Differential
Front End
Slew
Boost
IN-
High Capacitive
Load
Compensation
Output
Stage
VOUT
PCH Input
Stage
±
e-trim
Package Level Trim
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8.3 Feature Description
8.3.1 Input Protection Circuitry
The OPAx192-Q1 uses a unique input architecture to eliminate the need for input protection diodes but still
provides robust input protection under transient conditions. Conventional input diode protection schemes shown
in Figure 49 can be activated by fast transient step responses and can introduce signal distortion and settling
time delays because of alternate current paths, as shown in Figure 50. For low-gain circuits, these fast-ramping
input signals forward-bias back-to-back diodes, causing an increase in input current, and resulting in extended
settling time, as shown in Figure 51.
V+
V+
VIN+
VIN+
VOUT
36 V
VOUT
OPAx192-Q1
~0.7 V
VIN
VIN
V
OPA192-Q1 Provides Full
36-V Differential Input
Range
V
Conventional Input Protection
Limits Differential Input Range
Copyright © 2017, Texas Instruments Incorporated
Figure 49. OPAx192-Q1 Input Protection Does Not Limit Differential Input Capability
Vn = +10 V
RFILT
+10 V
1
Ron_mux
Sn
1
D
+10 V
CFILT
2
~±9.3 V
CS
CD
Vn+1 = ±10 V RFILT
±10 V
Vin±
2
Ron_mux
Sn+1
~0.7 V
CS
CFILT
Vout
Idiode_transient
±10 V
Input Low Pass Filter
Vin+
Buffer Amplifier
Simplified Mux Model
Figure 50. Back-to-Back Diodes Create Settling Issues
Output Delta From Final Value (mV)
100
Standard Input Diode Structure
Extends Settling Time
80
60
40
0.1% Settling = ±10 mV
20
0
–20
OPA192-Q1 Input Structure
Offers Fast Settling
–40
–60
–80
–100
0
5
10
15
20
25
30
35
40
45
50
55
Time (µs)
60
C040
Figure 51. OPAx192-Q1 Protection Circuit Maintains Fast-Settling Transient Response
22
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Feature Description (continued)
The OPAx192-Q1 family of operational amplifiers provides a true high-impedance differential input capability for
high-voltage applications. This patented input protection architecture does not introduce additional signal
distortion or delayed settling time, making the device an optimal op amp for multichannel, high-switched, input
applications. The OPAx192-Q1 can tolerate a maximum differential swing (voltage between inverting and
noninverting pins of the op amp) of up to 36 V, making the device suitable for use as a comparator or in
applications with fast-ramping input signals such as multiplexed data-acquisition systems; see Figure 61.
8.3.2 EMI Rejection
The OPAx192-Q1 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the OPAx192-Q1 benefits
from these design improvements. Texas Instruments has developed the ability to accurately measure and
quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz
to 6 GHz. Figure 52 shows the results of this testing on the OPAx192-Q1. Table 2 shows the EMIRR IN+ values
for the OPAx192-Q1 at particular frequencies commonly encountered in real-world applications. Applications
listed in Table 2 may be centered on or operated near the particular frequency shown. Detailed information can
also be found in the application report EMI Rejection Ratio of Operational Amplifiers available for download from
www.ti.com.
160.0
140.0
PRF = -10 dBm
VSUPPLY = ±18 V
VCM = 0 V
EMIRR IN+ (dB)
120.0
100.0
80.0
60.0
40.0
20.0
0.0
10M
100M
1G
Frequency (Hz)
10G
C017
Figure 52. EMIRR Testing
Table 2. OPAx192-Q1 EMIRR IN+ For Frequencies of Interest
FREQUENCY
APPLICATION OR ALLOCATION
EMIRR IN+
400 MHz
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF)
applications
44.1 dB
900 MHz
Global system for mobile communications (GSM) applications, radio communication, navigation,
GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications
52.8 dB
1.8 GHz
GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz)
61.0 dB
2.4 GHz
802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and
medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz)
69.5 dB
3.6 GHz
Radiolocation, aero communication and navigation, satellite, mobile, S-band
88.7 dB
802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite
operation, C-band (4 GHz to 8 GHz)
105.5 dB
5 GHz
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8.3.3 Phase Reversal Protection
The OPAx192-Q1 family has internal phase-reversal protection. Many op amps exhibit a phase reversal when
the input is driven beyond its linear common-mode range. This condition is most often encountered in
noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the
output to reverse into the opposite rail. The OPAx192-Q1 is a rail-to-rail input op amp; therefore, the commonmode range can extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the
output limits into the appropriate rail. This performance is shown in Figure 53.
VIN
+ 18 V
VOUT
OPA192-Q1
+
-
37 VPP -18 V
Sine Wave
(±18.5V)
5 V/div
+
VOUT
Time (200 μs/div)
Figure 53. No Phase Reversal
8.3.4 Thermal Protection
TA = 65°C
PD = 0.81W
JA = 116°C/W
TJ = 116°C/W × 0.81W + 65°C
TJ = 159°C (expected)
+30 V
VOUT
The internal power dissipation of any amplifier causes its internal (junction) temperature to rise. This
phenomenon is called self heating. The absolute maximum junction temperature of the OPAx192-Q1 is 150°C.
Exceeding this temperature causes damage to the device. The OPAx192-Q1 has a thermal protection feature
that prevents damage from self heating. The protection works by monitoring the temperature of the device and
turning off the op amp output drive for temperatures above 140°C. Figure 54 shows an application example for
the OPAx192-Q1 that has significant self heating (159°C) because of the power dissipation (0.81 W). Thermal
calculations indicate that for an ambient temperature of 65°C the device junction temperature must reach 187°C.
The actual device, however, turns off the output drive to maintain a safe junction temperature. Figure 54 shows
how the circuit behaves during thermal protection. During normal operation, the device acts as a buffer so the
output is 3 V. When self heating causes the device junction temperature to increase above 140°C, the thermal
protection forces the output to a high-impedance state and the output is pulled to ground through resistor RL.
3V
Normal
Operation
0V
Output
High-Z
150°C
OPAx192-Q1
+
±
VIN
3V
+
RL
3V
100 Ÿ ±
140ºC
Temperature
IOUT = 30 mA
Copyright © 2017, Texas Instruments Incorporated
Figure 54. Thermal Protection
8.3.5 Capacitive Load and Stability
The OPAx192-Q1 features a patented output stage capable of driving large capacitive loads, and in a unity-gain
configuration, directly drives up to 1 nF of pure capacitive load. Increasing the gain enhances the ability of the
amplifier to drive greater capacitive loads; see Figure 55 and Figure 56. The particular op amp circuit
configuration, layout, gain, and output loading are some of the factors to consider when establishing whether an
amplifier is stable in operation.
24
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50
50
+ 18 V
45
45
-
+ 18 V
40
+
OP A192-Q1
+
V IN
-
30
40
R ISO
Overshoot (%)
35
Overshoot (%)
-
CL
-18 V
25
RISO
OPA192-Q1
+
35
VIN
+
RL
30
25
20
20
R ISO = 0 0Ω
15
R ISO = 25 25
Ω
15
10
R ISO = 50 Ω50
10
RISO = 0 Ω0
RISO = 25
25 Ω
RISO = 50
50 Ω
5
5
0
0
10p
100p
1n
CL
-18 V
-
10p
100p
1n
Capacitive Load (F)
Capacitive Load (F)
Figure 55. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
Figure 56. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small
(10 Ω to 20 Ω) resistor, RISO, in series with the output, as shown in Figure 57. This resistor significantly reduces
ringing and maintains dc performance for purely capacitive loads. However, if a resistive load is in parallel with
the capacitive load, then a voltage divider is created, thus introducing a gain error at the output and slightly
reducing the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible at
low output levels. A high capacitive-load drive makes the OPAx192-Q1 work well with applications such as
reference buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 57 uses an isolation
resistor, RISO, to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for increased
phase margin, and results using the OPAx192-Q1 are summarized in Table 3. For additional information on
techniques to optimize and design using this circuit, TI Precision Design Capacitive Load Drive Solution using an
Isolation Resistor details complete design goals, simulation, and test results.
+Vs
Vout
Riso
+
Vin
Cload
+
±
-Vs
Figure 57. Extending Capacitive Load Drive with the OPAx192-Q1
Table 3. OPAx192-Q1 Capacitive Load Drive Solution Using Isolation Resistor Comparison of
Calculated and Measured Results
PARAMETER
VALUE
Capacitive Load
100 pF
1000 pF
0.01 µF
0.1 µF
1 µF
Phase Margin
45°
60°
45°
60°
45°
60°
45°
60°
45°
60°
RISO (Ω)
47
360
24
100
20
51
6.2
15.8
2
4.7
Measured
Overshoot (%)
23.2 8.6
10.4
22.5
9.0
22.1
8.7
23.1
8.6
21
8.6
Calculated PM
45.1°
58.1°
45.8°
59.7°
46.1°
60.1°
45.2°
60.2°
47.2°
60.2°
For step-by-step design procedure, circuit schematics, bill of materials, printed circuit board (PCB) files,
simulation results, and test results, refer to TI Precision Design TIDU032, Capacitive Load Drive Solution using
an Isolation Resistor .
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8.3.6 Common-Mode Voltage Range
The OPAx192-Q1 is a 36-V, true rail-to-rail input operational amplifier with an input common-mode range that
extends 100 mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel
and P-channel differential input pairs, as shown in Figure 58. The N-channel pair is active for input voltages
close to the positive rail, typically (V+) – 3 V to 100 mV above the positive supply. The P-channel pair is active
for inputs from 100 mV below the negative supply to approximately (V+) – 1.5 V. There is a small transition
region, typically (V+) –3 V to (V+) – 1.5 V in which both input pairs are on. This transition region can vary
modestly with process variation, and within this region PSRR, CMRR, offset voltage, offset drift, noise and THD
performance may be degraded compared to operation outside this region.
+Vsupply
IS1
VINPCH1
NCH4
NCH3
PCH2
VIN+
e-TrimTM
FUSE BANK
VOS TRIM
VOS DRIFT TRIM
-Vsupply
Figure 58. Rail-to-Rail Input Stage
To achieve the best performance for two-stage rail-to-rail input amplifiers, avoid the transition region when
possible. The OPAx192-Q1 uses a precision trim for both the N-channel and P-channel regions. This technique
enables significantly lower levels of offset than previous-generation devices, causing variance in the transition
region of the input stages to appear exaggerated relative to offset over the full common-mode range, as shown in
Figure 59.
Transition
Region
N-Channel
Region
P-Channel
Region
200
200
100
100
Input Offset Voltage ( V)
Input Offset Voltage ( V)
P-Channel
Region
0
±100
OPA192 e-Trim
Input Offset Voltage vs Vcm
±200
Transition
Region
N-Channel
Region
0
±100
±200
Input Offset Voltage vs Vcm
without e-Trim Input
±300
±15.0
±14.0
«
11.0
12.0
13.0
Common-Mode Voltage (V)
14.0
15.0
±300
±15.0
±14.0
«
11.0
12.0
13.0
Common-Mode Voltage (V)
14.0
15.0
Figure 59. Common-Mode Transition vs Standard Rail-to-Rail Amplifiers
26
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8.3.7 Electrical Overstress
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress
(EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the
output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. Figure 60 shows an illustration of the ESD circuits contained in the OPAx192-Q1 (indicated by the
dashed line area). The ESD protection circuitry involves several current-steering diodes connected from the input
and output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption
device or the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to
remain inactive during normal circuit operation.
TVS
+
±
RF
+VS
OPAx192-Q1
VDD
R1
RS
IN±
100 Ÿ
IN+
100 Ÿ
±
+
Power Supply
ESD Cell
VIN
RL
+
±
VSS
+
±
±VS
TVS
Copyright © 2017, Texas Instruments Incorporated
Figure 60. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
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An ESD event is very short in duration and very high voltage (for example, 1 kV, 100 ns), whereas an EOS event
is long duration and lower voltage (for example, 50 V, 100 ms). The ESD diodes are designed for out-of-circuit
ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB).
During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit (labeled
ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level.
Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if
activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by
turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting
resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.
8.3.8 Overload Recovery
Overload recovery is defined as the time required for the op amp output to recover from a saturated state to a
linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds the
rated operating voltage, either due to the high input voltage or the high gain. After the device enters the
saturation region, the charge carriers in the output devices require time to return back to the linear state. After
the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the
propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.
The overload recovery time for the OPAx192-Q1 is approximately 200 ns.
8.4 Device Functional Modes
The OPAx192-Q1 has a single functional mode and is operational when the power-supply voltage is greater than
4.5 V (±2.25 V). The maximum power supply voltage for the OPAx192-Q1 is 36 V (±18 V).
28
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The OPAx192-Q1 family offers outstanding dc precision and ac performance. These devices operate up to 36-V
supply rails and offer true rail-to-rail input and output, ultra-low offset voltage and offset voltage drift, as well as
10-MHz bandwidth and high capacitive load drive. These features make the OPAx192-Q1 a robust, highperformance operational amplifier for high-voltage industrial applications.
9.2 Typical Applications
9.2.1 16-Bit Precision Multiplexed Data-Acquisition System
Figure 61 shows a 16-bit, differential, 4-channel, multiplexed data-acquisition system. This example is typical in
industrial applications that require low distortion and a high-voltage differential input. The circuit uses the
ADS8864, a 16-bit, 400-kSPS successive-approximation-resistor (SAR) analog-to-digital converter (ADC), along
with a precision, high-voltage, signal-conditioning front end, and a 4-channel differential multiplexer (mux). This
TI Precision Design details the process for optimizing the precision, high-voltage, front-end drive circuit using the
OPAx192-Q1 and OPA140 to achieve excellent dynamic performance and linearity with the ADS8864.
1
2
Very Low Output Impedance
Input-Filter Bandwidth
OPAx192-Q1
±20-V,
10-kHz
Sine Wave
3
High-Impedance Inputs
No Differential Input Clamps
Fast Settling-Time Requirements
Attenuate High-Voltage Input Signal
Fast-Settling Time Requirements
Stability of the Input Driver
4
Attenuate ADC Kickback Noise
VREF Output: Value and Accuracy
Low Temp and Long-Term Drift
Voltage
Reference
CH0+
+
RC Filter
Buffer
RC Filter
Reference Driver
+
OPAx192-Q1
CH0-
Gain
Network
OPAx192-Q1
Gain
Network
+
4:2
Mux
REFP
+
OPAx192-Q1
CH3+
OPAx192-Q1
+
+
Antialiasing
Filter
SAR
ADC
+
VINM
OPAx192-Q1
CH3-
n
16 Bits
400 kSPS
High-Voltage Level Translation
VCM
High-Voltage Multiplexed Input
CONV
Gain
Network
±20-V,
10-kHz
Sine Wave
VINP
OPAx192-Q1
Gain
Network
REF3240
Voltage
Divider
OPA350
VCM Generation Circuit
Counter
n
Shmidtt
Trigger
Delay
Digital Counter For Multiplexer
5
Fast logic transition
Copyright © 2017, Texas Instruments Incorporated
Figure 61. OPAx192-Q1 in 16-Bit, 400-kSPS, 4-Channel, Multiplexed Data Acquisition System for HighVoltage Inputs With Lowest Distortion
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Typical Applications (continued)
9.2.1.1 Design Requirements
The primary objective is to design a ±20 V, differential 4-channel multiplexed data acquisition system with lowest
distortion using the 16-bit ADS8864 at a throughput of 400 kSPS for a 10 kHz full-scale pure sine-wave input.
The design requirements for this block design are:
• System Supply Voltage: ±15 V
• ADC Supply Voltage: 3.3 V
• ADC Sampling Rate: 400 kSPS
• ADC Reference Voltage (REFP): 4.096 V
• System Input Signal: A high-voltage differential input signal with a peak amplitude of 10 V and frequency
(fIN) of 10 kHz are applied to each differential input of the mux.
9.2.1.2 Detailed Design Procedure
The purpose of this precision design is to design an optimal high voltage multiplexed data acquisition system for
highest system linearity and fast settling. The overall system block diagram is illustrated in Figure 61. The circuit
is a multichannel data acquisition signal chain consisting of an input low-pass filter, multiplexer (mux), mux output
buffer, attenuating SAR ADC driver, digital counter for mux and the reference driver. The architecture allows fast
sampling of multiple channels using a single ADC, providing a low-cost solution. The two primary design
considerations to maximize the performance of a precision multiplexed data acquisition system are the mux input
analog front-end and the high-voltage level translation SAR ADC driver design. However, carefully design each
analog circuit block based on the ADC performance specifications in order to achieve the fastest settling at 16-bit
resolution and lowest distortion system. The diagram includes the most important specifications for each
individual analog block.
This design systematically approaches each analog circuit block to achieve a 16-bit settling for a full-scale input
stage voltage and linearity for a 10-kHz sinusoidal input signal at each input channel. The first step in the design
is to understand the requirement for extremely low impedance input-filter design for the mux. This understanding
helps in the decision of an appropriate input filter and selection of a mux to meet the system settling
requirements. The next important step is the design of the attenuating analog front-end (AFE) used to level
translate the high-voltage input signal to a low-voltage ADC input when maintaining amplifier stability. The next
step is to design a digital interface to switch the mux input channels with minimum delay. The final design
challenge is to design a high-precision, reference-driver circuit that provides the required REFP reference voltage
with low offset, drift, and noise contributions.
9.2.1.3 Application Curve
Integral Nonlinearity Error (LSB)
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–20
–15
–10
–5
0
5
10
15
20
ADC Differential Input (V)
Figure 62. ADC 16-Bit Linearity Error for the Multiplexed Data Acquisition Block
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, refer to TI Precision Design TIDU181, 16-bit, 400-kSPS, 4-Channel, Multiplexed Data Acquisition
System for High Voltage Inputs with Lowest Distortion.
30
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9.2.2 Slew Rate Limit for Input Protection
In control systems for valves or motors, abrupt changes in voltages or currents can cause mechanical damages.
By controlling the slew rate of the command voltages into the drive circuits, the load voltages ramps up and down
at a safe rate. For symmetrical slew-rate applications (positive slew rate equals negative slew rate), one
additional op amp provides slew-rate control for a given analog gain stage. The unique input protection and high
output current and slew rate of the OPAx192-Q1 make the device an optimal amplifier to achieve slew rate
control for both dual- and single-supply systems.Figure 63 shows the OPAx192-Q1 in a slew-rate limit design.
Op Amp Gain Stage
Slew Rate Limiter
C1
470 nF
R1
1.69 kΩ
VEE
VEE
R2
1.6 MΩ
+
VIN
-
OPAx192-Q1
+ V+
VOUT
OPAx192-Q1
+ V+
VCC
RL
10 kΩ
VCC
Copyright © 2017, Texas Instruments Incorporated
Figure 63. Slew Rate Limiter Uses One Op Amp
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, see TI Precision Design TIDU026, Slew Rate Limiter Uses One Op Amp.
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9.2.3 Precision Reference Buffer
The OPAx192-Q1 features high output current drive capability and low input offset voltage, making the device an
excellent reference buffer to provide an accurate buffered output with ample drive current for transients. For the
10-µF ceramic capacitor shown in Figure 64, RISO, a 37.4-Ω isolation resistor, provides separation of two
feedback paths for optimal stability. Feedback path number one is through RF and is directly at the output (VOUT).
Feedback path number two is through RFx and CF and is connected at the output of the op amp. The optimized
stability components shown for the 10-µF load give a closed-loop signal bandwidth at VOUT of 4 kHz and still
provides a loop gain phase margin of 89°. Any other load capacitances require recalculation of the stability
components: RF, RFx , CF , and RISO.
RF
1 kŸ
RFx
10 kŸ
CF
39 nF
RISO
37.4 Ÿ
VOUT
OPAx192-Q1
V+
CL
10 µF
VREF
2.5 V
VCC
Copyright © 2017, Texas Instruments Incorporated
Figure 64. Precision Reference Buffer
32
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10 Power-Supply Recommendations
The OPAx192-Q1 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply
from –40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in Typical Characteristics.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see Absolute
Maximum Ratings.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see Layout.
11 Layout
11.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically
separate digital and analog grounds paying attention to the flow of the ground current. .
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much
better as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As illustrated in Figure 66, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit may experience performance shifts due to moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, TI recommends baking the PCB
assemblyto remove moisture introduced into the device packaging during the cleaning process. A low
temperature, post cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
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11.2 Layout Example
+
VIN
VOUT
RG
RF
Figure 65. Schematic Representation
Run the input traces
as far away from
the supply lines
as possible
Place components close
to device and to each
other to reduce parasitic
errors
RF
VS+
N/C
N/C
GND
±IN
V+
VIN
+IN
OUTPUT
V±
N/C
RG
GND
GND
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitors
Copyright © 2017, Texas Instruments Incorporated
Figure 66. Operational Amplifier Board Layout for Noninverting Configuration
34
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
12.1.1.2 TI Precision Designs
The OPA192 is featured in several Texas Instruments (TI) Precision Designs, available online at
http://www.ti.com/ww/en/analog/precision-designs/. TI Precision Designs are analog solutions created by TI’s
precision analog applications experts and offer the theory of operation, component selection, simulation,
complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits.
12.2 Related Links
Table 4 lists quick access links. Categories include technical documents, support and community resources,
tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
OPA192-Q1
Click here
Click here
Click here
Click here
Click here
OPA2192-Q1
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: OPA192-Q1 OPA2192-Q1
35
OPA192-Q1, OPA2192-Q1
SBOS850 – DECEMBER 2017
www.ti.com
12.5 Trademarks
e-trim, E2E are trademarks of Texas Instruments.
TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
e-trim, are trademarks of ~ Texas Instruments.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
36
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: OPA192-Q1 OPA2192-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA192QDGKRQ1
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
192
OPA2192QDGKRQ1
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
2192
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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