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OPA170-Q1, OPA2170-Q1, OPA4170-Q1
SBOS834B – DECEMBER 2016 – REVISED NOVEMBER 2017
OPAx170-Q1 36-V, Single-Supply, Low-Power, Automotive-Grade Operational Amplifiers
1 Features
3 Description
•
•
The OPA170-Q1, OPA2170-Q1, and OPA4170-Q1
devices (OPAx170-Q1) are a family of 36-V, singlesupply, low-noise operational amplifiers that feature
micro packages with the ability to operate on supplies
ranging from 2.7 V (±1.35 V) to 36 V (±18 V). They
offer good offset, drift, and bandwidth with low
quiescent current.
1
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Qualified With the Following Results:
– Device Temperature Grade 1: –40°C to
+125°C Ambient Operating Temperature
– Device HBM ESD Classification Level 3A
– Device CDM ESD Classification Level C5
Supply Range: 2.7 V to 36 V, ±1.35 V to ±18 V
Low Noise: 19 nV/√Hz
RFI Filtered Inputs
Input Range Includes the Negative Supply
Input Range Operates to Positive Supply
Rail-to-Rail Output
Gain Bandwidth: 1.2 MHz
Low Quiescent Current: 110 µA per Amplifier
High Common-Mode Rejection: 120 dB
Low Bias Current: 15 pA (Maximum)
Number of Channels:
– OPA170-Q1: 1
– OPA2170-Q1: 2
– OPA4170-Q1: 4
Industry-Standard Packages
Unlike most operational amplifiers, which are
specified at only one supply voltage, the OPAx170Q1 family of operational amplifiers is specified from
2.7 V to 36 V. Input signals beyond the supply rails
do not cause phase reversal. The OPAx170-Q1
family is stable with capacitive loads up to 300 pF.
The input can operate 100 mV below the negative rail
and within 2 V of the positive rail for normal
operation. Note that these devices can operate with
full rail-to-rail input 100 mV beyond the positive rail,
but with reduced performance within 2 V of the
positive rail. The OPAx170-Q1 operational amplifiers
are specified from –40°C to +125°C.
Device Information(1)
PART NUMBER
BODY SIZE (NOM)
SOT-23 (5)
2.90 mm × 1.60 mm
OPA2170-Q1
VSSOP (8)
3.00 mm × 3.00 mm
OPA4170-Q1
TSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
•
•
•
PACKAGE
OPA170-Q1
Automotive
HEV and EV Power Trains
Advanced Driver Assist (ADAS)
Automatic Climate Controls
Temperature Measurements
Strain Gauge Amplifiers
Precision Integrators
EMIRR IN+ vs Frequency
140
EMIRR IN+ (dB)
120
100
80
60
40
PRP = -10 dBm
VS = ±18 V
VCM = 0 V
20
0
10 M
100 M
1G
10 G
Frequency (Hz)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA170-Q1, OPA2170-Q1, OPA4170-Q1
SBOS834B – DECEMBER 2016 – REVISED NOVEMBER 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
7
1
1
1
2
3
6
Absolute Maximum Ratings ...................................... 6
ESD Ratings ............................................................ 6
Recommended Operating Conditions....................... 6
Thermal Information: OPA170-Q1 ............................ 7
Thermal Information: OPA2170-Q1 .......................... 7
Thermal Information: OPA4170-Q1 .......................... 7
Electrical Characteristics........................................... 8
Typical Characteristics: Table of Graphs ................ 10
Typical Characteristics ............................................ 11
Detailed Description ............................................ 17
7.1 Overview ................................................................. 17
7.2 Functional Block Diagram ...................................... 17
7.3 Feature Description................................................. 17
7.4 Device Functional Modes........................................ 21
8
Application and Implementation ........................ 22
8.1 Application Information............................................ 22
8.2 Typical Application .................................................. 22
9 Power Supply Recommendations...................... 24
10 Layout................................................................... 24
10.1 Layout Guidelines ................................................. 24
10.2 Layout Example .................................................... 25
11 Device and Documentation Support ................. 26
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
27
27
27
27
27
27
12 Mechanical, Packaging, and Orderable
Information ........................................................... 28
4 Revision History
Changes from Revision A (March 2017) to Revision B
Page
•
Deleted 8-pin SOIC, 5-pin SOT, 8-pin VSSOP, and 14-pin SOIC packages from Device Information table......................... 1
•
Changed front-page graphic .................................................................................................................................................. 1
•
Deleted OPA170-Q1 D (SOIC) and DRL (SOT) pinout drawings and pinout table information............................................. 3
•
Deleted OPA2170-Q1 D (SOIC) and DCU (VSSOP Micro size packages ............................................................................ 4
•
Deleted OPA170-Q1 D (SOIC) pinout drawing ...................................................................................................................... 5
•
Deleted D (SOIC) and DRL (SOT) thermal information from OPA170-Q1 Thermal Information table ................................. 7
•
Deleted D (SOIC) and DCU (VSSOP) thermal information from OPA2170-Q1 Thermal Information table ......................... 7
•
Deleted D (SOIC) thermal information from OPA4170-Q1 Thermal Information table ......................................................... 7
•
Changed values in Figure 38 from 250 Ω to 2.5 kΩ ............................................................................................................ 19
Changes from Original (December 2016) to Revision A
Page
•
Deleted last sentence of first para of Description .................................................................................................................. 1
•
Deleted static literature number in Thermal Information: OPA170-Q1 table note ................................................................. 7
•
Separated the IB and IOS test conditions for the OPA4170 in Electrical Characteristics table............................................. 8
•
Added additional text to Figure 8 title .................................................................................................................................. 12
•
Changed "many specifications apply from –40°C to +125°C" to "many specifications apply from –40°C to +85°C" to
correct typo ........................................................................................................................................................................... 24
2
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SBOS834B – DECEMBER 2016 – REVISED NOVEMBER 2017
5 Pin Configuration and Functions
OPA170-Q1 DBV Package
5-Pin SOT-23
Top View
OUT
1
V-
2
+IN
3
5
V+
4
-IN
Table 1. Pin Functions: OPA170-Q1
PIN
NAME
NO.
IN– (–IN)
4
IN+ (+IN)
OUT
I/O
DESCRIPTION
I
Negative (inverting) input
3
I
Positive (noninverting) input
1
O
Output
V–
2
—
Negative (lowest) power supply
V+
5
—
Positive (highest) power supply
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3
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SBOS834B – DECEMBER 2016 – REVISED NOVEMBER 2017
www.ti.com
OPA2170-Q1 DGK Package
8-Pin VSSOP
Top View
OUT A
1
8
V+
-IN A
2
7
OUT B
+IN A
3
6
-IN B
V-
4
5
+IN B
Table 2. Pin Functions: OPA2170-Q1
PIN
I/O
DESCRIPTION
NAME
NO.
–IN A
2
I
Inverting input, channel A
–IN B
6
I
Inverting input, channel B
+IN A
3
I
Noninverting input, channel A
+IN B
5
I
Noninverting input, channel B
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
V–
4
—
Negative (lowest) power supply
V+
8
—
Positive (highest) power supply
4
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SBOS834B – DECEMBER 2016 – REVISED NOVEMBER 2017
OPA4170-Q1 PW Package
14-Pin TSSOP
Top View
OUT A
1
14
OUT D
-IN A
2
13
-IN D
+IN A
3
12
+IN D
V+
4
11
V-
+IN B
5
10
+IN C
-IN B
6
9
-IN C
OUT B
7
8
OUT C
Table 3. Pin Functions: OPA4170-Q1
PIN
I/O
DESCRIPTION
NAME
NO.
–IN A
2
I
Inverting input, channel A
–IN B
6
I
Inverting input, channel B
–IN C
9
I
Inverting input, channel C
–IN D
13
I
Inverting input, channel D
+IN A
3
I
Noninverting input, channel A
+IN B
5
I
Noninverting input, channel B
+IN C
10
I
Noninverting input, channel C
+IN D
12
I
Noninverting input, channel D
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
OUT C
8
O
Output, channel C
OUT D
14
O
Output, channel D
V–
11
—
Negative (lowest) power supply
V+
4
—
Positive (highest) power supply
Copyright © 2016–2017, Texas Instruments Incorporated
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SBOS834B – DECEMBER 2016 – REVISED NOVEMBER 2017
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
–20
20
V
40
V
Signal input pin voltage
(V–) – 0.5
(V+) + 0.5
V
Signal input pin current
–10
10
mA
150
°C
150
°C
150
°C
Supply voltage
Single supply voltage
Output short-circuit current (2)
Continuous
Operating ambient temperature, TA
–55
Junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002 (1)
±4000
Charged-device model (CDM), per AEC Q100-011
±750
UNIT
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VS
Supply voltage (V+ – V–)
2.7
36
V
TA
Operating temperature
–40
125
°C
6
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UNIT
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SBOS834B – DECEMBER 2016 – REVISED NOVEMBER 2017
6.4 Thermal Information: OPA170-Q1
OPA170-Q1
THERMAL METRIC (1)
DBV (SOT-23)
UNIT
5 PINS
RθJA
Junction-to-ambient thermal resistance
245.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
133.9
°C/W
RθJB
Junction-to-board thermal resistance
83.6
°C/W
ψJT
Junction-to-top characterization parameter
18.2
°C/W
ψJB
Junction-to-board characterization parameter
83.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Thermal Information: OPA2170-Q1
OPA2170-Q1
THERMAL METRIC (1)
DGK (VSSOP)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
180
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
55
°C/W
RθJB
Junction-to-board thermal resistance
130
°C/W
ψJT
Junction-to-top characterization parameter
5.3
°C/W
ψJB
Junction-to-board characterization parameter
120
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Thermal Information: OPA4170-Q1
OPA4170-Q1
THERMAL METRIC
(1)
PW (TSSOP)
UNIT
14 PINS
RθJA
Junction-to-ambient thermal resistance
106.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
24.4
°C/W
RθJB
Junction-to-board thermal resistance
59.3
°C/W
ψJT
Junction-to-top characterization parameter
0.6
°C/W
ψJB
Junction-to-board characterization parameter
54.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
Copyright © 2016–2017, Texas Instruments Incorporated
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SBOS834B – DECEMBER 2016 – REVISED NOVEMBER 2017
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6.7 Electrical Characteristics
at TA = 25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.25
±1.8
mV
OFFSET VOLTAGE
TA = 25°C
VOS
Input offset voltage
dVOS/dT
Input offset voltage drift
TA = –40°C to 125°C
PSRR
Input offset voltage vs power
supply
VS = 4 V to 36 V
TA = –40°C to 125°C
TA = –40°C to 125°C
Channel separation, dc
±2
mV
±0.3
±2
µV/°C
1
±5
µV/V
5
µV/V
INPUT BIAS CURRENT
TA = 25°C
IB
Input bias current
±8
±3.5
TA = –40°C to 125°C (OPA4170-Q1)
±16
TA = 25°C
IOS
Input offset current
±15
TA = –40°C to 125°C (OPA170-Q1 and
OPA2170-Q1)
±4
±15
TA = –40°C to 125°C (OPA170-Q1 and
OPA2170-Q1)
±3.5
TA = –40°C to 125°C (OPA4170-Q1)
±16
pA
nA
pA
nA
NOISE
Input voltage noise
en
ƒ = 0.1 Hz to 10 Hz
Input voltage noise density
2
µVPP
ƒ = 100 Hz
22
nV/√Hz
ƒ = 1 kHz
19
nV/√Hz
INPUT VOLTAGE
Common-mode voltage range (1)
VCM
CMRR
Common-mode rejection ratio
(V–) – 0.1
(V+) – 2
V
VS = ±2 V, (V–) – 0.1 V < VCM < (V+) – 2 V
TA = –40°C to 125°C
90
104
dB
VS = ±18 V, (V–) – 0.1 V < VCM < (V+) – 2
V
TA = –40°C to 125°C
104
120
dB
INPUT IMPEDANCE
Differential
Common-mode
100 || 3
MΩ || pF
6 || 3
1012 Ω ||
pF
130
dB
OPEN-LOOP GAIN
VS = 4 V to 36 V
(V–) + 0.35 V < VO < (V+) – 0.35 V
TA = –40°C to 125°C
AOL Open-loop voltage gain
110
FREQUENCY RESPONSE
GBP
Gain bandwidth product
SR
Slew rate
tS
THD+N
(1)
8
1.2
MHz
G=1
0.4
V/µs
To 0.1%, VS = ±18 V, G = 1 10-V step
20
µs
Settling time
To 0.01% (12-bit), VS = ±18 V, G = 1
10-V step
28
µs
Overload recovery time
VIN × Gain > VS
2
µs
Total harmonic distortion + noise
G = 1, ƒ = 1 kHz, VO = 3 VRMS
0.0002%
The input range can be extended beyond (V+) – 2 V up to V+. For additional information, see Typical Characteristics and Application
and Implementation.
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SBOS834B – DECEMBER 2016 – REVISED NOVEMBER 2017
Electrical Characteristics (continued)
at TA = 25°C, VCM = VOUT = VS / 2, and RL = 10 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
VO
VO
VO
Voltage output swing from
positive rail
Voltage output swing from
negative rail
Voltage output swing from rail
ISC
Short-circuit current
CLOAD
Capacitive load drive
RO
IL = 0 mA
VS = 4 V to 36 V
10
mV
IL sourcing 1 mA
VS = 4 V to 36 V
115
mV
IL = 0 mA
VS = 4 V to 36 V
8
mV
IL sinking 1 mA
VS = 4 V to 36 V
70
mV
VS = 5 V
RL = 10 kΩ
TA = –40°C to 125°C
(V–) + 0.03
(V+) –
0.05
V
RL = 10 kΩ
AOL ≥ 110 dB
TA = –40°C to 125°C
(V–) + 0.35
(V+) –
0.35
V
–20
17
See Typical Characteristics
Open-loop output resistance
ƒ = 1 MHz
IO = 0 A
mA
pF
900
Ω
POWER SUPPLY
VS
IQ
Specified voltage range
2.7
Quiescent current per amplifier
IO = 0 A
TA = 25°C
110
IO = 0 A
TA = –40°C to 125°C
36
V
145
µA
155
µA
TEMPERATURE
Specified range
–40
125
°C
Operating range
–55
150
°C
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6.8 Typical Characteristics: Table of Graphs
Table 4. Characteristic Performance Measurements
DESCRIPTION
FIGURE
Offset Voltage Production Distribution
Figure 1
Offset Voltage Drift Distribution
Figure 2
Offset Voltage vs Temperature
Figure 3
Offset Voltage vs Common-Mode Voltage
Figure 4
Offset Voltage vs Common-Mode Voltage (Upper Stage)
Figure 5
Offset Voltage vs Power Supply
Figure 6
IB and IOS vs Common-Mode Voltage
Figure 7
Input Bias Current vs Temperature
Figure 8
Output Voltage Swing vs Output Current (Maximum Supply)
Figure 9
CMRR and PSRR vs Frequency (Referred-to-Input)
Figure 10
CMRR vs Temperature
Figure 11
PSRR vs Temperature
Figure 12
0.1-Hz to 10-Hz Noise
Figure 13
Input Voltage Noise Spectral Density vs Frequency
Figure 14
THD+N Ratio vs Frequency
Figure 15
THD+N vs Output Amplitude
Figure 16
Quiescent Current vs Temperature
Figure 17
Quiescent Current vs Supply Voltage
Figure 18
Open-Loop Gain and Phase vs Frequency
Figure 19
Closed-Loop Gain vs Frequency
Figure 20
Open-Loop Gain vs Temperature
Figure 21
Open-Loop Output Impedance vs Frequency
Figure 22
Small-Signal Overshoot vs Capacitive Load (100-mV Output Step)
Figure 23, Figure 24
No Phase Reversal
Figure 25
Positive Overload Recovery
Figure 26
Negative Overload Recovery
Figure 27
Small-Signal Step Response (100 mV)
Figure 28, Figure 29
Large-Signal Step Response
Figure 30, Figure 31
Large-Signal Settling Time (10-V Positive Step)
Figure 32
Large-Signal Settling Time (10-V Negative Step)
Figure 33
Short-Circuit Current vs Temperature
Figure 34
Maximum Output Voltage vs Frequency
Figure 35
EMIRR IN+ vs Frequency
Figure 36
10
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SBOS834B – DECEMBER 2016 – REVISED NOVEMBER 2017
6.9 Typical Characteristics
VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
20
25
Distribution Taken From 400 Amplifiers
Distribution Taken From 104 Amplifiers
Percentage of Amplifiers (%)
Percentage of Amplifiers (%)
18
16
14
12
10
8
6
4
20
15
10
5
2
0
Offset Voltage (mV)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
−1200
−1100
−1000
−900
−800
−700
−600
−500
−400
−300
−200
−100
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
0
Offset Voltage Drift (mV/°C)
G001
Figure 1. Offset Voltage Production Distribution
G002
Figure 2. Offset Voltage Drift Distribution
1000
800
5 Typical Units Shown
Offset Voltage (mV)
Offset Voltage (µV)
600
400
200
0
−200
−400
VCM = -18.1 V
−600
−800
−1000
−50
−25
0
25
50
75
Temperature (°C)
100
125
150
Common-Mode Voltage (V)
G003
Figure 3. Offset Voltage vs Temperature
Figure 4. Offset Voltage vs Common-Mode Voltage
500
5 Typical Units Shown
Offset Voltage (PV)
Offset Voltage (mV)
300
Normal
Operation
100
-100
-300
Common-Mode Voltage (V)
Figure 5. Offset Voltage vs Common-Mode Voltage
(Upper Stage)
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-500
0
2
4
6
8
10
12
VSUPPLY (V)
14
16
18
20
D006
Figure 6. Offset Voltage vs Power Supply
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12
2000
IB+
IB-
1500
+IB
IOS
Input Bias Current (pA)
IB and IOS (pA)
10
8
6
IOS
4
-IB
1000
500
0
-500
2
VCM = 16.1 V
VCM = -18.1 V
-1000
0
-20
-15
-10
0
-5
5
10
15
-75
20
-50
0
-25
Common-Mode Rejection Ratio (dB),
Power-Supply Rejection Ratio (dB)
17
Output Voltage (V)
75
100
125
150
140
18
16
15
14.5
-14.5
-15
-40°C
+25°C
+125°C
-16
-17
120
100
80
60
40
+PSRR
-PSRR
CMRR
20
0
-18
0
1
2
3
4
5
6
7
8
9
1
10
10
100
1k
100k
10k
1M
Frequency (Hz)
Output Current (mA)
Figure 9. Output Voltage Swing vs Output Current
(Maximum Supply)
Figure 10. CMRR and PSRR vs Frequency
(Referred to Input)
30
3
VS = ±1.35 V
VS = ±2 V
25
VS = ±18 V
20
15
10
5
0
-75
-50
-25
0
25
50
75
100
Temperature (°C)
Figure 11. CMRR vs Temperature
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125
150
Power-Supply Rejection Ratio (PV/V)
Common-Mode Rejection Ratio (mV/V)
50
Figure 8. Input Bias Current vs Temperature for Single and
Dual Versions
Figure 7. IB and IOS vs Common-Mode Voltage
12
25
Temperature (°C)
VCM (V)
VS = 2.7 V to 36 V
VS = 4 V to 36 V
2
1
0
-1
-2
-3
-75
-50
-25
0
25
50
75
Temperature (qC)
100
125
150
D012
Figure 12. PSRR vs Temperature
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1 mV/div
Voltage Noise Density (nV/ Hz)
1000
100
10
1
Time (1 s/div)
Figure 13. 0.1-Hz to 10-Hz Noise
-120
0.0001
1k
-140
100 k
10 k
1k
10k
Frequency (Hz)
0.1
Total Harmonic Distortion + Noise (%)
Total Harmonic Distortion + Noise (%)
-100
0.001
100
100
100k
1M
G014
BW = 80 kHz
G = +1
RL = 10 kW
-60
0.01
-80
0.001
-100
0.0001
-120
0.00001
0.01
Frequency (Hz)
0.1
1
10
Total Harmonic Distortion + Noise (dB)
-80
VOUT = 3 VRMS
BW = 80 kHz
G = +1
RL = 10 kW
0.00001
10
10
Figure 14. Input Voltage Noise Spectral Density vs
Frequency
Total Harmonic Distortion + Noise (dB)
0.01
1
-140
20
Output Amplitude (VRMS)
Figure 15. THD + N Ratio vs Frequency
Figure 16. THD + N vs Output Amplitude
140
130
120
IQ (mA)
IQ (μA)
110
VS = ±18 V
100
90
80
VS = ±1.35 V
70
Specified Supply-Voltage Range
60
-50
-25
0
25
50
75
Temperature (°C)
100
125
150
Figure 17. Quiescent Current vs Temperature
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D017
Figure 18. Quiescent Current vs Supply Voltage
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140
135
120
90
Gain
100
40
45
30
0
-45
Phase (°)
Phase
60
Gain (dB)
80
Gain (dB)
50
20
40
-90
20
-135
0
-180
-20
-225
−10
-270
10M
−20
-40
0.1
1
10
100
1k
10k
100k
1M
10
0
G = −1
G=1
G = 100
1k
10k
100k
1M
Frequency (Hz)
Frequency (Hz)
Figure 19. Open-Loop Gain and Phase vs Frequency
10M
100M
G020
Figure 20. Closed-Loop Gain vs Frequency
3
10 k
VS = 2.7 V
VS = 4 V
2.5
1k
VS = 36 V
ZO (W)
AOL (mV/V)
2
1.5
100
10
1
1
0.5
0
1m
-75
-50
-25
0
25
50
75
100
125
150
1
10
100
Temperature (°C)
1k
10 k
100 k
1M
10 M
Frequency (Hz)
Figure 21. Open-Loop Gain vs Temperature
Ω
Figure 22. Open-Loop Output Impedance vs Frequency
RL = 10 kW
G = +1
+18 V
RI = 10 kW
RF = 10 kW
G = -1
ROUT
+18 V
OPAx170-Q1
Ω
Ω
Ω
-18 V
RL
100-mV output step
Figure 23. Small-Signal Overshoot vs Capacitive Load
14
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Ω
Ω
Ω
CL
ROUT
OPAx170-Q1
CL
-18 V
100-mV output step
Figure 24. Small-Signal Overshoot vs Capacitive Load
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+18 V
OPAx170-Q1
20 kΩ
5 V/div
5 V/div
-18 V
37 VPP
Sine Wave
(±18.5 V)
+18 V
2 kΩ
OPAx170-Q1
VOUT
VIN
-18 V
G = -10
Time (100 μs/div)
Time (10 μs/div)
Figure 25. No Phase Reversal
Figure 26. Positive Overload Recovery
20 kΩ
RL = 10 kΩ
CL = 10 pF
+18 V
2 kΩ
OPAx170-Q1
VOUT
VIN
5 V/div
G = -10
20 mV/div
-18 V
+18 V
OPAx170-Q1
-18 V
Time (10 μs/div)
RL
CL
Time (5 μs/div)
Figure 27. Negative Overload Recovery
Figure 28. Small-Signal Step Response (100-mV)
G = +1
RL = 10 kΩ
CL = 10 pF
RI
= 2 kΩ
RF
2 V/div
RL = 10 kΩ
CL = 10 pF
20 mV/div
G = +1
= 2 kΩ
+18 V
OPAx170-Q1
CL
-18 V
G = -1
Time (5 μs/div)
Figure 29. Small-Signal Step Response (100-mV)
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Time (50 μs/div)
Figure 30. Large-Signal Step Response
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10
G = -1
RL = 10 kΩ
CL = 10 pF
2 V/div
D From Final Value (mV)
8
6
4
12-Bit Settling
2
0
-2
(±1/2LSB = ±0.012%)
-4
-6
-8
-10
0
Time (50 μs/div)
10
20
30
40
50
60
70
80
90
100
Time (ms)
10-V positive step
Figure 31. Large-Signal Step Response
10
G = -1
8
6
4
12-Bit Settling
2
0
-2
(±1/2LSB = ±0.012%)
-4
-6
-10
10
20
30
40
50
5
0
−5
−10
−15
−20
−25
−30
−50
-8
0
ISC, Source
ISC, Sink
20
15
10
ISC (mA)
D From Final Value (mV)
Figure 32. Large-Signal Settling Time
30
25
60
Time (ms)
−25
0
25
50
75
Temperature (°C)
100
125
150
G034
10-V negative step
10-V negative step
Figure 34. Short-Circuit Current vs Temperature
Figure 33. Large-Signal Settling Time
15
140
VS = ±15 V
120
Maximum output range without
slew−rate induced distortion
10
EMIRR IN+ (dB)
Output Voltage (VPP )
12.5
7.5
VS = ±5 V
5
2.5
0
10k
100k
Frequency (Hz)
1M
10M
Figure 35. Maximum Output Voltage vs Frequency
16
80
60
40
PRP = -10 dBm
VS = ±18 V
VCM = 0 V
20
VS = ±1.35 V
1k
100
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G035
0
10 M
100 M
1G
10 G
Frequency (Hz)
Figure 36. EMIRR IN+ vs Frequency
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7 Detailed Description
7.1 Overview
The OPAx170-Q1 family of operational amplifiers provides high overall performance, making them ideal for many
general-purpose applications. The excellent offset drift of only 2 μV/°C provides excellent stability over the entire
temperature range. In addition, the device offers very good overall performance with high CMRR, PSRR, and
AOL.
7.2 Functional Block Diagram
PCH
FF Stage
Ca
Cb
+IN
PCH
Input Stage
Output
Stage
2nd Stage
OUT
-IN
NCH
Input Stage
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7.3 Feature Description
7.3.1 Operating Characteristics
The OPAx170-Q1 family of amplifiers is specified for operation from 2.7 V to 36 V (±1.35 V to ±18 V). Many of
the specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to
operating voltage or temperature are listed in Table 4.
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Feature Description (continued)
7.3.2 Phase-Reversal Protection
The OPAx170-Q1 family has an internal phase-reversal protection. Many operational amplifiers exhibit a phase
reversal when the input is driven beyond the linear common-mode range. This condition is most often
encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range,
causing the output to reverse into the opposite rail. The input of the OPAx170-Q1 prevents phase reversal with
excessive common-mode voltage. Instead, the output limits into the appropriate rail. Figure 37 shows this
performance.
+18 V
OPAx170-Q1
5 V/div
-18 V
37 VPP
Sine Wave
(±18.5 V)
Time (100 μs/div)
Figure 37. No Phase Reversal
7.3.3 Electrical Overstress
Designers typically ask questions about the capability of an operational amplifier to withstand electrical
overstress. These questions typically focus on the device inputs, but may involve the supply voltage pins or the
output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Internal electrostatic discharge (ESD) protection is built into these circuits to protect them from accidental ESD
events both before and during product assembly.
A good understanding of basic ESD circuitry and the relevance of the circuitry to an electrical overstress event is
helpful. Figure 38 shows the ESD circuits (indicated by the dashed line area) in the OPAx170-Q1. The ESD
protection circuitry involves several current-steering diodes connected from the input and output pins and routed
back to the internal power-supply lines, where the diodes meet at an absorption device internal to the operational
amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.
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Feature Description (continued)
TVS
+
±
RF
+VS
R1
IN±
2.5 NŸ
RS
IN+
2.5 NŸ
+
Power-Supply
ESD Cell
ID
VIN
RL
+
±
+
±
±VS
TVS
Figure 38. Equivalent Internal ESD Circuitry Relative to a Typical Circuit Application
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, highcurrent pulse when discharging through a semiconductor device. The ESD protection circuits are designed to
provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the
protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or more
steering diodes. The absorption device can activate depending on the path of the current. The absorption device
has a trigger (or threshold voltage) that is above the normal operating voltage of the OPAx170-Q1, but below the
device breakdown voltage level. When this threshold is exceeded, the absorption device quickly activates and
clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit (see Figure 38), the ESD protection components are
intended to remain inactive and do not become involved in the application circuit operation. However,
circumstances may arise where an applied voltage exceeds the operating voltage range of a given pin. If this
condition occurs, there is a risk that some internal ESD protection circuits can turn on and conduct current. Any
such current flow occurs through steering-diode paths and rarely involves the absorption device.
Figure 38 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (V+) by
500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If V+ can sink the
current, one of the upper input steering diodes conducts and directs current to V+. Excessively high current
levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that
applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN can begin sourcing current to the operational amplifier and
then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to
levels that exceed the operational amplifier absolute maximum ratings.
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Feature Description (continued)
Another common question involves what happens to the amplifier if an input signal is applied to the input when
the power supplies (V+ or V–) are at 0 V. Again, this question depends on the supply characteristic when at 0 V,
or at a level below the input signal amplitude. If the supplies appear as high impedance, then the input source
supplies the operational amplifier current through the current-steering diodes. This state is not a normal bias
condition; most likely, the amplifier does not operate normally. If the supplies are low impedance, then the current
through the steering diodes can become quite high. The current level depends on the ability of the input source
to deliver current, and any resistance in the input path.
If there is any uncertainty about the ability of the supply to absorb this current, add external Zener diodes to the
supply pins; see Figure 38. Select the Zener voltage so that the diode does not turn on during normal operation.
However, the Zener voltage must be low enough so that the Zener diode conducts if the supply pin begins to rise
above the safe-operating, supply-voltage level.
The OPAx170-Q1 input pins are protected from excessive differential voltage with back-to-back diodes, as shown
in Figure 38. In most circuit applications, the input protection circuitry has no effect. However, in low-gain or G =
1 circuits, fast-ramping input signals can forward-bias these diodes because the output of the amplifier cannot
respond rapidly enough to the input ramp. If the input signal is fast enough to create this forward-bias condition,
limit the input signal current to 10 mA or less. If the input signal current is not inherently limited, an input series
resistor can limit the input signal current. This input series resistor degrades the low-noise performance of the
OPAx170-Q1. Figure 38 is an example configuration that implements a current-limiting feedback resistor.
7.3.4 Capacitive Load and Stability
The dynamic characteristics of the OPAx170-Q1 are optimized for common operating conditions. The
combination of low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier and
can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated from the output.
The simplest way to achieve this isolation is to add a small resistor (for example, ROUT equal to 50 Ω) in series
with the output. Figure 39 and Figure 40 are graphs showing small-signal overshoot versus capacitive load for
several values of ROUT. See Feedback Plots Define Op Amp AC Performance for details of analysis techniques
and application circuits.
Ω
RL = 10 kW
G = +1
+18 V
RI = 10 kW
RF = 10 kW
G = -1
ROUT
+18 V
OPAx170-Q1
Ω
Ω
Ω
100-mV output step
-18 V
RL
G=1
Figure 39. Small-Signal Overshoot vs Capacitive Load
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ROUT
Ω
Ω
Ω
CL
100-mV output step
OPAx170-Q1
CL
-18 V
G = –1
Figure 40. Small-Signal Overshoot vs Capacitive Load
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7.4 Device Functional Modes
7.4.1 Common-Mode Voltage Range
The input common-mode voltage range of the OPAx170-Q1 series extends 100 mV below the negative rail and
within 2 V of the top rail for normal operation.
This device can operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance within
2 V of the top rail. The typical performance in this range is summarized in Table 5.
Table 5. Typical Performance for Common-Mode Voltages Within 2 V of the Positive Supply
PARAMETER
Input common-mode voltage
Offset voltage
MIN
TYP
(V+) – 2
vs temperature
Common-mode rejection
MAX
(V+) + 0.1
UNIT
V
7
mV
12
µV/°C
65
dB
Open-loop gain
60
dB
Gain-bandwidth product
0.3
MHz
Slew rate
0.3
V/µs
7.4.2 Overload Recovery
Overload recovery is defined as the time required for the operational amplifier output to recover from the
saturated state to the linear state. The output devices of the operational amplifier enter the saturation region
when the output voltage exceeds the rated operating voltage, either resulting from the high input voltage or the
high gain. After the device enters the saturation region, the charge carriers in the output devices need time to
return back to the normal state. After the charge carriers return back to the equilibrium state, the device begins to
slew at the normal slew rate. Thus, the propagation delay in case of an overload condition is the sum of the
overload recovery time and the slew time. The overload recovery time for the OPAx170-Q1 is approximately 2
µs.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPAx170-Q1 family of operational amplifiers provides high overall performance in a large number of
general-purpose applications. As with all amplifiers, applications with noisy or high-impedance power supplies
require decoupling capacitors placed close to the device pins. In most cases, capacitors with a value of 0.1 µF
are adequate. Follow the additional recommendations in the Layout Guidelines section to achieve the maximum
performance from this device. Many applications may introduce capacitive loading to the output of the amplifier
that may cause instability. Adding an isolation resistor between the amplifier output and the capacitive load
stabilizes the amplifier. The design process for selecting this resistor is shown in the Typical Application section.
8.2 Typical Application
This circuit can drive capacitive loads such as cable shields, reference buffers, MOSFET gates, and diodes. The
circuit uses an isolation resistor (RISO) to stabilize the output of an operational amplifier. RISO modifies the openloop gain of the system to ensure the circuit has sufficient phase margin.
+VS
VOUT
RISO
+
VIN
+
±
CLOAD
-VS
Figure 41. Unity-Gain Buffer With RISO Stability Compensation
8.2.1 Design Requirements
The design requirements are:
• Supply voltage: 30 V (±15 V)
• Capacitive loads: 100-pF, 1000-pF, 0.01-μF, 0.1-μF, and 1-μF
• Phase margin: 45° and 60°
8.2.2 Detailed Design Procedure
Figure 41 shows a unity-gain buffer driving a capacitive load. Equation 1 shows the transfer function for the
circuit in Figure 41. Not shown in Figure 41 is the open-loop output resistance of the operational amplifier, RO.
1 + CLOAD × RISO × s
T(s) =
1 + Ro + RISO × CLOAD × s
(1)
The transfer function in Equation 1 has a pole and a zero. The frequency of the pole (fp) is determined by (RO +
RISO) and CLOAD. RISO and CLOAD determine the frequency of the zero (fz). A stable system is obtained by
selecting RISO, so the rate of closure (ROC) between the open-loop gain (AOL) and 1/β is 20 dB / decade.
Figure 42 depicts the concept. The 1/β curve for a unity-gain buffer is 0 dB.
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Typical Application (continued)
120
AOL
100
1
fp
2 u Πu RISO
Gain (dB)
80
60
Ro
u CLOAD
40 dB
fz
40
1
2 u Πu RISO u CLOAD
1 dec
1/
20
ROC
20 dB
dec
0
10
100
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Figure 42. Unity-Gain Amplifier With RISO Compensation
ROC stability analysis is typically simulated. The validity of the analysis depends on multiple factors, especially
the accurate modeling of R O . In addition to simulating the ROC, a robust stability analysis includes a
measurement of overshoot percentage and ac gain peaking of the circuit using a function generator,
oscilloscope, and gain and phase analyzer. Phase margin is then calculated from these measurements. Table 6
shows the overshoot percentage and ac gain peaking that correspond to 45° and 60° phase margins. For more
details on this design and other alternative devices that can be used in place of the OPAx170-Q1 family, see
Capacitive Load Drive Solution Using an Isolation Resistor.
Table 6. Phase Margin versus Overshoot and AC Gain
Peaking
PHASE
MARGIN
OVERSHOOT
AC GAIN PEAKING
45°
23.3%
2.35 dB
60°
8.8%
0.28 dB
8.2.3 Application Curve
Using the described methodology, the values of RISO that yield phase margins of 45º and 60º for various
capacitive loads were determined. Figure 43 shows the results.
10000
45° Phase Margin
Isolation Resistor (RISO,
)
60° Phase Margin
1000
100
10
0.1
1
10
100
Capacitive Load (nF)
1000
C002
Figure 43. Isolation Resistor Required for Various Capacitive Loads to Achieve a Target Phase Margin
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9 Power Supply Recommendations
The OPAx170-Q1 family is specified for operation from 2.7 V to 36 V (±1.35 V to ±18 V); many specifications
apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in Table 4.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings table.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see the Layout
section.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the
operational amplifier itself. Bypass capacitors are used to reduce the coupled noise by providing lowimpedance power sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close as possible to the device. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are typically devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Take care to physically
separate digital and analog grounds, paying attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away as possible from the supply or output
traces. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much
better than in parallel with the noisy trace.
• Place the external components as close as possible to the device. As shown in Figure 45, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
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10.2 Layout Example
+
VIN
VOUT
RG
RF
Figure 44. Schematic Representation of a Noninverting Configuration
Run the input traces
as far away from
the supply lines
as possible
Place components close
to device and to each
other to reduce parasitic
errors
VS+
RF
N/C
N/C
GND
±IN
V+
VIN
+IN
OUTPUT
V±
N/C
Use a low-ESR,
ceramic bypass
capacitor
RG
GND
VS±
GND
VOUT
Ground (GND) plane on another layer
Use low-ESR,
ceramic bypass
capacitor
Copyright © 2017, Texas Instruments Incorporated
Figure 45. Operational Amplifier Board Layout for a Noninverting Configuration
Copyright © 2016–2017, Texas Instruments Incorporated
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 TINA-TI™ (Free Software Download)
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI™ is
a free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a
range of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency
domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the WEBENCH® Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NOTE
These files require that either the TINA software (from DesignSoft™) or TINA-TI software
be installed. Download the free TINA-TI software from the TINA-TI folder.
11.1.1.2 DIP Adapter EVM
The DIP Adapter EVM tool provides an easy, low-cost way to prototype small surface mount devices. The
evaluation tool these TI packages: D or U (SOIC-8), PW (TSSOP-8), DGK (MSOP-8), DBV (SOT-23-6, SOT-23-5
and SOT-23-3), DCK (SC70-6 and SC70-5), and DRL (SOT563-6). The DIP Adapter EVM may also be used with
terminal strips or may be wired directly to existing circuits.
11.1.1.3 Universal Operational Amplifier EVM
The Universal Op Amp EVM is a series of general-purpose, blank circuit boards that simplify prototyping circuits
for a variety of device package types. The evaluation module board design allows many different circuits to be
constructed easily and quickly. Five models are offered, with each model intended for a specific package type.
PDIP, SOIC, MSOP, TSSOP and SOT-23 packages are all supported.
NOTE
These boards are unpopulated, so users must provide their own devices. TI recommends
requesting several op amp device samples when ordering the Universal Op Amp EVM.
11.1.1.4 TI Precision Designs
TI Precision Designs are analog solutions created by TI’s precision analog applications experts and offer the
theory of operation, component selection, simulation, complete PCB schematic and layout, bill of materials, and
measured performance of many useful circuits. TI Precision Designs are available online at
http://www.ti.com/ww/en/analog/precision-designs/.
26
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OPA170-Q1, OPA2170-Q1, OPA4170-Q1
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SBOS834B – DECEMBER 2016 – REVISED NOVEMBER 2017
Device Support (continued)
11.1.1.5 WEBENCH® Filter Designer
WEBENCH® Filter Designer is a simple, powerful, and easy-to-use active filter design program. The
WEBENCH® Filter Designer allows the user create optimized filter designs using a selection of TI operational
amplifiers and passive components from TI's vendor partners.
Available as a web-based tool from the WEBENCH® Design Center, WEBENCH® Filter Designer allows the
user to design, optimize, and simulate complete multistage active filter solutions within minutes.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following (available for download from www.ti.com):
• Feedback Plots Define Op Amp AC Performance
• Capacitive Load Drive Solution Using an Isolation Resistor
11.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 7. Related Links
PARTS
PRODUCT FOLDER
ORDER NOW
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
OPA170-Q1
Click here
Click here
Click here
Click here
Click here
OPA2170-Q1
Click here
Click here
Click here
Click here
Click here
OPA4170-Q1
Click here
Click here
Click here
Click here
Click here
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
TINA-TI, E2E are trademarks of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
TINA, DesignSoft are trademarks of DesignSoft, Inc.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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SBOS834B – DECEMBER 2016 – REVISED NOVEMBER 2017
www.ti.com
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
OPA170AQDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
170Q
OPA2170AQDGKRQ1
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
2170
OPA4170AQPWRQ1
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
4170Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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