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OPA2211-EP
SBOS761 – NOVEMBER 2015
OPA2211-EP 1.1-nV/√Hz Noise, Low-Power, Precision Operational Amplifier
1 Features
3 Description
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The OPA2211-EP series of precision operational
amplifiers achieves very-low 1.1-nV/√Hz noise density
with a supply current of only 3.6 mA. This series also
offers rail-to-rail output swing, which maximizes
dynamic range.
1
•
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•
•
•
•
Low Voltage Noise: 1.1 nV/√Hz at 1 kHz
Input Voltage Noise: 80 nVPP (0.1 to 10 Hz)
THD+N: –136 dB (G = 1, ƒ = 1 kHz)
Offset Voltage: 180 μV (Max)
Offset Voltage Drift: 0.35 μV/°C (Typ)
Low Supply Current: 3.6 mA/Ch (Typ)
Unity-Gain Stable
Gain Bandwidth Product:
80 MHz (G = 100)
45 MHz (G = 1)
Slew Rate: 27 V/μs
16-Bit Settling: 700 ns
Wide Supply Range:
±2.25 V to ±18 V, +4.5 V to +36 V
Rail-to-Rail Output
Output Current: 30 mA
Supports Defense, Aerospace, and Medical
Applications
– Controlled Baseline
– One Assembly and Test Site
– One Fabrication Site
– Available in Military (–55°C to 125°C)
Temperature Range (1)
– Extended Product Life Cycle
– Extended Product-Change Notification
– Product Traceability
The extremely low voltage and low current noise,
high speed, and wide output swing of the OPA2211EP series make these devices an excellent choice as
a loop filter amplifier in PLL applications.
In precision data acquisition applications, the
OPA2211-EP series of operational amplifiers
provides 700-ns settling time to 16-bit accuracy
throughout 10-V output swings. This AC performance,
combined with only 125 μV of offset and 0.35 μV/°C
of drift over temperature, makes the OPA2211-EP
ideal for driving high-precision 16-bit analog-to-digital
converters (ADCs) or buffering the output of highresolution digital-to-analog converters (DACs).
The OPA2211-EP is specified over a wide dual-power
supply range of ±2.25 V to ±18 V, or for single-supply
operation from 4.5 to 36 V.
The OPA2211-EP is available in a small DFN-8 (3mm × 3-mm) package. These operational amplifiers
are specified from TJ = –55°C to 125°C.
Device Information(1)
PART NUMBER
OPA2211-EP
(1)
3.00 mm × 3.00 mm
Voltage Noise Density vs Frequency
100
Voltage Noise Density (nV/ √ Hz)
PLL Loop Filter
Low-Noise, Low-Power Signal Processing
16-Bit ADC Drivers
DAC Output Amplifiers
Active Filters
Low-Noise Instrumentation Amplifiers
Ultrasound Amplifiers
Professional Audio Preamplifiers
Low-Noise Frequency Synthesizers
Infrared Detector Amplifiers
Hydrophone Amplifiers
Geophone Amplifiers
Medical
WSON (8)
BODY SIZE (NOM)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
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PACKAGE
10
1
0.1
1
10
100
1k
10k
100k
Frequency (Hz)
Additional temperature ranges available - contact factory
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA2211-EP
SBOS761 – NOVEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
4
4
5
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics: VS = ±2.25 to ±18 V.........
Typical Characteristics ..............................................
7.4 Device Functional Modes........................................ 16
8
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Application ................................................. 19
9
Power Supply Recommendations...................... 22
9.1 Operating Voltage ................................................... 22
10 Layout................................................................... 22
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 23
10.3 Thermal Considerations ........................................ 23
11 Device and Documentation Support ................. 24
11.1
11.2
11.3
11.4
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 14
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
24
24
24
24
12 Mechanical, Packaging, and Orderable
Information ........................................................... 24
4 Revision History
2
DATE
REVISION
NOTES
November 2015
*
Initial release.
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SBOS761 – NOVEMBER 2015
5 Pin Configuration and Functions
DRG Package
8-Pin WSON
Top View
8 V+
OUT A 1
IN A 2
+IN A 3
7 OUT B
A
B
V 4
6 IN B
5 +IN B
(1)
Pad
(1)
Exposed thermal die pad on underside; connect thermal die pad to V–. Soldering the thermal pad improves heat
dissipation and provides specified performance
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
+IN A
3
I
Noninverting input for channel A
–IN A
2
I
Inverting input for channel A
+IN B
5
I
Noninverting input for channel B
–IN B
6
I
Inverting input for channel B
OUT A
1
O
Output terminal for channel A
OUT B
7
O
Output terminal for channel B
V+
8
—
Positive supply voltage
V–
4
—
Negative supply voltage
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Supply voltage
MAX
UNIT
40
V
VS = (V+) – (V–)
Input voltage
Input current (any pin except power-supply pins)
(V–) – 0.5
(V+) + 0.5
V
–10
10
mA
150
°C
150
°C
Output short-circuit (2)
Continuous
Junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Short-circuit to VS / 2 (ground in symmetrical dual supply setups), one amplifier per package.
6.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±3000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage (V+ – V–)
Operating temperature, TJ
NOM
MAX
UNIT
4.5 (±2.25)
36 (±18)
V
–55
125
°C
6.4 Thermal Information
OPA2211-EP
THERMAL METRIC (1)
DRG (WSON)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
47.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
51.8
°C/W
RθJB
Junction-to-board thermal resistance
21.8
°C/W
ψJT
Junction-to-top characterization parameter
0.7
°C/W
ψJB
Junction-to-board characterization parameter
21.9
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4.2
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SBOS761 – NOVEMBER 2015
6.5 Electrical Characteristics: VS = ±2.25 to ±18 V
at TJ = 25°C, RL = 10 kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
±50
±175
μV
OFFSET VOLTAGE
Input offset voltage
VOS
Over temperature
VS = ±15 V
TJ = –55°C to 125°C
Drift
dVOS/dT
TJ = –55°C to 125°C
vs power supply
PSRR
VS = ±2.25 V to ±18 V
±350
0.1
Over temperature
µV
μV/°C
0.35
1
μV/V
3
μV/V
INPUT BIAS CURRENT
Input bias current
IB
VCM = 0 V, TJ = –55°C to 125°C
±50
±350
nA
Offset current
IOS
VCM = 0 V, TJ = –55°C to 125°C
±20
±200
nA
en
ƒ = 0.1 Hz to 10 Hz
NOISE
Input voltage noise
80
nVPP
2
nV/√Hz
ƒ = 100 Hz
1.4
nV/√Hz
ƒ = 1 kHz
1.1
nV/√Hz
ƒ = 10 Hz
3.2
pA/√Hz
ƒ = 1 kHz
1.7
pA/√Hz
ƒ = 10 Hz
Input voltage noise density
Input current noise density
In
INPUT VOLTAGE RANGE
Common-mode voltage range
Common-mode rejection ratio
VCM
CMRR
VS ≥ ±5 V
(V–) + 1.8
(V+) – 1.4
V
VS < ±5 V
(V–) + 2
(V+) – 1.4
V
VS ≥ ±5V, (V–) + 2V ≤ VCM ≤ (V+) – 2V,
TJ = –55°C to 125°C
114
120
dB
VS < ±5V, (V–) + 2V ≤ VCM ≤ (V+) – 2V,
TJ = –55°C to 125°C
106
120
dB
INPUT IMPEDANCE
Differential
20k || 8
Ω || pF
Common-mode
109 || 2
Ω || pF
OPEN-LOOP GAIN
Open-loop voltage gain
Over temperature
AOL
AOL
(V–) + 0.2 V ≤ VO ≤ (V+) – 0.2V,
RL = 10 kΩ, TJ = –55°C to 125°C
114
130
dB
(V–) + 0.6 V ≤ VO ≤ (V+) – 0.6 V,
RL = 600 Ω
110
114
dB
(V–) + 0.6 V ≤ VO ≤ (V+) – 0.6V,
IO ≤ 15 mA, TJ = –55°C to 125°C
100
dB
FREQUENCY RESPONSE
Gain-bandwidth product
GBW
Slew rate
SR
Settling time, 0.01%
tS
0.0015% (16-bit)
Overload recovery time
Total harmonic distortion + noise
THD+N
G = 100
80
MHz
G=1
45
MHz
27
V/μs
VS = ±15 V, G = –1, 10-V step, CL = 100
pF
400
ns
VS = ±15 V, G = –1, 10-V step, CL = 100
pF
700
ns
G = –10
500
ns
G = +1, ƒ = 1kHz,
VO = 3VRMS, RL = 600 Ω
0.000015
%
–136
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Electrical Characteristics: VS = ±2.25 to ±18 V (continued)
at TJ = 25°C, RL = 10 kΩ connected to midsupply, VCM = VOUT = midsupply, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
Voltage output
VOUT
Short-circuit current
ISC
Capacitive load drive
CLOAD
Open-loop output impedance
ZO
RL = 10 kΩ, AOL ≥ 114 dB, TJ = –55°C to
125°C
(V–) + 0.2
(V+) – 0.2
V
RL = 600 Ω, AOL ≥ 110 dB
(V–) + 0.6
(V+) – 0.6
V
IO < 15 mA, AOL ≥ 100 dB, TJ = –55°C to
125°C
(V–) + 0.6
(V+) – 0.6
V
+30/–45
mA
See Typical Characteristics
pF
5
Ω
ƒ = 1MHz
POWER SUPPLY
Specified voltage
VS
Quiescent current (per channel)
IQ
Over temperature
±2.25
IOUT = 0 A
3.6
TJ = –55°C to 125°C
±18
V
4.5
mA
6
mA
125
°C
TEMPERATURE RANGE
Operating range
6
TJ
–55
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6.6 Typical Characteristics
At TJ = 25°C, VS = ±18 V, and RL = 10 kΩ, unless otherwise noted.
100
Current Noise Density (pA/ÖHz)
Voltage Noise Density (nV/ÖHz)
100
10
1
10
1
0.1
1
10
100
1k
10k
100k
0.1
1
10
Frequency (Hz)
100
1k
10k
100k
Frequency (Hz)
Figure 1. Input Voltage Noise Density vs Frequency
Figure 2. Input Current Noise Density vs Frequency
VS = ±15V
-90 V = 3.5V
IN
RMS
-100 G = 1
RL = 600W
-110
20nV/div
Channel Separation (dB)
-80
-120
-130
-140
RL = 2kW
-150
-160
RL = 5kW
-170
-180
100
10
1k
10k
Time (1s/div)
100k
Frequency (Hz)
Figure 4. 0.1-Hz to 10-Hz Noise
Figure 3. Channel Separation vs Frequency
160
140
140
120
100
100
CMRR (dB)
PSRR (dB)
120
-PSRR
80
+PSRR
60
80
60
40
40
20
20
0
0
1
10
100
1k
10k
100k
1M
10M
100M
10k
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
Figure 5. Power-Supply Rejection Ratio vs Frequency
(Referred to Input)
Figure 6. Common-Mode Rejection Ratio vs Frequency
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Typical Characteristics (continued)
At TJ = 25°C, VS = ±18 V, and RL = 10 kΩ, unless otherwise noted.
180
140
10k
120
Gain (dB)
100
100
10
80
90
60
40
Gain
20
1
135
Phase
Phase (°)
ZO (W)
1k
45
0
0.1
100
1k
10k
100k
1M
10M
100
100M
1k
10k
Figure 7. Open-Loop Output Impedance vs Frequency
5
100k
1M
10M
Frequency (Hz)
Frequency (Hz)
Figure 8. Gain and Phase vs Frequency
RL = 10kW
4
3
2
300mV Swing From Rails
1
Population
Open-Loop Gain (mV/V)
0
100M
-20
10
0
-1
200mV Swing From Rails
-2
-3
-4
112.5
125.0
87.5
100.0
62.5
75.0
37.5
50.0
25.0
0
12.5
-12.5
-37.5
-25.0
-62.5
-50.0
75 100 125 150 175 200
-87.5
50
Temperature (°C)
-75.0
25
-112.5
0
-100.0
-75 -50 -25
-125.0
-5
Offset Voltage (mV)
Figure 10. Offset Voltage Production Distribution
Figure 9. Normalized Open-Loop Gain vs Temperature
200
Population
IB and IOS Bias Current (nA)
150
100
+IB
50
IOS
0
-50
-IB
-100
-150
-200
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
-50
Offset Voltage Drift (mV/°C)
0
25
50
75
100
125
150
Ambient Temperature (°C)
Figure 11. Offset Voltage Drift Production Distribution
8
-25
Figure 12. IB and IOS Current vs Temperature
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Typical Characteristics (continued)
At TJ = 25°C, VS = ±18 V, and RL = 10 kΩ, unless otherwise noted.
12
10
2000
1500
8
VOS Shift (mV)
1000
500
VOS (mV)
20 Typical Units Shown
0
-500
-1000
6
4
2
0
-2
-4
-6
-8
-1500
-10
-12
-2000
(V-)+1.0 (V-)+1.5 (V-)+2.0
0
(V+)-1.5 (V+)-1.0 (V+)-0.5
10
20
30
VCM (V)
Figure 13. Offset Voltage vs Common-Mode Voltage
100
80
60
50
Figure 14. VOS Warmup
100
5 Typical Units Shown
VS = 36V
3 Typical Units Shown
75
60
50
40
20
IOS (nA)
IOS (nA)
40
Time (s)
0
-20
25
0
-25
Common-Mode Range
-40
-50
-60
-75
-80
-100
2.25
-100
4
6
8
10
12
14
1
18
16
5
10
15
Figure 15. Input Offset Current vs Supply Voltage
25
30
35
Figure 16. Input Offset Current vs Common-Mode Voltage
150
150
3 Typical Units Shown
100
VS = 36V
3 Typical Units Shown
100
Unit 1
-IB
+IB
Unit 2
50
IB (nA)
50
IB (nA)
20
VCM (V)
VS (±V)
0
Unit 2
Unit 1
0
Unit 3
-50
-50
Unit 3
-100
-IB
-100
Common-Mode Range
+IB
-150
2.25
-150
4
6
8
10
12
14
16
18
1
5
10
15
20
25
30
35
VCM (V)
VS (±V)
Figure 17. Input Bias Current vs Supply Voltage
Figure 18. Input Bias Current vs Common-Mode Voltage
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Typical Characteristics (continued)
At TJ = 25°C, VS = ±18 V, and RL = 10 kΩ, unless otherwise noted.
6
4.0
3.5
5
3.0
2.5
IQ (mA)
IQ (mA)
4
3
2.0
1.5
2
1.0
1
0.5
0
0
-75 -50 -25
0
25
0
75 100 125 150 175 200
50
4
8
12
0.05
0
ISC (mA)
IQ Shift (mA)
-0.05
-0.10
-0.15
-0.20
-0.25
Average of 10 Typical Units
24
28
32
36
60
50
40
30
20
10
0
-10
-20
-30
-40
-50
Sourcing
Sinking
-60
-0.30
0
60
120 180 240 300 360 420 480 540
-75 -50 -25
600
0
25
50
75
100 125 150 175 200
Temperature (°C)
Time (s)
Figure 22. Short-Circuit Current vs Temperature
Figure 21. Normalized Quiescent Current vs Time
G = -1
CL = 100pF
G = -1
CL = 10pF
CF
5.6pF
CF
5.6pF
RI
604W
20mV/div
20mV/div
20
Figure 20. Quiescent Current vs Supply Voltage
Figure 19. Quiescent Current vs Temperature
RF
604W
RI
604W
RF
604W
+18V
+18V
OPA211
OPA211
CL
CL
-18V
-18V
Time (0.1µs/div)
Time (0.1µs/div)
Figure 23. Small-Signal Step Response (100 mV)
10
16
VS (V)
Temperature (°C)
Figure 24. Small-Signal Step Response (100 mV)
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Typical Characteristics (continued)
At TJ = 25°C, VS = ±18 V, and RL = 10 kΩ, unless otherwise noted.
G = +1
RL = 600W
CL = 100pF
20mV/div
20mV/div
G = +1
RL = 600W
CL = 10pF
+18V
OPA211
-18V
RL
+18V
OPA211
-18V
CL
Time (0.1ms/div)
RL
CL
Time (0.1ms/div)
Figure 25. Small-Signal Step Response (100 mV)
Figure 26. Small-Signal Step Response (100 mV)
60
G = -1
CL = 100pF
RL = 600W
G = +1
40
G = -1
2V/div
Overshoot (%)
50
30
G = 10
20
10
0
0
200
400
600
800
1000
1200
Time (0.5ms/div)
1400
Capacitive Load (pF)
Figure 27. Small-Signal Overshoot vs Capacitive Load
(100-mV Output Step)
2V/div
RF = 100W
Note: See the
Applications Information
section, Input Protection.
1.0
0.010
0.8
0.008
0.6
0.006
0.4
16-Bit Settling
0.2
-0.2
(±1/2 LSB = ±0.00075%)
-0.4
-0.002
-0.004
-0.6
-0.006
-0.8
-0.008
0
Figure 29. Large-Signal Step Response
0.002
0
0
-1.0
Time (0.5ms/div)
0.004
100
200 300
400 500 600
Time (ns)
D From Final Value (%)
RF = 0W
D From Final Value (mV)
G = +1
CL = 100pF
RL = 600W
Figure 28. Large-Signal Step Response
-0.010
700 800 900 1000
Figure 30. Large-Signal Positive Settling Time
(10 VPP, CL = 100 pF)
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Typical Characteristics (continued)
1.0
0.010
0.008
0.8
0.008
0.6
0.006
0.6
0.006
0.4
0.004
16-Bit Settling
0.2
0
0.002
0
-0.2
(±1/2 LSB = ±0.00075%)
-0.4
-0.002
-0.004
0
0.006
0.4
16-Bit Settling
0.2
0
0.004
0.002
0
(±1/2 LSB = ±0.00075%)
-0.002
-0.004
-0.6
-0.006
-0.8
-0.008
200 300
200 300
400 500 600
Time (ns)
G = -10
0V
10kW
1kW
OPA211
VOUT
VIN
VOUT
-0.010
700 800 900 1000
400 500 600
Time (ns)
-0.010
700 800 900 1000
VIN
5V/div
D From Final Value (mV)
0.6
100
Figure 32. Large-Signal Negative Settling Time (10 VPP, CL =
100 pF)
D From Final Value (%)
0.008
100
-0.004
-0.008
0.010
0
-0.002
-1.0
0.8
-1.0
(±1/2 LSB = ±0.00075%)
-0.4
-0.010
700 800 900 1000
1.0
-0.4
0
-0.2
Figure 31. Large-Signal Positive Settling Time (10 VPP, CL =
10 pF)
-0.2
0.002
0
-0.006
-1.0
400 500 600
Time (ns)
0.004
-0.8
-0.8
200 300
16-Bit Settling
0.2
-0.008
-0.006
100
0.4
-0.6
-0.6
0
D From Final Value (mV)
0.010
0.8
D From Final Value (%)
1.0
D From Final Value (%)
D From Final Value (mV)
At TJ = 25°C, VS = ±18 V, and RL = 10 kΩ, unless otherwise noted.
Time (0.5ms/div)
Figure 33. Large-Signal Negative Settling Time (10 VPP, CL =
10 pF)
Figure 34. Negative Overload Recovery
20
0°C
G = -10
15
10kW
VOUT
1kW
OPA211
VOUT
VOUT (V)
VIN
5V/div
+85°C
+125°C
10
5
+125°C
0
-55°C
0°C
+150°C
-5
0V
VIN
-10
+85°C
-15
-20
Time (0.5ms/div)
0
Figure 35. Positive Overload Recovery
12
10
20
30
40
IOUT (mA)
50
60
70
Figure 36. Output Voltage vs Output Current
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Typical Characteristics (continued)
At TJ = 25°C, VS = ±18 V, and RL = 10 kΩ, unless otherwise noted.
5V/div
Output
+18V
OPA211
Output
37VPP
(±18.5V)
-18V
0.5ms/div
Figure 37. No Phase Reversal
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7 Detailed Description
7.1 Overview
The OPA2211-EP is a unity-gain stable, precision operational amplifier with very low noise. Applications with
noisy or high-impedance power supplies require decoupling capacitors close to the device pins. In most cases,
0.1-μF capacitors are adequate. Functional Block Diagram shows a simplified schematic of the OPA2211-EP.
This die uses a SiGe bipolar process and contains 180 transistors.
7.2 Functional Block Diagram
V+
Pre-Output Driver
IN-
OUT
IN+
V-
7.3 Feature Description
7.3.1 Input Protection
The input terminals of the OPA2211-EPFigure 38 are protected from excessive differential voltage with back-toback diodes, as shown in . In most circuit applications, the input protection circuitry has no consequence.
However, in low-gain or G = 1 circuits, fast ramping input signals can forward bias these diodes because the
output of the amplifier cannot respond rapidly enough to the input ramp. This effect is illustrated in Figure 29 in
the Typical Characteristics. If the input signal is fast enough to create this forward bias condition, the input signal
current must be limited to 10 mA or less. If the input signal current is not inherently limited, an input series
resistor can be used to limit the signal input current. This input series resistor degrades the low-noise
performance of the OPA2211-EP, and is discussed in Noise Performance. Figure 38 shows an example
implementing a current-limiting feedback resistor.
14
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Feature Description (continued)
RF
-
Output
OPA2211-EP
RI
Input
+
Figure 38. Pulsed Operation
7.3.2 Noise Performance
Figure 39 shows total circuit noise for varying source impedances with the operational amplifier in a unity-gain
configuration (no feedback resistor network, and therefore no additional noise contributions). Two different
operational amplifiers are shown with total circuit noise calculated. The OPA2211-EP has very low voltage noise,
making it ideal for low source impedances ( 500kHz
G = 11
RL = 600W
0.0001
-120
G= 1
RL = 5kW
G=1
RL = 600W
0.00001
10
100
1k
10k
Total Harmonic Distortion + Noise (dB)
0.001
-140
100k
Frequency (Hz)
Figure 45. THD+N Ratio vs Frequency
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9 Power Supply Recommendations
9.1 Operating Voltage
OPA2211-EP series operational amplifiers operate from ±2.25-V to ±18-V supplies while maintaining excellent
performance. The OPA2211-EP series can operate with as little as +4.5 V between the supplies and with up to
+36 V between the supplies. However, some applications do not require equal positive and negative output
voltage swing. With the OPA2211-EP series, power-supply voltages do not need to be equal. For example, the
positive supply could be set to +25 V with the negative supply at –5 V or vice-versa.
The common-mode voltage must be maintained within the specified range. In addition, key parameters are
assured over the specified temperature range, TA = –55°C to 125°C. Parameters that vary significantly with
operating voltage or temperature are shown in Typical Characteristics.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp itself.
Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to
the analog circuitry.
– Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current. For more detailed information refer to
Circuit Board Layout Techniques, SLOA089.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as
opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As shown in Figure 46, keeping RF and
RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit may experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, TI recommends baking the PCB assembly to
remove moisture introduced into the device packaging during the cleaning process. A low temperature, post
cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
22
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10.2 Layout Example
RIN
VIN
+
VOUT
RG
±
RF
(Schematic Representation)
Place components close to
device and to each other to
reduce parasitic errors
Run the input traces as
far away from the supply
lines as possible
VS+
RF
GND
OUT A
V+
±IN A
OUT B
+IN A
±IN B
V±
+IN B
RG
GND
RIN
VIN
GND
Only needed for dualsupply operation
VS±
(or GND for single supply)
VOUT
Use low-ESR, ceramic
bypass capacitor
Ground (GND) plane on another layer
Figure 46. Operational Amplifier Board Layout for Noninverting Configuration
10.3 Thermal Considerations
The primary issue with all semiconductor devices is junction temperature (TJ). The most obvious consideration is
assuring that TJ never exceeds the absolute maximum rating specified for the device. However, addressing
device thermal dissipation has benefits beyond protecting the device from damage. Even modest increases in
junction temperature can decrease operational amplifier performance, and temperature-related errors can
accumulate. Understanding the power generated by the device within the specific application and assessing the
thermal effects on the error tolerance lead to a better understanding of system performance and thermal
dissipation needs.
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11 Device and Documentation Support
11.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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6-Feb-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA2211MDRGTEP
ACTIVE
SON
DRG
8
250
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
OCQM
V62/15606-01XE
ACTIVE
SON
DRG
8
250
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
-55 to 125
OCQM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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