OPA810IDBVT

OPA810 OPA810 SBOS799D – AUGUST 2019 – REVISED JULY 2020 SBOS799D – AUGUST 2019 – REVISED JULY 2020 www.ti.com OPA810 140-MHz, Rail-to-Rail Input and Output, FET-Input Operational Amplifier 1 Features 3 Description • • • • • The OPA810 is a single-channel, field-effect transistor (FET)-input, voltage-feedback operational amplifier with bias current in the picoampere (pA) range. The OPA810 is unity-gain stable with a small-signal, unitygain bandwidth of 140 MHz, and offers excellent DC precision and dynamic AC performance at a low quiescent current (IQ) of 3.7 mA per channel. The OPA810 is fabricated on Texas Instrument's proprietary, high-speed SiGe BiCMOS process and achieves significant performance improvements over comparable FET-input amplifiers at similar levels of quiescent power. With a gain-bandwidth product (GBWP) of 70 MHz, slew rate of 200 V/µs, and lownoise voltage of 6.3 nV/√ Hz, the OPA810 is well suited for use in a wide range of high-fidelity data acquisition and signal processing applications. • • • • • • Gain-Bandwidth Product: 70 MHz Small-Signal Bandwidth: 140 MHz Slew Rate: 200 V/µs Wide Supply Range: 4.75 V to 27 V Low Noise: – Input Voltage Noise: 6.3 nV/√ Hz (f = 500 kHz) – Input Current Noise: 5 fA/√ Hz (f = 10 kHz) Rail-to-Rail Input and Output: – FET Input Stage: 2-pA Input Bias Current (Typical) – High Linear Output Current: 75 mA Input Offset: ±500 µV (Maximum) Offset Drift: ±2.5 µV/°C (Typical) Low Power: 3.7 mA/Channel Extended Temperature Operation: –40°C to +125°C Dual-Channel Version: OPA2810 2 Applications • • • • • • • • Wideband Photodiode Transimpedance Amplifiers Analog Input and Output Modules Impedance Measurements Power Analyzers and Meters High-Z Voltage and Current Measurements Data Acquisition Multichannel Sensor Interfaces Optoelectronic Drivers The OPA810 features rail-to-rail inputs and outputs and delivers 75 mA of linear output current, suitable for driving optoelectronics components and analog-todigital converter (ADC) inputs or buffering digital-toanalog converter (DAC) outputs into heavy loads. The OPA810 is rated over the extended industrial temperature range of –40°C to +125°C. The OPA2810 is a dual-channel variant of this device, available in 8pin SOIC, SOT-23, and VSSOP packages. Device Information PART NUMBER(1) OPA810 (1) PACKAGE BODY SIZE (NOM) SOIC (8) 4.90 mm × 3.91 mm SOT-23 (5) 2.90 mm × 1.60 mm SC70 (5) 2.00 mm × 1.25 mm For all available packages, see the orderable addendum at the end of the data sheet. CF 12V RF ± OPA810 + VIN+ R C 1.8V 1.8V AVDD DVDD RG 12V RS ± -12V VOCM 12V C CB ADS911 0 18-bit 2 MSPS THS456 1 + CCB RG VREF ± -0.2V OPA810 + VINR C RF R¶ R¶ -12V 5V CF 5V 12V REF505 0 5.0 V Reference RFIL T ± ± OPA837 OPA378 + + CFIL T High-Z Input Data Acquisition Front-End An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated intellectual property matters and other important disclaimers. PRODUCTION DATA. Product Folder Links: OPA810 1 OPA810 www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Device Comparison Table...............................................3 6 Pin Configuration and Functions...................................3 Pin Functions.................................................................... 3 7 Specifications.................................................................. 4 7.1 Absolute Maximum Ratings........................................ 4 7.2 ESD Ratings............................................................... 4 7.3 Recommended Operating Conditions.........................4 7.4 Thermal Information....................................................4 7.5 Electrical Characteristics: 10 V................................... 5 7.6 Electrical Characteristics: 24 V................................... 7 7.7 Electrical Characteristics: 5 V..................................... 9 7.8 Typical Characteristics: VS = 10 V.............................11 7.9 Typical Characteristics: VS = 24 V............................ 14 7.10 Typical Characteristics: VS = 5 V............................ 17 7.11 Typical Characteristics: ±2.375-V to ±12-V Split Supply......................................................................... 19 8 Detailed Description......................................................22 8.1 Overview................................................................... 22 8.2 Functional Block Diagram......................................... 22 8.3 Feature Description...................................................23 8.4 Device Functional Modes..........................................24 9 Application and Implementation.................................. 25 9.1 Application Information............................................. 25 9.2 Typical Applications.................................................. 30 10 Power Supply Recommendations..............................34 11 Layout........................................................................... 34 11.1 Layout Guidelines................................................... 34 11.2 Layout Example...................................................... 36 12 Device and Documentation Support..........................37 12.1 Third-Party Products Disclaimer............................. 37 12.2 Documentation Support.......................................... 37 12.3 Receiving Notification of Documentation Updates..37 12.4 Support Resources................................................. 37 12.5 Trademarks............................................................. 37 12.6 Electrostatic Discharge Caution..............................37 12.7 Glossary..................................................................38 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (June 2020) to Revision C (July 2020) Page • Changed the status of the DCK package From: Preview To: Production .......................................................... 1 Changes from Revision A (December 2019) to Revision B (June 2020) Page • Changed the status of the DBV package From: Preview To: Production .......................................................... 1 • Added noise corner information to 10 V, 24 V and 5 V electrical characteristics tables..................................... 5 • Changed offset voltage test conditions for 10 V, 24 V and 5 V supplies for SOIC, SOT23 and SC70 packages. ............................................................................................................................................................................5 • Updated Figure 62. Noninverting Amplifier ......................................................................................................25 Changes from Revision * (August 2019) to Revision A (December 2019) Page • Changed document status From: Advance Information To: Production Data ....................................................1 2 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 OPA810 www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020 5 Device Comparison Table DEVICE VS ± (V) IQ / CHANNEL (mA) GBWP (MHz) SLEW RATE (V/μs) VOLTAGE NOISE (nV/√ Hz) OPA2810 ±12 3.6 70 192 6 Unity-gain stable FET input AMPLIFIER DESCRIPTION OPA607 ±2.5 0.9 50 24 3.8 Gain of 6, stable, low-cost CMOS amplifier THS4631 ±15 13 210 900 7 Unity-gain stable FET input OPA859 ±2.625 20.5 1800 1150 3.3 Unity-gain stable FET input OPA818 ±6.5 27.7 2700 1400 2.2 Gain of 7, stable FET input 6 Pin Configuration and Functions NC 1 8 NC VIN± 2 7 VS+ VIN+ 3 6 VO VS± 4 5 NC Not to scale VO 1 VS± 2 VIN+ 3 5 VS+ 4 VIN± Figure 6-2. 5-Pin SOT23 (DBV) and SC70 (DCK) Packages Figure 6-1. 8-Pin SOIC (D) Package Pin Functions PIN NAME SOIC SOT-23 and SC70 TYPE(1) DESCRIPTION NC 1 — — VIN– 2 4 I Inverting input pin VIN+ 3 3 I Noninverting input pin VS– 4 2 P Negative power-supply pin NC 5 — — No internal connection VO 6 1 O Output pin VS+ 7 5 P Positive power-supply pin NC 8 — — No internal connection (1) No internal connection I = input, O = output, and P = power. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 3 OPA810 www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020 7 Specifications 7.1 Absolute Maximum Ratings Over operating free-air temperature range (unless otherwise noted).(1) MIN VS Supply voltage (total bipolar supplies)(4) VIN Input voltage VIN,Diff Differential input voltage(2) II Continuous input current IO Continuous output current(3) PD Continuous power dissipation TJ Junction temperature Tstg Storage temperature (1) (2) (3) (4) VS– – 0.5 MAX UNIT ±14 V VS+ + 0.5 V ±7 V ±10 mA TA = –40℃ to +85℃ ±40 mA TA = 125℃ ±15 mA See Section 7.4 –65 150 °C 125 °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Equal to the lower of ±7 V or total supply voltage. Long-term continuous output current for electromigration limits. VS is the total supply voltage given by VS = VS+ – VS– . 7.2 ESD Ratings UNIT VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500 V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 7.3 Recommended Operating Conditions Over operating free-air temperature range (unless otherwise noted). MIN NOM MAX VS Total supply voltage 4.75 TA Ambient temperature –40 25 D (SOIC) DBV (SOT-23) DCK (SC70) 8 PINS 5 PINS 5 PINS UNIT 27 V 125 °C 7.4 Thermal Information OPA810 THERMAL METRIC(1) RθJA Junction-to-ambient thermal resistance 134.8 174.3 190.8 °C/W RθJC(top) Junction-to-case (top) thermal resistance 75.2 94.7 140.1 °C/W RθJB Junction-to-board thermal resistance 78.2 45.4 69.0 °C/W ψJT Junction-to-top characterization parameter 25.2 21.6 45.9 °C/W ψJB Junction-to-board characterization parameter 77.4 45.0 68.8 °C/W (1) 4 UNIT For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 OPA810 www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020 7.5 Electrical Characteristics: 10 V Test conditions unless otherwise noted: TA = 25°C, VS+ = 5 V, VS– = –5 V, common-mode voltage (VCM) = midsupply, RL = 1 kΩ connected to mid-supply(5). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL(3) AC PERFORMANCE SSBW Small-signal bandwidth LSBW Large-signal bandwidth GBWP Gain-bandwidth product G = 1, VO = 20 mVPP, RF = 0 Ω 135 G = 1, VO = 20 mVPP, RF = 0 Ω, CL = 10 pF 140 C 68 C G = 2, VO = 2 VPP 41 MHz C 70 MHz C 16 MHz C 200 V/µs C Slew rate (20%-80%)(4) G = 2, VO = –2-V to 2-V step Rise time VO = 200-mV step 4 ns C Fall time VO = 200-mV step 4 ns C Settling time to 0.1% Settling time to 0.001% HD2 MHz G = –1, VO = 20 mVPP Bandwdith for 0.1-dB flatness G = 2, VO = 20 mVPP SR C G = 2, VO = 2-V step 47 G = 2, VO = 8-V step 65 G = 2, VO = 2-V step 330 G = 2, VO = 8-V step 230 ns ns C C C C Input overdrive recovery G = 1, RF = 0 Ω, (VS– – 0.5 V) to (VS+ + 0.5 V) input 55 ns C Output overdrive recovery G = –1, (VS– – 0.5 V) to (VS+ + 0.5 V) input 55 ns C Second-order harmonic distortion f = 100 kHz, RL = 1 kΩ, VO = 2 VPP –120 f = 1 MHz, RL = 1 kΩ, VO = 2 VPP –101 f = 100 kHz, RL = 1 kΩ, VO = 2 VPP –137 –101 HD3 Third-order harmonic distortion f = 1 MHz, RL = 1 kΩ, VO = 2 VPP en Input-referred voltage noise Flatband, 1/f corner at 1.5 kHz in Input-referred current noise f = 10 kHz zO Closed-loop output impedance f = 100 kHz dBc dBc C C C C 6.3 nV/√ Hz C 5 fA/√ Hz C Ω C dB A µV A 0.007 DC PERFORMANCE AOL VOS Open-loop voltage gain Input offset voltage Input offset voltage drift CMRR f = DC, VO = ±2.5 V 108 120 SOIC package 100 500 DBV and DCK packages 100 715 TA = –40°C to +125°C 2.5 10 µV/°C B Input bias current 2 20 pA A Input offset current 1 20 pA A f = DC, VCM = –3 V to 1 V, SOIC Common-mode rejection ratio package TA = –40°C to +125°C, SOIC package 80 100 dB 80 A B INPUT Allowable input differential voltage See Figure 7-54 Common-mode input impedance In closed-loop configuration Differential input capacitance In open-loop configuration Most positive input voltage ΔVOS < 5 mV(1) ±7 V C GΩ||pF C 0.5 pF C VS+ + 0.3 V A 12 || 2 VS+ + 0.2 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 5 OPA810 www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL(3) Most negative input voltage ΔVOS < 5 mV(1) VS– – 0.2 VS– – 0.3 V A Most positive input voltage for main-JFET stage See Figure 7-17 VS+ – 2.9 VS+ – 2.5 V C VOCRH Output voltage range high RL = 667 Ω VS+ – 0.18 VS+ – 0.11 V A VOCRH Output voltage range high TA = –40°C to +125°C, RL = 667 Ω OUTPUT VOCRL Output voltage range low RL = 667 Ω VOCRL Output voltage range low TA = –40°C to +125°C, RL = 667 Ω IO(max) Linear output drive (sourcing and sinking) VO = 2.65 V, RL = 51 Ω, ΔVOS < 1 mV ISC Output short-circuit current CL Capacitive load drive VS+ – 0.2 V B VS– + 0.15 V A VS– + 0.2 V B 75 mA A 100 mA B 10 pF C mA A VS– + 0.08 52 < 3-dB peaking, RS = 0 Ω POWER SUPPLY IQ Quiescent current per channel PSRR Power-supply rejection ratio 3.7 ΔVS = ±2 V(2), SOIC package 79 TA = –40°C to +125°C, SOIC package 79 4.6 100 dB A B AUXILIARY CMOS INPUT STAGE Gain-bandwidth product (1) (2) (3) (4) (5) 6 Input-referred voltage noise f = 1 MHz Input offset voltage VCM = VS+ – 1.5 V, no load, SOIC Package Input bias current VCM = VS+ – 1.5 V 27 MHz C 20 nV/√ Hz C 1.6 mV A 20 pA A 2 Change in input offset from its value when input is biased to midsupply. Change in supply voltage from the default test condition with only one of the positive or negative supplies changing corresponding to +PSRR and –PSRR. Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information. Lower of the measured positive and negative slew rate. For AC specifications, G = 2 V/V, RF = 1 kΩ and CL = 4.7 pF (unless otherwise noted). Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 OPA810 www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020 7.6 Electrical Characteristics: 24 V Test conditions unless otherwise noted: TA = 25°C, VS+ = 12 V, VS– = –12 V, common-mode voltage (VCM) = midsupply, RL = 1 kΩ connected to mid-supply(5). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Test Level(3) AC PERFORMANCE SSBW Small-signal bandwidth G = 1, Vo = 20 mVPP, RF = 0 Ω 135 G = 1, Vo = 20 mVPP, RF = 0 Ω, CL= 10 pF 140 G = –1, Vo = 20 mVPP C MHz 68 G = 2 Vo = 2 VPP 44 G = 2 Vo = 10 VPP 14 C C Large-signal bandwidth GBWP Gain-bandwidth product 70 MHz C Bandwdith for 0.1-dB flatness G = 2, Vo = 20 mVPP 16 MHz C SR Slew rate (20%-80%)(4) 222 G = 2, Vo = –4.5-V to 3.5-V step 254 C V/µs C C Rise time Vo = 200-mV step 4 ns C Vo = 200-mV step 4 ns C Settling time to 0.001% HD3 237 G = –1, Vo = –2-V to 2-V step C Fall time Settling time to 0.1% HD2 G = 2, Vo = –2-V to 2-V step MHz C LSBW G = 2, Vo = 2-V step 47 G = 2, Vo = 10-V step 70 G = 2, Vo = 2-V step 320 G = 2, Vo = 10-V step 200 ns ns C C C C Input overdrive recovery G = 1, RF = 0 Ω, (VS– – 0.5 V) to (VS+ + 0.5 V) input 35 ns C Output overdrive recovery G = –1, (VS– – 0.5 V) to (VS+ + 0.5 V) input 45 ns C Second-order harmonic distortion Third-order harmonic distortion f = 100 kHz, RL = 1 kΩ, Vo = 2 VPP –118 f = 100 kHz, RL =1 kΩ, Vo = 10 VPP –108 f = 1 MHz, RL = 1 kΩ, Vo = 2 VPP –112 f = 1 MHz, RL=1 kΩ, Vo = 10 VPP –91 C C f = 100 kHz, RL = 1 kΩ, Vo = 2 VPP –136 f = 100 kHz, RL =1 kΩ, Vo = 10 VPP –130 C dBc dBc C C C f = 1 MHz, RL = 1 kΩ, Vo = 2 VPP –104 f = 1 MHz, RL =1 kΩ, Vo = 10 VPP –91 6.3 nV/√ Hz C 5 fA/√ Hz C Ω C dB A µV A µV/°C B en Input-referred voltage noise Flatband, 1/f corner at 1.5 kHz in Input-referred current noise f = 10 kHz zO Closed-loop output impedance f = 100 kHz C C 0.007 DC PERFORMANCE AOL VOS Open-loop voltage gain 108 120 100 500 DBV and DCK packages 100 550 TA = –40°C to +125°C 2.5 10 Input bias current 2 20 pA A Input offset current 1 20 pA A Input offset voltage Input offset voltage drift CMRR f = DC, Vo = ±8 V SOIC package Common-mode rejection ratio f = DC, VCM = ±5 V, SOIC package 90 TA = –40°C to +125°C, SOIC package 90 105 dB A B Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 7 OPA810 www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Test Level(3) V C GΩ||pF C INPUT Allowable input differential voltage see Figure 7-54 Common-mode input impedance In closed-loop configuration Differential input capacitance In open-loop configuration 0.5 pF C Most positive input voltage ΔVOS < 5 mV(1) VS+ + 0.2 VS+ + 0.3 V A mV(1) VS– – 0.2 VS– – 0.3 V A VS+ – 2.9 VS+ – 2.5 V C RL = 667 Ω VS+ – 0.33 VS+ – 0.22 TA = –40°C to +125°C, RL = 667 Ω VS+ – 0.36 Most negative input voltage ΔVOS < 5 Most positive input voltage for main-JFET stage See Figure 7-33 ±7 12 || 2.5 OUTPUT VOCRH Output voltage range high RL = 667 Ω VOCRL VS– + 0.15 Output voltage range low Linear output drive (sourcing and sinking) ISC Output short-circuit current CL Capacitive load drive Vo = 7.25 V, RL = 151 Ω, ΔVOS < 1 mV VS– + 0.23 VS– + 0.33 TA = –40°C to +125°C, RL = 667 Ω IO(max) V 48 < 3-dB peaking, RS = 0 Ω A B A V B 64 mA A 108 mA B 10 pF C mA A POWER SUPPLY IQ Quiescent current per channel PSRR Power supply rejection ratio 3.8 ΔVS = ±2 V(2), SOIC package 90 TA = –40°C to +125°C, SOIC package 90 4.7 105 dB A B AUXILIARY CMOS INPUT STAGE Gain-bandwidth product (1) (2) (3) (4) (5) 8 Input-referred voltage noise f = 1 MHz Input offset voltage VCM = VS+ – 1.5 V, no load, SOIC Package Input bias current VCM = VS+ – 1.5 V 27 MHz C 20 nV/√ Hz C 1.6 mV A 24 pA A 2 Change in input offset from its value when input is biased to midsupply. Change in supply voltage from the default test condition with only one of the positive or negative supplies changing corresponding to +PSRR and -PSRR. Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information. Lower of the measured positive and negative slew rate. For AC specifications, G = 2 V/V, RF = 1 kΩ and CL = 4.7 pF (unless otherwise noted). Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 OPA810 www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020 7.7 Electrical Characteristics: 5 V Test conditions unless otherwise noted: TA = 25°C, VS+ = 5 V, VS– = 0 V, common-mode voltage (VCM) = 1.25 V, RL = 1 kΩ connected to 1.25 V(5). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Test Level(1) AC PERFORMANCE SSBW Small-signal bandwidth G = 1, Vo = 20 mVPP, RF = 0 Ω 133 G = 1, Vo = 20 mVPP, RF= 0 Ω, CL= 10 pF 135 G = –1, Vo = 20 mVPP LSBW Large-signal bandwidth GBWP Gain-bandwidth product MHz 65 G = 2 Vo = 2 VPP Bandwdith for 0.1-dB flatness G = 2, Vo = 20 mVPP SR C C C 36 MHz C 70 MHz C 16 MHz C G = 2, Vo = –1-V to 1-V step 134 Slew rate (20%-80%)(4) G = 2, Vo = –2-V to 2-V step, VS = ±2.5 V 78 Rise time Vo = 200-mV step 4 ns C Fall time Vo = 200-mV step 4 ns C Settling time to 0.1% G = 2, Vo = –2-V to 0-V step, VS = ±2.5 V 100 ns C Settling time to 0.001% G = 2, Vo = –2-V to 0-V step, VS = ±2.5 V 565 ns C Input overdrive recovery G = 1, (VS– – 0.5 V) to (VS+ + 0.5 V) input, VS = ±2.5 V 76 ns C Output overdrive recovery G = –1, (VS– – 0.5 V) to (VS+ + 0.5 V) input, VS = ±2.5 V 93 ns C f = 100 kHz, RL = 1 kΩ, Vo = 2 VPP C V/µs –102 C C HD2 Second-order harmonic distortion HD3 Third-order harmonic distortion f = 1 MHz, RL = 1 kΩ, Vo = 2 VPP –92 6.3 nV/√ Hz C 5 fA/√ Hz C 0.007 Ω C 118 dB A µV A f = 1 MHz, RL = 1 kΩ, Vo = 2 VPP f = 100 kHz, RL = 1 kΩ, Vo = 2 VPP en Input-referred voltage noise Flatband, 1/f corner at 1.5 kHz in Input-referred current noise f = 10 kHz zO Closed-loop output impedance f = 100 kHz dBc –81 –114 dBc C C C DC PERFORMANCE AOL Open-loop voltage gain VOS Input offset voltage Input offset voltage drift CMRR f = DC, Vo = 1.25 V to 3.25 V 104 SOIC package 100 550 DBV and DCK packages 100 760 TA = –40°C to +125°C 2.5 10 µV/°C B Input bias current 2 20 pA A Input offset current 1 20 pA A f = DC, VCM = 0.75 V to 1.75 V, SOIC Common-mode rejection ratio package TA = –40°C to +125°C, SOIC package 73 92 dB 73 A B INPUT Allowable input differential voltage See Figure 7-54 Common-mode input impedance In closed-loop configuration Differential input capacitance In open-loop configuration ±5 12 || 2.5 0.5 V C GΩ||pF C pF C Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 9 OPA810 www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020 UNIT Test Level(1) VS+ + 0.3 V A VS- – 0.2 VS- – 0.3 V A VS+ – 2.9 VS+ – 2.5 V C RL = 667 Ω VS+ – 0.12 VS+ – 0.09 TA = –40°C to +125°C, RLOAD = 667 Ω VS+ – 0.15 PARAMETER Most positive input voltage TEST CONDITIONS MIN TYP ΔVOS < 5 mV(2) VS+ + 0.2 mV(2) Most negative input voltage ΔVOS < 5 Most positive input voltage for main-JFET stage See Figure 7-41 MAX OUTPUT VOCRH Output voltage range high RL = 667 Ω VOCRL VS–+ 0.06 Output voltage range low Linear output drive (sourcing and sinking) ISC Output short-circuit current CL Capacitive load drive VO = 1.4 V, RL = 27.5 Ω, ΔVOS < 1 mV, VS+ = 3 V and VS– = –2 V VS– + 0.11 VS– + 0.15 TA = –40°C to +125°C, RL = 667 Ω IO(max) V 50 < 3-dB peaking, RS = 0 Ω A B A V B 64 mA A 96 mA B 10 pF C mA A POWER SUPPLY IQ Quiescent current per channel PSRR Power-supply rejection ratio 3.15 3.7 ΔVS = ±0.5 V(3), SOIC package 78 100 TA = –40°C to +125°C, SOIC package 78 4.5 dB A B AUXILIARY CMOS INPUT STAGE Gain-bandwidth product (1) (2) (3) (4) (5) 10 Input-referred voltage noise f = 1 MHz Input offset voltage VCM = VS+ – 1.5 V, no load, SOIC Package Input bias current VCM = VS+ – 1.5 V 27 MHz C 20 nV/√ Hz C 1.6 mV A 20 pA A 2 Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information. Change in input offset from its value when input is biased to 0 V. Change in supply voltage from the default test condition with only one of the positive or negative supplies changing corresponding to +PSRR and -PSRR. Lower of the measured positive and negative slew rate. For AC specifications, VS+ = 3.5 V, VS– = –1.5 V, G = 2 V/V, RF = 1 kΩ, CL = 4.7 pF, VCM = 0 V (unless otherwise noted). Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 OPA810 www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020 7.8 Typical Characteristics: VS = 10 V At VS+ = 5 V, VS– = –5 V, RL = 1 kΩ, input and output are biased to midsupply, and TA ≈ 25°C. For AC specifications, VO = 2 VPP, G = 2 V/V, RF = 1 kΩ, and CL = 4.7 pF (unless otherwise noted). 3 3 0 -3 Normalized Gain (dB) Normalized Gain (dB) 0 -6 -9 -12 Gain = 1 V/V Gain = 1 V/V Gain = 2 V/V Gain = 5 V/V Gain = 10 V/V -15 -18 -21 100k 1M -6 -9 -12 10M Frequency (Hz) -15 100k 100M RL = 500 : RL = 1 k: 1M D041 See Figure 9-1 and Figure 9-2, VO = 20 mVPP 10M Frequency (Hz) 100M D042 See Figure 9-1, VO = 20 mVPP, gain = 1 V/V, RF = 0 Ω Figure 7-1. Small-Signal Frequency Response vs Gain Figure 7-2. Small-Signal Frequency Response vs Output Load 6 6 3 3 0 0 Normalized Gain (dB) Normalized Gain (dB) -3 -3 -6 -9 -12 RS = 0 :, CL = 4.7 pF RS = 0 :, CL = 10 pF RS = 56 :, CL = 22 pF RS = 40 :, CL = 33 pF RS = 47 :, CL = 47 pF -15 -18 -21 100k 1M 10M Frequency (Hz) -3 -6 -9 -12 -15 -18 -21 100k 100M RS = 0 :, CL = 4.7 pF RS = 0 :, CL = 10 pF RS = 0 :, CL = 22 pF RS = 56 :, CL = 47 pF 1M D044 See Figure 9-1 and Figure 8-1, 10M Frequency (Hz) 100M D045 See Figure 9-1and Figure 8-1, VO = 20 mVPP, gain = 2 V/V VO = 20 mVPP, gain = 1 V/V, RF = 0 Ω Figure 7-4. Small-Signal Frequency Response vs CL 3 3 0 0 -3 -3 Normalized Gain (dB) Normalized Gain (dB) Figure 7-3. Small-Signal Frequency Response vs CL -6 -9 -12 -15 VO = 200 mVPP VO = 1 VPP VO = 2 VPP VO = 4 VPP -18 -21 100k 1M -6 -9 -12 -15 -18 10M Frequency (Hz) -21 100k 100M D046 VO = 200 mVPP VO = 1 VPP VO = 2 VPP VO = 4 VPP 1M 10M Frequency (Hz) 100M D047 See Figure 9-1, gain = 2 V/V See Figure 9-1, gain = 1 V/V, RF = 0 Ω Figure 7-5. Large-Signal Frequency Response vs Output Voltage Figure 7-6. Large-Signal Frequency Response vs Output Voltage Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 11 OPA810 www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020 1 Normalized Gain (dB) 0.6 0.4 -60 Gain = 1 V/V Gain = 1 V/V Gain = 2 V/V Gain = 5 V/V Gain = 10 V/V 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 100k HD2, RL = 1 k: HD3, RL = 1 k: HD2, RL = 500 : HD3, RL = 500 : -70 Harmonic Distortion (dBc) 0.8 -80 -90 -100 -110 -120 -130 -140 -150 1M 10M Frequency (Hz) -160 1k 100M See Figure 9-1 and Figure 9-2, VO = 20 mVPP Harmonic Distortion (dBc) Harmonic Distortion (dBc) HD2, Gain = 1 HD3, Gain = 1 HD2, Gain = 2 HD3, Gain = 2 HD2, Gain = -1 HD3, Gain = -1 -70 -100 -110 -120 -130 -140 -80 -90 -100 -110 -120 -130 -140 -150 -150 10k 100k Frequency (Hz) -160 1k 1M 10k D049 See Figure 9-2, gain = –1 V/V 100k Frequency (Hz) 1M D050 See Figure 9-1 and Figure 9-2, RF = 0 Ω Figure 7-9. Harmonic Distortion vs Frequency Figure 7-10. Harmonic Distortion vs Gain 45 0.15 Overshoot, VO = 2 VPP Undershoot, VO = 2 VPP Overshoot, VO = 200 mVPP Undershoot, VO = 200 mVPP 40 Overshoot/Undershoot (%) 0.1 Output Voltage (V) D048 -60 HD2, RL = 1 k: HD3, RL = 1 k: HD2, RL = 500 : HD3, RL = 500 : -90 -160 1k 1M Figure 7-8. Harmonic Distortion vs Frequency -60 -80 100k Frequency (Hz) See Figure 9-1, gain = 2 V/V Figure 7-7. Small-Signal Response Flatness vs Gain -70 10k D051 0.05 0 -0.05 35 30 25 20 15 10 5 -0.1 0 5 Time (100 ns/div) 10 D052 See Figure 9-1, gain = 1 V/V, RF = 0 Ω, CL = 10 pF Figure 7-11. Small-Signal Transient Response 12 15 20 25 30 35 Load Capacitance (pF) 40 45 50 D053 See Figure 9-1, gain = 1 V/V, RF = 0 Ω Figure 7-12. Overshoot and Undershoot vs CL Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 OPA810 SBOS799D – AUGUST 2019 – REVISED JULY 2020 6 6 4 4 Input and Output Voltage (V) Input and Output Voltage (V) www.ti.com 2 0 -2 -4 VIN VOUT -6 2 0 -2 -4 VIN x -1 Gain VO -6 0 200 400 600 800 1000 Time (nsec) 1200 1400 1600 0 See Figure 9-1, gain = 1 V/V, RF = 0 Ω 400 600 800 1000 Time (nsec) 1200 1400 D055 See Figure 9-2, gain = –1 V/V Figure 7-13. Input Overdrive Recovery Figure 7-14. Output Overdrive Recovery 120 Output Short-Circuit Current (mA) 6 4 Output Voltage (V) 200 D054 2 Sourcing Sinking 0 -2 -4 10 20 30 40 50 60 Output Current (mA) 70 80 60 30 0 90 Sourcing Sinking -30 -60 -90 -120 -150 -40 -6 0 90 -20 0 20 40 60 80 100 Ambient Temperature (qC) D056 120 140 D057 Output saturated and then short-circuited Figure 7-15. Output Voltage vs Load Current Figure 7-16. Output Short-Circuit Current vs Ambient Temperature 1200 Input Offset Voltage (PV) 800 400 0 -400 -800 -1200 -6 -4 -2 0 2 Input Common-Mode Voltage (V) 4 6 D058 Measured for 12 units Figure 7-17. Input Offset Voltage vs Input Common-Mode Voltage Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 13 OPA810 www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020 7.9 Typical Characteristics: VS = 24 V 3 3 0 0 -3 -3 Normalized Gain (dB) Normalized Gain (dB) At VS+ = 12 V, VS– = –12 V, RL = 1 kΩ, input and output are biased to midsupply, and TA ≈ 25°C. For AC specifications, VO = 2 VPP, G = 2 V/V, RF = 1 kΩ, and CL = 4.7 pF (unless otherwise noted). -6 -9 -12 -15 Gain = 1 V/V Gain = 1 V/V Gain = 2 V/V Gain = 5 V/V -18 -21 100k 1M -9 -12 -15 -18 10M Frequency (Hz) -21 100k 100M 0 -3 -3 Normalized Gain (dB) 3 0 -6 -9 -12 VO = 200 mVPP VO = 1 VPP VO = 2 VPP VO = 4 VPP -21 100k 1M -12 -15 -21 100k 100M 100M D075 Figure 7-21. Large-Signal Frequency Response vs Vo -60 Harmonic Distortion (dBc) Harmonic Distortion (dBc) 10M Frequency (Hz) -40 HD2, VO = 2 VPP HD3, VO = 2 VPP HD2, VO = 10 VPP HD3, VO = 10 VPP HD2, VO = 20 VPP HD3, VO = 20 VPP -80 -100 -120 -80 HD2, VO = 2 VPP HD3, VO = 2 VPP HD2, VO = 10 VPP HD3, VO = 10 VPP HD2, VO = 20 VPP HD3, VO = 20 VPP -100 -120 -140 -140 10k 100k Frequency (Hz) -160 1k 1M D076 See Figure 9-1, gain = 2 V/V 10k 100k Frequency (Hz) 1M D077 See Figure 9-2, gain = –1 V/V Figure 7-22. Harmonic Distortion vs Frequency vs Vo 14 1M See Figure 9-1, gain = 2 V/V -20 -160 1k VO = 200 mVPP VO = 1 VPP VO = 2 VPP VO = 4 VPP VO = 10 VPP D074 Figure 7-20. Large-Signal Frequency Response vs Output Voltage -60 D072 -9 -18 10M Frequency (Hz) 100M -6 See Figure 9-1, gain = 1 V/V, RF = 0 Ω -40 10M Frequency (Hz) Figure 7-19. Small-Signal Frequency Response vs Output Common-Mode Voltage 3 -18 1M See Figure 9-1, VO = 20 mVPP, gain = 1 V/V, CL = 4.7 pF, RF = 0Ω Figure 7-18. Noninverting Small-Signal Frequency Response vs Gain -15 VCM = 0 V VCM = 9 V VCM = 11 V D071 See Figure 9-1 and Figure 9-2, VO = 20 mVPP Normalized Gain (dB) -6 Figure 7-23. Harmonic Distortion vs Frequency vs Vo Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 OPA810 www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020 6 0.15 4 Output Voltage (V) Output Voltage (V) 0.1 0.05 0 2 0 -2 -0.05 -4 -6 -0.1 Time (100 ns/div) Time (100 ns/div) D079 D078 See Figure 9-1, gain = 1 V/V, RF = 0 Ω See Figure 9-1, gain = 1 V/V, RF = 0 Ω, CL = 10 pF Figure 7-24. Small-Signal Transient Response Figure 7-25. Large-Signal Transient Response 6 12 VO = 2 VPP VO = 10 VPP VO = 20 VPP VO = 4 VPP VO = 10 VPP 4 Output Voltage (V) Output Voltage (V) 8 4 0 -4 2 0 -2 -4 -8 -6 -12 Time (50 ns/div) Time (100 ns/div) D081 D080 See Figure 9-2, gain = –1 V/V See Figure 9-1, gain = 2 V/V Figure 7-26. Large-Signal Transient Response Figure 7-27. Large-Signal Transient Response 25 15 15 Overshoot, VO = 2 VPP Undershoot, VO = 2 VPP Overshoot, VO = 200 mVPP Undershoot, VO = 200 mVPP 10 5 Input and Output Voltage (V) Overshoot/Undershoot (%) 12 20 9 6 3 0 -3 -6 -9 VIN VOUT -12 -15 0 5 10 15 20 25 30 35 40 45 Load Capacitance (pF) 50 55 60 0 D082 See Figure 9-1, gain = 1 V/V, RF = 0 Ω 200 400 Time (nsec) 600 800 D083 See Figure 9-1, gain = 1 V/V, RF = 0 Ω Figure 7-28. Overshoot and Undershoot vs CL Figure 7-29. Input Overdrive Recovery Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 15 OPA810 www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020 15 14 10 9 6 Output Voltage (V) Input and Output Voltage (V) 12 3 0 -3 -6 6 2 Sourcing Sinking -2 -6 -9 -10 VIN x -1 Gain VO -12 -14 -15 0 200 400 600 800 1000 Time (nsec) 1200 0 1400 10 D084 20 30 40 50 60 Output Current (mA) 70 80 90 D085 See Figure 9-2, gain = –1 V/V Figure 7-30. Output Overdrive Recovery Figure 7-31. Output Voltage Range vs Load Current 1500 120 1000 90 Input Offset Voltage (PV) Output Short-Circuit Current (mA) 150 60 30 0 Sourcing Sinking -30 -60 -90 -120 500 0 -500 -1000 -150 -180 -40 -20 0 20 40 60 80 100 Ambient Temperature (qC) 120 140 -1500 -12.5 -10 D086 Output saturated and then short-circuited 10 12.5 D087 Measured for 12 units Figure 7-32. Output Short-Circuit Current vs Ambient Temperature 16 -7.5 -5 -2.5 0 2.5 5 7.5 Input Common-Mode Voltage (V) Figure 7-33. Input Offset Voltage vs Input Common-Mode Voltage Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 OPA810 www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020 7.10 Typical Characteristics: VS = 5 V At VS+ = 5 V, VS– = 0 V, VCM= 1.25 V, RL = 1 kΩ, output is biased to midsupply, and TA ≈ 25°C. For AC specifications, VS+ = 3.5 V, VS– = –1.5 V, VCM= 0 V, VO = 2 VPP, G = 2 V/V, RF = 1 kΩ, and CL = 4.7 pF (unless otherwise noted). 3 0.15 0 Output Voltage (V) Normalized Gain (dB) 0.1 -3 -6 -9 -12 -15 Gain = 1 V/V Gain = 1 V/V Gain = 2 V/V Gain = 5 V/V -18 -21 100k 0 -0.05 -0.1 1M 10M Frequency (Hz) 100M Time (100 ns/div) D010 See Figure 9-1 and Figure 9-2, VO = 20 mVPP D011 See Figure 9-1, gain = 1 V/V, RF = 0 Ω, CL = 10 pF Figure 7-34. Small-Signal Response vs Gain Figure 7-35. Small-Signal Transient Response 60 3 50 45 Input and Output Voltage (V) Overshoot, VO = 2 VPP Undershoot, VO = 2 VPP Overshoot, VO = 200 mVPP Undershoot, VO = 200 mVPP 55 Overshoot/Undershoot (%) 0.05 40 35 30 25 20 15 10 2 1 0 -1 -2 VIN VOUT 5 -3 0 5 10 15 20 25 30 35 Load Capacitance (pF) 40 45 50 0 See Figure 9-1, gain = 1 V/V, RF = 0 Ω 600 800 1000 Time (nsec) 1200 1400 D014 Figure 7-37. Input Overdrive Recovery 3 3 2 2 Output Voltage (V) Input and Output Voltage (V) 400 See Figure 9-1, gain = 1 V/V, RF = 0 Ω Figure 7-36. Overshoot and Undershoot vs CL 1 0 -1 -2 200 D012 1 Sourcing Sinking 0 -1 -2 VIN x -1 Gain VO -3 -3 0 200 400 600 800 1000 Time (nsec) 1200 0 1400 D013 10 20 30 40 50 60 Output Current (mA) 70 80 90 D015 See Figure 9-2, gain = –1 V/V Figure 7-38. Output Overdrive Recovery Figure 7-39. Output Voltage Range vs Output Current Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 17 OPA810 www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020 1000 100 75 Input Offset Voltage (PV) Output Short-Circuit Current (mA) 125 50 25 0 -25 -50 -75 500 0 -500 -100 -125 -40 -1000 -20 0 20 40 60 80 100 Ambient Temperature (qC) 120 140 -3 D016 Output saturated and then short-circuited -1 0 1 Input Common-Mode Voltage (V) 2 3 D017 Measured for 12 units Figure 7-40. Output Short-Circuit Current vs Ambient Temperature 18 -2 Figure 7-41. Input Offset Voltage vs Input Common-Mode Voltage Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 OPA810 www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020 7.11 Typical Characteristics: ±2.375-V to ±12-V Split Supply At VO = 2 VPP, RF = 1 kΩ, RL = 1 kΩ and TA ≈ 25°C (unless otherwise noted). 90 140 70 120 50 100 30 80 10 60 -10 10 100 1k 10k 100k Frequency (Hz) 1M 10M 3 0 Normalized Gain (dB) 110 180 Magnitude Phase 160 Open-Loop Phase (o) Open-Loop Gain Magnitude (dB) 130 -3 -6 -9 VS = 5 V VS = 10 V VS = 24 V -12 40 100M -15 100k Simulated with no output load -70 Harmonic Distortion (dBc) Normalized Gain (dB) -3 -6 -9 VS= 5 V VS= 10 V VS= 24 V -80 -90 -100 -120 -130 -140 -150 1M 10M Frequency (Hz) -160 1k 100M 1M D103 Figure 7-45. Harmonic Distortion vs Frequency vs Supply Voltage 100 HD2, VS = 5 V HD3, VS = 5 V HD2, VS = 10 V HD3, VS = 10 V HD2, VS = 24 V HD3, VS = 24 V Input Voltage Noise (nV/—Hz) Harmonic Distortion (dBc) 100k Frequency (Hz) See Figure 9-1, gain = 2 V/V -60 -90 10k D102 Figure 7-44. Large-Signal Response vs Supply Voltage -100 HD2, VS = 5 V HD3, VS = 5 V HD2, VS = 10 V HD3, VS = 10 V HD2, VS = 24 V HD3, VS = 24 V -110 See Figure 9-1, gain = 2 V/V -80 D101 -60 0 -70 100M Figure 7-43. Large-Signal Response vs Supply Voltage 3 -15 100k 10M Frequency (Hz) See Figure 9-1, gain = 1 V/V, RF = 0 Ω Figure 7-42. Open-Loop Gain and Phase vs Frequency -12 1M D109 -110 -120 -130 -140 10 -150 -160 1k 10k 100k Frequency (Hz) 1 10 1M D104 See Figure 9-2, gain = –1 V/V 100 1k 10k 100k Frequency (Hz) 1M 10M D103 Measured then fit to ideal 1/f model Figure 7-46. Harmonic Distortion vs Frequency vs Supply Voltage Figure 7-47. Input Voltage Noise Density vs Frequency Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 19 OPA810 www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020 100 90 80 Output Impedance (:) Aux Input Voltage Noise (nV/—Hz) 10000 1000 100 70 60 50 40 30 20 10 10 10 100 1k 10k 100k Frequency (Hz) 1M 0 10 10M 100 1k D106 10k 100k Frequency (Hz) 1M 10M 100M D108 Measured then fit to ideal 1/f model Figure 7-48. Auxiliary Input Stage Voltage Noise Density vs Frequency Figure 7-49. Open-Loop Output Impedance vs Frequency 120 Power Supply Rejection Ratio (dB) Common-Mode Rejection Ratio (dB) 120 100 80 60 40 20 10 100 1k 10k 100k Frequency (Hz) 1M 100 80 60 40 20 0 10 10M 100 D110 Figure 7-50. Common-Mode Rejection Ratio vs Frequency 1M 10M 100M D111 Figure 7-51. Power Supply Rejection Ratio vs Frequency 120 20 PSRR VS+ PSRR VS- 100 16 12 Input Bias Current (pA) Power Supply Rejection Ratio (dB) 10k 100k Frequency (Hz) VS = 5 V and 10 V VS = 10 V and 24 V 80 60 40 8 4 0 -4 -8 -12 20 -16 0 100 1k 10k 100k 1M Frequency (Hz) 10M 100M -20 -12.5 -10 D112 Simulated curves, VS = 24 V -7.5 -5 -2.5 0 2.5 5 7.5 Input Common-Mode Voltage (V) 10 12.5 D118 VS = ±12 V Figure 7-52. Power Supply Rejection Ratio vs Frequency 20 1k Figure 7-53. Input Bias Current vs Input CommonMode Voltage Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 OPA810 www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020 4.2 200 Quiescent Current (mA) Non-Inverting Input Bias Current (PA) 300 100 0 -100 -200 4 3.8 3.6 TA = 25qC TA = 125qC -300 -7.5 -6 -4.5 -3 -1.5 0 1.5 3 Differential Input Voltage (V) 4.5 6 3.4 -50 7.5 -25 0 D115 25 50 75 100 Ambient Temperature (qC) 125 150 D117 32 units, SOIC package, VS = ±5 V Abs (VIN,Diff (max)) = VS when VS < 7 V Figure 7-54. Input Bias Current vs Differential Input Voltage Figure 7-55. Quiescent Current vs Ambient Temperature 24000 600 22000 20000 No. of Units in Each Bin Input Offset Voltage (PV) 400 200 0 -200 -400 18000 16000 14000 12000 10000 8000 6000 4000 -600 2000 12 4.1 4.05 4 Input Offset Voltage Drift (PV/qC) D113 10 8 6 -10 500 400 300 200 0 100 0 0 2 -100 2000 4 4 2 4000 6 0 6000 8 -2 8000 10 -4 10000 -6 No. of Units in Each Bin 12000 -200 3.95 Figure 7-57. Quiescent Current Distribution 14 -300 3.9 27000 units, µ = 3.82 mA, σ = 17 µA, VS = 24 V 14000 -400 3.8 Quiescent Current (mA) Figure 7-56. Input Offset Voltage vs Ambient Temperature -500 D120 D116 32 units, SOIC package No. of Units in Each Bin 3.85 150 3.75 125 3.7 25 50 75 100 Ambient Temperature (qC) 3.6 0 -8 -25 3.65 0 -800 -50 D114 Input Offset Voltage (PV) 27000 units, µ = 16 µV, σ = 63 µV, VS = 24 V Figure 7-58. Input Offset Voltage Distribution –40°C to +125°C fit, 32 units, µ = –0.15 µV/°C, σ = 2.5 µV/°C Figure 7-59. Input Offset Voltage Drift Distribution Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 21 OPA810 www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020 8 Detailed Description 8.1 Overview The OPA810 is a single-channel, field-effect transistor (FET)-input, unity-gain stable, voltage-feedback operational amplifier with extremely low input bias current across its common-mode input voltage range. The OPA810, characterized to operate over a wide supply range of 4.75 V to 27 V, has a small-signal, unity-gain bandwidth of 140 MHz and offers both excellent DC precision and dynamic AC performance at low quiescent power. The OPA810 is fabricated on Texas Instrument's proprietary, high-speed SiGe BiCMOS process and achieves significant performance improvements over comparable FET-input amplifiers at similar levels of quiescent power. With a gain-bandwidth product (GBWP) of 70 MHz, extremely high slew rate (200 V/µs), and low noise (6.3 nV/√ Hz), the OPA810 is ideal in a wide range of data acquisition and signal processing applications. The OPA810 includes input clamps to allow maximum input differential voltage of up to 7 V, making the device suitable for use with multiplexers and for processing signals with fast transients. The device achieves these benchmark levels of performance while consuming a typical quiescent current (IQ) of 3.7 mA per channel. The OPA810 can source and sink large amounts of current without degradation in its linearity performance. The wide bandwidth of the OPA810 implies that the device has low output impedance across a wide frequency range, thereby allowing the amplifier to drive capacitive loads up to 10 pF without requiring output isolation. This device is suitable for a wide range of data acquisition, test and measurement front-end buffer, impedance measurement, power analyzer, wideband photodiode transimpedance, and signal processing applications. 8.2 Functional Block Diagram VS+ OPA810 VIN+ + Aux-Stage ± EN + ± CC JFET-Stage VO EN ± ± + VS+ ±2.5 V VIN± VS± 22 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 OPA810 www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020 8.3 Feature Description 8.3.1 OPA810 Architecture The OPA810 features a true high-impedance input stage including a JFET differential-input pair main stage and a CMOS differential-input auxiliary (aux) stage operational within 2.5 V of the positive supply voltage. The bias current is limited to a maximum of 20 pA throughout the common-mode input range of the amplifier. The Section 8.2 section provides a block diagram representation for the input stage of the OPA810. The amplifier exhibits superior performance for high-speed signals (distortion, noise, and input offset voltage) while the aux stage enables rail-to-rail inputs and prevents phase reversal. The device exhibits a CMRR and PSRR of 75 dB (typical) when the input common-mode is in aux stage. The OPA810 also includes input clamps that enable the maximum input differential voltage of up to 7 V (lower of 7 V and total supply voltage). This architecture offers significantly greater differential input voltage capability as compared to one to two times the diode forward voltage drop maximum rating in standard amplifiers, and makes this device suitable for use with multiplexers and processing of signals with fast transients. The input bias currents are also clamped to maximum 300 µA, as Figure 7-54 shows, which does not load the previous driver stage or require current-limiting resistors (except limiting current through the input ESD diodes when input common-mode voltages are greater than the supply voltages). This feature also enables this amplifier to be used as a comparator in systems that require an amplifier and a comparator for signal gain and fault detection, respectively. For the lowest offset, distortion, and noise performance, limit the common-mode input voltage to the main JFET-input stage (greater than 2.5 V away from the positive supply). The OPA810 is a rail-to-rail output amplifier and swings to either of the rails at the output, as shown in Figure 7-15 for 10-V supply operation. This is particularly useful for inputs biased near the rails or when the amplifier is configured in a closed-loop gain such that the output approaches the supply voltage. When the output saturates, it recovers with 55 ns when inputs exceed the supply voltages by 0.5 V in an G = –1 V/V inverting gain with a 10–V supply. The outputs are short-circuit protected with the limits of Figure 7-16. As Figure 8-1 shows, an amplifier phase margin reduces and becomes unstable when driving a capacitive load (CL) at its output. Using a series resistor (RS) between the amplifier output and load capacitance introduces a zero that cancels the pole formed by the amplifier output impedance and CL in the open-loop transfer function. The OPA810 drives capacitive loads of up to 10 pF without causing instability. It is recommended to use a series resistor for larger load capacitance values, as Figure 7-3 shows for OPA810 configured as a unity-gain buffer. As Figure 7-4 shows, when used in a gain larger than 1 V/V, the OPA810 is able to drive a load capacitance larger than 10 pF without the need for a series resistor at its output. RS VIN VO + CL RL Figure 8-1. OPA810 Driving Capacitive Load Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 23 OPA810 www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020 8.3.2 ESD Protection As Figure 8-2 shows, all device pins are protected with internal ESD protection diodes to the power supplies. These diodes provide moderate protection to input overdrive voltages above the supplies. The protection diodes can typically support 10-mA continuous input and output currents. The differential input clamps only limit the bias current when the input common-mode voltages are within the supply voltage range, whereas current-limiting series resistors must be added at the inputs if common-mode voltages higher than the supply voltages are possible. Keep these resistor values as low as possible because using high values degrades noise performance and frequency response. VS+ Power Sup ply ESD Cell VIN+ 300 A ICLAMP + ± VO VIN± VS± Figure 8-2. Internal ESD Protection 8.4 Device Functional Modes 8.4.1 Split-Supply Operation (±2.375 V to ±13.5 V) To facilitate testing with common lab equipment, the OPA810 can be configured to allow for split-supply operation (see the OPA2810DGK Evaluation Module user guide). This configuration eases lab testing because the mid-point between the power rails is ground, and most signal generators, network analyzers, oscilloscopes, spectrum analyzers, and other lab equipment reference the inputs and outputs to ground. Figure 9-1 depicts the OPA810 configured as a noninverting amplifier and Figure 9-2 illustrates the OPA810 configured as an inverting amplifier. For split-supply operation referenced to ground, the power supplies VS+ and VS- are symmetrical around ground and VREF is at GND. Split-supply operation is preferred in systems where the signals swing around ground because of the ease-of-use; however, the system requires two supply rails. 8.4.2 Single-Supply Operation (4.75 V to 27 V) Many newer systems use a single power supply to improve efficiency and reduce the cost of the extra power supply. The OPA810 can be used with a single supply (with the negative supply set to ground) with no change in performance if the input and output are biased within the linear operation of the device. To change the circuit from split supply to a balanced, single-supply configuration, level shift all voltages by half the difference between the power-supply rails. An additional advantage of configuring an amplifier for single-supply operation is that the effects of PSRR are minimized because the low-supply rail is grounded. See the Single-Supply Op Amp Design Techniques application report for examples of single-supply designs. 24 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 OPA810 www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020 9 Application and Implementation Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information 9.1.1 Amplifier Gain Configurations The OPA810 is a classic voltage-feedback amplifier with each channel having two high-impedance inputs and a low-impedance output. Standard application circuits (as shown in Figure 9-1 and Figure 9-2) include the noninverting and inverting gain configurations. The DC operating point for each configuration is level-shifted by the reference voltage VREF that is typically set to midsupply in single-supply operation. VREF is often connected to ground in split-supply applications. VSIG VS+ VREF (1+RF/R G)VSIG VIN + VO VREF VREF RG VS± RF Figure 9-1. Noninverting Amplifier VS+ ±(RF/RG)VSIG VREF VSIG + VO VREF VIN VREF ± RG VS± RF Figure 9-2. Inverting Amplifier Equation 1 shows the closed-loop gain of an amplifier in a noninverting configuration. VO § RF · VIN ¨ 1 ¸ © RG ¹ VREF (1) Equation 2 shows the closed-loop gain of an amplifier in an inverting configuration. VO § RF · VIN ¨ ¸ © RG ¹ VREF (2) Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 25 OPA810 www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020 9.1.2 Selection of Feedback Resistors The OPA810 is a classic voltage feedback amplifier with each channel having two high-impedance inputs and a low-impedance output. Standard application circuits (as shown in Figure 9-3 and Figure 9-4) include the noninverting and inverting gain configurations. The DC operating point for each configuration is level-shifted by the reference voltage VREF which is typically set to midsupply in single-supply operation. VREF is often connected to ground in split-supply applications. VSIG VS+ VREF VIN (1+RF/RG)VSIG + VO VREF ± RG VS- VREF RF Figure 9-3. Noninverting Amplifier VS+ VREF VSIG VREF -(RF/RG)VSIG + VO VIN RG VREF ± VSRF Figure 9-4. Inverting Amplifier Equation 3 shows the closed-loop gain of an amplifier in noninverting configuration. VO § RF · VIN ¨ 1 ¸ © RG ¹ VREF (3) Equation 4 shows the closed-loop gain of an amplifier in an inverting configuration. VO § RF · VIN ¨ ¸ © RG ¹ VREF (4) The magnitude of the low-frequency gain is determined by the ratio of the magnitudes of the feedback resistor (RF) and the gain setting resistor RG. The order of magnitudes of the individual values of RF and RG offer a trade-off between amplifier stability, power dissipated in the feedback resistor network, and total output noise. The feedback network increases the loading on the amplifier output. Using large values of the feedback resistors reduces the power dissipated at the amplifier output. On the other hand, this increases the inherent voltage and amplifier current noise contribution seen at the output while lowering the frequency at which a pole occurs in the feedback factor (β). This pole causes a decrease in the phase margin at zero-gain crossover frequency and potential instability. Using small feedback resistors increases power dissipation and also degrades amplifier linearity due to a heavier amplifier output load. Figure 9-5 illustrates a representative schematic of the OPA810 in an inverting configuration with the input capacitors shown. 26 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 OPA810 www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020 CCM VS+ -(RF/RG)VSIG + VSIG CDIFF VIN VREF VO VREF ± RG CPCB CCM VS- RF Figure 9-5. Inverting Amplifier with Input Capacitors The effective capacitance at the amplifier inverting input pin is shown in Equation 5, which forms a pole in β at a cut-off frequency of Equation 6. CIN CCM CDIFF CPCB (5) where • • • CCM is the amplifier common-mode input capacitance CDIFF is the amplifier differential input capacitance CPCB is the PCB parasitic capacitance FC 1 2SRFCIN (6) 120 110 100 90 80 70 60 50 40 30 20 10 0 -10 -20 100 100 RF = 200 :, RG = 50 : RF = 10 k:, RG = 2.5 k: RF = 1 M:, RG = 250 k: 90 80 Phase (Degrees) Gain (dB) For low-power systems, greater the values of the feedback resistors, the earlier in frequency does the phase margin begin to reduce and cause instability. Figure 9-6 and Figure 9-7 illustrate the loop gain magnitude and phase plots, respectively, for the OPA810 simulation in TINA-TI configured as an inverting amplifier with values of feedback resistors varying by orders of magnitudes. 70 60 50 40 30 20 10 1k 10k 100k 1M Frequency (Hz) 10M 100M 0 100 D801 Figure 9-6. Loop-Gain vs Frequency for Circuit of Figure 9-5 RF = 200 :, RG = 50 : RF = 10 k:, RG = 2.5 k: RF = 1 M:, RG = 250 k: 1k 10k 100k 1M Frequency (Hz) 10M 100M D802 Figure 9-7. Loop-Gain Phase vs Frequency for Circuit of Figure 9-5 A lower phase margin results in peaking in the frequency response and lower bandwidth as Figure 9-8 shows, which is synonymous with overshoot and ringing in the pulse response results. The OPA810 offers a flat-band voltage noise density of 6.3 nV/√ Hz. TI recommends selecting an RF so the voltage noise contribution does not exceed that of the amplifier. Figure 9-9 shows the voltage noise density variation with value of resistance at 25°C. A 2-kΩ resistor exhibits a thermal noise density of 5.75 nV/√ Hz which is comparable to the flatband noise of the OPA810. Hence, TI recommends using an RF lower than 2 kΩ while being large enough to not dissipate Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 27 OPA810 www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020 excessive power for the output voltage swing and supply current requirements of the application. The Section 9.1.3 section shows a detailed analysis of the various contributors to noise. 30 1000 Voltage Noise Density (nV/—Hz) RF = 200 :, RG = 50 : RF = 10 k:, RG = 2.5 k: RF = 1 M:, RG = 250 k: Gain (dB) 20 10 0 -10 10k 100k 1M Frequency (Hz) 10M 100 10 1 0.1 10 100M D806 Figure 9-8. Closed-Loop Gain vs. Frequency for Circuit of Figure 9-5 100 1k 10k 100k Resistance (:) 1M 10M D803 Figure 9-9. Thermal Noise Density vs Resistance 9.1.3 Noise Analysis and the Effect of Resistor Elements on Total Noise The OPA810 provides a low input-referred broadband noise voltage density of 6.3 nV/√ Hz while requiring a low 3.7-mA quiescent supply current. To take full advantage of this low input noise, careful attention to the other possible noise contributors is required. Figure 9-10 shows the operational amplifier noise analysis model with all the noise terms included. In this model, all the noise terms are taken to be noise voltage or current density terms in nV/√ Hz or pA/√ Hz. ENI + EO IBN RS ± ERS 4kTR S 4kT RF RG RG 4kTR F IBI 4kT 1.6E 20 J at 290q K Figure 9-10. Operational Amplifier Noise Analysis Model The total output spot noise voltage is computed as the square root of the squared contributing terms to the output noise voltage. This computation adds all the contributing noise powers at the output by superposition, then calculates the square root to get back to a spot noise voltage. Figure 9-10 shows the general form for this output noise voltage using the terms shown in Equation 7. EO = (E 2 NI 2 ) ( + (IBNRS ) + 4kTRS NG2 + IBIRF 2 ) + 4kTRFNG (7) Dividing this expression by the noise gain (NG = 1 + RF / RG) shows the equivalent input referred spot noise voltage at the noninverting input; see Equation 8. 2 4kTRF æI R ö 2 EN = ENI2 + (IBNRS ) + 4kTRS + ç BI F ÷ + NG NG è ø 28 Submit Document Feedback (8) Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 OPA810 www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020 Substituting large resistor values into Equation 8 can quickly dominate the total equivalent input referred noise. A source impedance on the noninverting input of 2-kΩ adds a Johnson voltage noise term similar to that of the amplifier (6.3 nV/√ Hz). Table 9-1 compares the noise contributions from the various terms when the OPA810 is configured in a noninverting gain of 5 V/V as Figure 9-11 shows. Two cases are considered where the resistor values in case 2 are 10x the resistor values in case 1. The total output noise in case 1 is 34 nV/√ Hz while the noise in case 2 is 51.5 nV/√ Hz. The large value resistors in case 2 dilute the benefits of selecting a low noise amplifier like the OPA810. To minimize total system noise, reduce the size of the resistor values. This increases the amplifiers output load and results in a degradation of distortion performance. The increased loading increases the dynamic power consumption of the amplifier. The circuit designer must make the appropriate tradeoffs to maximize the overall performance of the amplifier to match the system requirements. VS+ = 5V + EO Case1: 200 Case2: 2 k RS ± VS- = -5V RG Case1: 250 Case2: 2.5 k RF Case1: 1 k Case2: 10 k Figure 9-11. Comparing Noise Contributors for Two Cases with the Amplifier in a Noninverting Gain of 5 V/V Table 9-1. Comparing Noise Contributions for the Circuit in Figure 9-11 CASE 1 CASE 2 NOISE SOURCE OUTPUT NOISE EQUATION Source resistor, RS ERS (1 + RF /RG) 1.82 nV/√ Hz 9.1 82.81 7.15 5.76 nV/√ Hz 28.8 829.44 31.29 Gain resistor, RG ERG (RF / RG) 2.04 nV/√ Hz 8.16 66.59 5.75 6.44 nV/√ Hz 25.76 663.58 25.03 Feedback resistor, RF ERF 4.07 nV/√ Hz 4.07 16.57 1.43 12.87 nV/√ Hz 12.87 165.64 6.25 Amplifier voltage noise, ENI ENI (1 + RF / RG) 6.3 nV/√ Hz 31.5 992.25 85.67 6.3 nV/√ Hz 31.5 992.25 37.43 Inverting current noise, IBI IBI (RF || RG) 5 fA/√ Hz 5.0E-3 — — 5 fA/√ Hz 50E-3 — — Noninverting current noise, IBN IBNRS (1 + RF/ RG) 5 fA/√ Hz 1.0E-3 — — 5 fA/√ Hz 10E-3 — — NOISE SOURCE VALUE VOLTAGE NOISE NOISE POWER CONTRIBUTIO CONTRIBUTIO CONTRIBUTIO N (%) N (nV/√ Hz) N (nV2/Hz) NOISE SOURCE VALUE VOLTAGE NOISE NOISE POWER CONTRIBUTIO CONTRIBUTIO CONTRIBUTIO N (%) N (nV/√ Hz) N (nV2/Hz) Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 29 OPA810 www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020 9.2 Typical Applications 9.2.1 Transimpedance Amplifier The high GBWP and low input voltage and current noise for the OPA810 make the device an ideal wideband transimpedance amplifier for moderate to high transimpedance gains. VBIAS +5 V Sup ply Decouplin g n ot shown OPA810 + Oscillosco pe with 50- Inputs CD 20 pF CPCB 0.3 pF -5 V RF 100 k CF + CPCB 1.03 pF Figure 9-12. Wideband, High-Sensitivity, Transimpedance Amplifier 9.2.1.1 Design Requirements Table 9-2 lists the design requirements for a high-bandwidth, high-gain transimpedance amplifier circuit. Table 9-2. Design Requirements PARAMETER DESIGN REQUIREMENT Target bandwidth > 2 MHz Transimpedance gain 100 kΩ Photodiode capacitance 20 pF 9.2.1.2 Detailed Design Procedure Designs that require high bandwidth from a large area detector with relatively high transimpedance gain benefit from the low input voltage noise of the OPA810. This input voltage noise is peaked up over frequency by the diode source capacitance, and can (in many cases) become the limiting factor to input sensitivity. The key elements to the design are the expected diode capacitance (CD) with the reverse bias voltage (VBIAS) applied, the desired transimpedance gain, RF, and the GBWP for the OPA810 (70 MHz). Figure 9-12 shows a transimpedance circuit with the parameters as described in Table 9-2. With these three variables set (and including the parasitic input capacitance for the OPA810 and the printed circuit board (PCB) added to CD), the feedback capacitor value (CF) can be set to control the frequency response. The Transimpedance Considerations for High-Speed Amplifiers application report discusses using high-speed amplifiers for transimpedance applications. Set the feedback pole according to Equation 9 in order to achieve a maximally-flat second-order Butterworth frequency response: 1 2S RF CF GBWP 4S RF CD (9) The input capacitance of the amplifier is the sum of the common-mode and differential capacitance (2.0 + 0.5) pF. The parasitic capacitance from the photodiode package and the PCB is approximately 0.3 pF. Using Equation 5 gives a total input capacitance of CD = 22.8 pF. From Equation 9, set the feedback pole at 1.55 MHz. Setting the pole at 1.55 MHz requires a total feedback capacitance of 1.03 pF. Equation 10 shows the approximate –3-dB bandwidth of the transimpedance amplifier circuit: 30 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 OPA810 www.ti.com f 3 dB SBOS799D – AUGUST 2019 – REVISED JULY 2020 GBWP / (2S RF CD ) Hz (10) Equation 10 estimates a closed-loop bandwidth of 2.19 MHz. Figure 9-13 and Figure 9-14 show the loop-gain magnitude and phase plots from the TINA-TI simulations of the transimpedance amplifier circuit of Figure 9-12. The 1/β gain curve has a zero from RF and CIN at 70 kHz and a pole from RF and CF cancelling the 1/β zero at 1.5 MHz, resulting in a 20-dB per decade rate-of-closure at the loop-gain crossover frequency (the frequency where AOL equals 1/β), ensuring a stable circuit. A phase margin of 62° is obtained with a closed-loop bandwidth of 3 MHz and a 100-kΩ transimpedance gain. 120 110 100 90 80 70 60 50 40 30 20 10 0 -10 100 100 AOL 1/E AOLE 90 80 Phase (Degrees) Gain (dB) 9.2.1.3 Application Curves 70 60 50 AOL 1/E AOLE 40 30 20 10 1k 10k 100k 1M Frequency (Hz) 10M 100M 0 100 D804 1k 10k 100k 1M Frequency (Hz) 10M 100M D805 Figure 9-13. Loop-Gain Magnitude vs Frequency Figure 9-14. Loop-Gain Phase vs Frequency for the for the Transimpedance Amplifier Circuit of Figure Transimpedance Amplifier Circuit of Figure 9-12 9-12 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 31 OPA810 www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020 9.2.2 High-Z Input Data Acquisition Front-End An ideal data acquisition system must measure a parameter without altering the measurand. When measuring a voltage or current from sensors with a large output impedance, an extremely high input impedance front-end with a pA range bias current is needed. Figure 9-15 shows an example circuit with the OPA810 used at the front-end. For systems with large input voltage attenuated with the MΩ range resistor divider, the OPA810 with its pA range bias currents adds negligible offset voltage and distortion because of the bias current induced resistor voltage drops. This circuit shows a funneling architecture with the OPA810 FET-input amplifier used as a unity-gain buffer, followed by attenuation to the ADS9110 5-V, full-scale input range and the ADC input drive using the THS4561 fully-differential amplifier (FDA). The THS4561 helps achieve better SNR and ENOB than a similar 5-V FDA, with a higher 12.6-V supply voltage and signal swings up to the ADC full-scale input range. As a result of the capacitive switching and current inrush on the ADC VREF input pin, a wide bandwidth amplifier such as the OPA837 is used with the OPA378 in a composite loop as a reference buffer. The OPA378, driven from the REF5050 5-V voltage reference, offers high precision and the OPA837 gives fast-settling performance for the ADC reference input drive. See the Reference Design Maximizing Signal Dynamic Range for True 10 Vpp Differential Input to 20 bit ADC design guide for more a detailed analysis of this high-Z front-end. CF 12V RF ± OPA810 + VIN+ R C 1.8V 1.8V AVDD DVDD RG 12V RS ± -12V VOCM 12V C CB ADS911 0 18-bit 2 MSPS THS456 1 + CCB RG VREF ± -0.2V OPA810 + VINR C RF R¶ R¶ -12V 5V CF 5V ± 12V REF505 0 5.0 V Reference RFIL T ± OPA837 OPA378 + + CFIL T Figure 9-15. High-Z Input Data Acquisition Front-End 32 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 OPA810 www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020 9.2.3 Multichannel Sensor Interface High-Z input amplifiers are particularly useful when interfaced with sensors that have relatively high output impedance. Such multichannel systems usually interface these sensors with the signal chain through a multiplexer. Figure 9-16 shows one such implementation using an amplifier for the interface with each sensor, and driving into an ADC through a multiplexer. An alternate circuit, shown in Figure 9-17, can use a single higher GBWP and fast-settling amplifier at the output of the multiplexer. This architecture gives rise to large signal transients when switching between channels, where the settling performance of the amplifier and maximum allowed differential input voltage limits signal chain performance and amplifier reliability, respectively. + + MUX ADC + Figure 9-16. Multichannel Sensor Interface Using Multiple Amplifiers OPA810 MUX ADC + Figure 9-17. Multichannel Sensor Interface Using a Single Higher GBWP Amplifier Figure 9-18 shows the output voltage and input differential voltage when a 8-V step is applied at the noninverting terminal of the OPA810 configured as a unity-gain buffer of Figure 9-17. Input and Output Voltage (V) 7.5 5 2.5 0 -2.5 VIN VO VIN,Diff -5 Time (10 ns/div) BD_M Figure 9-18. Large-Signal Transient Response Using the OPA810 Because of the fast input transient, the amplifier is slew-limited and the inputs cease to track each other (a maximum VIN,Diff of 7 V is shown in Figure 9-18) until the output reaches its final value and the negative feedback loop is closed. For standard amplifiers with a 0.7-V to 1.5-V maximum VIN,Diff rating, current-limiting resistors must be used in series with the input pins to protect the device from irreversible damage, which also limits the device frequency response. The OPA810 has built-in input clamps that allow the application of as much as 7 V of VIN,Diff, with no external resistors required and no damage to the device or a shift in performance specifications. Such an input-stage architecture, coupled with its fast settling performance, makes the OPA810 a good fit for multichannel sensor multiplexed systems. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 33 OPA810 www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020 10 Power Supply Recommendations The OPA810 is intended for operation on supplies ranging from 4.75 V to 27 V. The OPA810 can be operated on single-sided supplies, split and balanced bipolar supplies, or unbalanced bipolar supplies. Operating from a single supply can have numerous advantages. With the negative supply at ground, the DC errors resulting from the –PSRR term can be minimized. Typically, AC performance improves slightly at 10-V operation with minimal increase in supply current. Minimize the distance (< 0.1 in) from the power-supply pins to high-frequency, 0.01µF decoupling capacitors. A larger capacitor (2.2 µF typical) is used along with a high-frequency, 0.01-µF, supply-decoupling capacitor at the device supply pins. For single-supply operation, only the positive supply has these capacitors. When a split supply is used, use these capacitors from each supply to ground. If necessary, place the larger capacitors further from the device and share these capacitors among several devices in the same area of the printed circuit board (PCB). An optional supply decoupling capacitor across the two power supplies (for split-supply operation) reduces second harmonic distortion. 11 Layout 11.1 Layout Guidelines Achieving optimum performance with a high-frequency amplifier such as the OPA810 requires careful attention to board layout parasitics and external component types. The OPA2810EVM can be used as a reference when designing the circuit board. Recommendations that optimize performance include: 1. Minimize parasitic capacitance to any AC ground for all signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability—on the noninverting input, this capacitance can react with the source impedance to cause unintentional band-limiting. To reduce unwanted capacitance, open a window around the signal I/O pins in all ground and power planes around those pins. Otherwise, ground and power planes must be unbroken elsewhere on the board. 2. Minimize the distance (< 0.1 in) from the power-supply pins to high-frequency, 0.01-µF decoupling capacitors. At the device pins, do not allow the ground and power plane layout to be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections must always be decoupled with these capacitors. Larger (2.2-µF to 6.8-µF) decoupling capacitors, effective at lower frequency, must also be used on the supply pins. These capacitors can be placed somewhat farther from the device and shared among several devices in the same area of the PC board. 3. Careful selection and placement of external components preserve the high-frequency performance of the OPA810. Resistors must be a low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal film and carbon composition axially leaded resistors can also provide good highfrequency performance. Again, keep their leads and PCB trace length as short as possible. Never use wirewound type resistors in a high-frequency application. Because the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as noninverting input termination resistors, must also be placed close to the package. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal film or surface-mount resistors have approximately 0.2 pF in shunt with the resistor. For resistor values greater than 10 kΩ, this parasitic capacitance can add a pole or zero close to the GBWP of 70 MHz and subsequently affects circuit operation. Keep resistor values as low as possible and consistent with load driving considerations. Lowering the resistor values keeps the resistor noise terms low, and minimizes the effect of parasitic capacitance, however lower resistor values increase the dynamic power consumption because RF and RG become part of the amplifiers output load network. Transimpedance applications (see the Section 9.2.1 section) can use whatever feedback resistor is required by the application as long as the feedback compensation capacitor is set considering all parasitic capacitance terms on the inverting node. 34 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 OPA810 www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020 4. Connections to other wideband devices on the board can be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 mils to 100 mils) must be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RS for sufficient phase margin and stability. Low parasitic capacitive loads (< 10 pF) may not need an RS because the OPA810 is nominally compensated to operate with a 10-pF parasitic load. Higher parasitic capacitive loads without an RS are allowed with increase in signal gain (increasing the unloaded phase margin). If a long trace is required, and the 6-dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50-Ω environment is normally not necessary onboard, and a higher impedance environment improves distortion. With a characteristic board trace impedance defined based on board material and trace dimensions, a matching series resistor into the trace from the output of the OPA810 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input impedance of the destination device—this total effective impedance must be set to match the trace impedance. If the 6-dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case and set the series resistor value to obtain sufficient phase margin and stability. This does not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, the signal attenuates because of the voltage divider formed by the series output into the terminating impedance. 5. Take care to design the PCB layout for optimal thermal dissipation. For the extreme case of 125°C operating ambient, using the approximate 134.8°C/W for the SOIC package, and an internal power of 24-V supply × 4.7-mA 125°C supply current gives a maximum internal power dissipation of 113 mW. This power gives a 15°C increase from ambient to junction temperature. Load power adds to this value and this dissipation must also be calculated to determine the worst-case safe operating point. 6. Socketing a high-speed device such as the OPA810 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network that can almost make achieving a smooth, stable frequency response impossible. Best results are obtained by soldering the OPA810 onto the board. 11.1.1 Thermal Considerations The OPA810 does not require heat sinking or airflow in most applications. Maximum allowed junction temperature sets the maximum allowed internal power dissipation. Do not allow the maximum junction temperature to exceed 150°C. Operating junction temperature (TJ) is given by TA + PD × θJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is the specified no-load supply current times the total supply voltage across the part. PDL depends on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to half of either supply voltage (for equal split-supplies). Under this condition PDL = VS 2 / (4 × RL) where RL includes feedback network loading. The power in the output stage and not into the load that determines internal power dissipation. As a worst-case example, compute the maximum TJ using a DCK (SC70 package) configured as a unity gain buffer, operating on ±12-V supplies at an ambient temperature of 25°C and driving a grounded 500-Ω load. PD = 24 V × 4.7 mA + 122 /(4 × 500 Ω) = 184.8 mW Maximum TJ = 25°C + (0.185 W × 190.8°C/W) = 60°C, which is well below the maximum allowed junction temperature of 150oC. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 35 OPA810 www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020 11.2 Layout Example VS+ Representative schematic of a single channe l CBYP RS + ± CBYP VS- RG RF Gro und and power plan e e xist on inne r la yer s. Remove G ND and Power plan e und er o utp ut and inverting pins to minimize stray PCB capacitance 1 8 Place inpu t resistor close to pin 2 to minimize p arasitic ca pacita nce 2 7 Place feedback r esistor on the bottom of PCB be tween pin s 2 and 6 3 6 4 5 Gro und and power plan e re mo ved from in ner layers. Gro und fill on outer layers a lso removed CBYP RG RS Place bypass capacitors close to power pins Place bypass capacitors close to power pins Place output r esi stors close to output pin to minimize para sitic capa citance Remove G ND and Power plan e und er o utp ut and inverting pins to minimize stray PCB capacitance CBYP Figure 11-1. Layout Recommendation 36 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 OPA810 www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020 12 Device and Documentation Support 12.1 Third-Party Products Disclaimer TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE. 12.2 Documentation Support 12.2.1 Related Documentation For related documentation see the following: • Texas Instruments, OPA2810 Dual-Channel, 27-V, Rail-to-Rail Input/Output FET-Input Operational Amplifier data sheet. • Texas Instruments, ADS9110 18-Bit, 2-MSPS, 15-mW, SAR ADC With Enhanced Performance Features data sheet • Texas Instruments, THS4561 Low-Power, High Supply Range, 70-MHz, Fully Differential Amplifier data sheet • Texas Instruments, OPAx837 Low-Power, Precision, 105-MHz, Voltage-Feedback Op Amp data sheet • Texas Instruments, OPAx378 Low-Noise, 900kHz, RRIO, Precision Operational Amplifier Zerø-Drift Series data sheet • Texas Instruments, REF50xx Low-Noise, Very Low Drift, Precision Voltage Reference data sheet • Texas Instruments, OPA2810DGK Evaluation Module user's guide • Texas Instruments, Single-Supply Op Amp Design Techniques application report • Texas Instruments, Transimpedance Considerations for High-Speed Amplifiers application report • Texas Instruments, Blog: What you need to know about transimpedance amplifiers – part 1 • Texas Instruments, Blog: What you need to know about transimpedance amplifiers – part 2 • Texas Instruments, Noise Analysis for High-Speed Op Amps application report • Texas Instruments, TINA model and simulation tool • Texas Instruments, TIDA-01057 Reference Design Maximizing Signal Dynamic Range for True 10 Vpp Differential Input to 20 bit ADC 12.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 12.4 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 12.5 Trademarks TI E2E™ is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 12.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 37 OPA810 www.ti.com SBOS799D – AUGUST 2019 – REVISED JULY 2020 12.7 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 38 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated Product Folder Links: OPA810 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) OPA810IDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 1ZQ5 OPA810IDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 1ZQ5 OPA810IDCKR ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 1GG OPA810IDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 810 OPA810IDT ACTIVE SOIC D 8 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 810 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of