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P82B96
SCPS144C – MAY 2006 – REVISED MAY 2015
P82B96 I2C Compatible Dual Bidirectional Bus Buffer
1 Features
3 Description
•
The P82B96 device is a bus buffer that supports
bidirectional data transfer between an I2C bus and a
range of other bus configurations with different
voltage and current levels.
1
•
•
•
•
•
•
•
Operating Power-Supply Voltage Range
of 2 V to 15 V
Can Interface Between I2C Buses Operating at
Different Logic Levels (2 V to 15 V)
Longer Cables by allowing bus capacitance of
400 pF on Main Side (Sx/Sy) and 4000 pF on
Transmission Side (Tx/Ty)
Outputs on the Transmission Side (Tx/Ty) Have
High Current Sink Capability for Driving LowImpedance or High-Capacitive Buses
Interface With Optoelectrical Isolators and Similar
Devices That Need Unidirectional Input and
Output Signal Paths by Splitting I2C Bus Signals
Into Pairs of Forward (Tx/Ty) and Reverse (Rx/Ry)
Signals
400-kHz Fast I2C Bus Operation Over at Least
20 Meters of Wire
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
2 Applications
•
•
•
•
One of the advantages of the P82B96 is that it
supports longer cables/traces and allows for more
devices per I2C bus because it can isolate bus
capacitance such that the total loading (devices and
trace lengths) of the new bus or remote I2C nodes
are not apparent to other I2C buses (or nodes). The
restrictions on the number of I2C devices in a system
due to capacitance, or the physical separation
between them, are greatly improved.
The device is able to provide galvanic isolation
(optocoupling) or use balanced transmission lines
(twisted pairs), because separate directional Tx and
Rx signals are provided. The Tx and Rx signals may
be connected directly (without causing bus latching),
to provide an bidirectional signal line with I2C
properties (open-drain driver). Likewise, the Ty and
Ry signals may also be connected together to provide
an bidirectional signal line with I2C properties (opendrain driver). This allows for a simple communication
design, saving design time and costs.
Device Information(1)
HDMI DDC
Long I2C Communication
Galvanic I2C Isolation
Industrial Communications
PART NUMBER
PACKAGE
P82B96
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
PDIP (8)
9.81 mm × 6.35 mm
TSSOP (8)
3.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Long-Distance I2C Communications
Main Enclosure
Remote-Control Enclosure
12 V
12 V
3.3–5 V
3.3–5 V
Long Cables
SCL
SCL
3.3–5 V
12 V
3.3–5 V
SDA
SDA
P82B96
P82B96
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
P82B96
SCPS144C – MAY 2006 – REVISED MAY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
8
1
1
1
2
3
4
5
Absolute Maximum Ratings ..................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics: VCC = 2.3 V to 2.7 V ........ 6
Electrical Characteristics: VCC = 3 V to 3.6 V ........... 7
Electrical Characteristics: VCC = 4.5 V to 5.5 V ........ 8
Electrical Characteristics: VCC = 15 V....................... 9
Switching Characteristics ........................................ 10
Typical Characteristics .......................................... 11
Parameter Measurement Information ................ 12
9
Detailed Description ............................................ 13
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
13
13
14
14
10 Application and Implementation........................ 15
10.1 Application Information.......................................... 15
10.2 Typical Applications .............................................. 17
11 Power Supply Recommendations ..................... 21
12 Layout................................................................... 21
12.1 Layout Guidelines ................................................. 21
12.2 Layout Example .................................................... 21
13 Device and Documentation Support ................. 22
13.1
13.2
13.3
13.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
22
14 Mechanical, Packaging, and Orderable
Information ........................................................... 22
4 Revision History
Changes from Revision B (July 2007) to Revision C
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Changed VCC pins to VCC pins in pinout diagrams................................................................................................................ 4
2
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P82B96
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SCPS144C – MAY 2006 – REVISED MAY 2015
5 Description (continued)
Two or more Sx or Sy I/Os must not be connected to each other on the same node. The P82B96 design does
not support this configuration. Bidirectional I2C signals do not have a direction control pin so, instead, slightly
different logic low-voltage levels are used at Sx/Sy to avoid latching of this buffer. A standard I2C low applied at
the Rx/Ry of a P82B96 is propagated to Sx/Sy as a buffered low with a slightly higher voltage level. If this special
buffered low is applied to the Sx/Sy of another P82B96, the second P82B96 does not recognize it as a standard
I2C bus low and does not propagate it to its Tx/Ty output. The Sx/Sy side of P82B96 may not be connected to
similar buffers that rely on special logic thresholds for their operation.
The Sx/Sy side of the P82B96 is intended for I2C logic voltage levels of I2C master and slave devices or Tx/Rx
signals of a second P82B96, if required. If Rx and Tx are connected, Sx can function as either the SDA or SCL
line. Similarly, if Ry and Ty are connected, Sy can function as either the SDA or SCL line. There are no
restrictions on the interconnection of the Tx/Rx and Ty/Ry I/O pins to other P82B96s, for example in a star or
multi-point configuration (multiple P82B96 devices share the same Tx/Rx and Ty/Ry nodes) with the Tx/Rx and
Ty/Ry I/O pins on the common bus, and the Sx/Sy side connected to the line-card slave devices.
In any design, the Sx pins of different devices should never be linked, because the resulting system would be
very susceptible to induced noise and would not support all I2C operating modes.
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P82B96
SCPS144C – MAY 2006 – REVISED MAY 2015
www.ti.com
6 Pin Configuration and Functions
P Package
8-Pin PDIP
(Top View)
D Package
8-Pin SOIC
(Top View)
Sx
1
8
VCC
Rx
2
7
Tx
3
GND
4
1
8
Sy
Sx
Rx
2
7
VCC
Sy
6
Ry
Tx
3
6
Ry
5
Ty
GND
4
5
Ty
DGK Package
8-Pin VSSOP
(Top View)
PW Package
8-Pin TSSOP
(Top View)
Sx
Rx
Tx
GND
8
7
6
5
1
2
3
4
Sx
Rx
Tx
GND
VCC
Sy
Ry
Ty
1
2
3
4
8
7
6
5
VCC
Sy
Ry
Ty
Pin Functions
PIN
NO.
NAME
I/O
Serial data bus or SDA. Connect to VCC of I2C master through a pullup resistor.
1
Sx
2
Rx
I
Receive signal. Connect to VCC of P82B96 through a pullup resistor.
3
Tx
O
Transmit signal. Connect to VCC of P82B96 through a pullup resistor.
4
GND
—
Ground
5
Ty
O
Transmit signal. Connect to VCC of P82B96 through a pullup resistor.
6
Ry
I
Receive signal. Connect to VCC of P82B96 through a pullup resistor.
7
Sy
I/O
8
VCC
I
4
I/O
DESCRIPTION
Serial clock bus or SCL. Connect to VCC of I2C master through a pullup resistor.
Supply voltage
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P82B96
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SCPS144C – MAY 2006 – REVISED MAY 2015
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
–0.3
18
V
Sx or Sy (SDA or SCL)
–0.3
18
Rx or Ry
–0.3
18
Sx or Sy (SDA or SCL)
–0.3
18
Tx or Ty
–0.3
18
VCC
Supply voltage on VCC pin
VI
Voltage on buffered input
VO
Voltage on buffered output
IO
Continuous output current
ICC
Continuous current through VCC or GND
250
mA
TA
Operating free-air temperature
–40
85
°C
Tstg
Storage temperature
–55
125
°C
(1)
Sx or Sy
250
Tx or Ty
250
V
V
mA
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human Body Model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±3500
Charged-Device Model (CDM), per JEDEC specification JESD22C101 (2)
±1000
Machine Model (MM), per JEDEC specification JESD22-A115-A
±200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
VCC
Supply voltage
IOL
Low-level output current
VIOmax
Maximum input/output voltage level
VILdiff
Low-level input voltage difference
TA
Operating free-air temperature
MIN
MAX
2
15
Sx, Sy
VSx, VSy = 1 V, VRx, VRy ≤ 0.42 V
3
Tx, Ty
VSx, VSy = 0.4 V, VTx, VTy = 0.4 V
30
Sx, Sy
VTx, VTy = 0.4 V
15
Tx, Ty
VSx, VSy = 0.4 V
15
Sx, Sy
UNIT
V
mA
V
0.4
V
85
°C
–40
7.4 Thermal Information
P82B96
THERMAL METRIC
RθJA
(1)
Junction-to-ambient thermal resistance
D (SOIC)
DGK (VSSOP)
P (PDIP)
PW (TSSOP)
8 PINS
8 PINS
8 PINS
8 PINS
UNIT
109.1
174.3
53.5
173.5
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
61.6
63
44.4
57.6
°C/W
RθJB
Junction-to-board thermal resistance
48.6
94.2
30.6
101.8
°C/W
ψJT
Junction-to-top characterization parameter
19.6
8.1
22.9
5.3
°C/W
ψJB
Junction-to-board characterization parameter
48.2
92.8
30.5
100.2
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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P82B96
SCPS144C – MAY 2006 – REVISED MAY 2015
www.ti.com
7.5 Electrical Characteristics: VCC = 2.3 V to 2.7 V
VCC = 2.3 V to 2.7 V, voltages are specified with respect to GND (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
ΔV/ΔTIN
Temperature coefficient of
input thresholds
Sx, Sy
VOL
Low-level output voltage
Sx, Sy
ΔV/ΔTOUT
Temperature coefficient of
output low levels (3)
Sx, Sy
ICC
Quiescent supply current
ΔICC
Additional supply current
per pin low
Dynamic output sink
capability on I2C bus
IIOS
Sx, Sy
Tx, Ty
Leakage current
on buffered bus
Input current
from buffered bus
II
Leakage current
on buffered bus input
Sx, Sy
Rx, Ry
VIT
ISx, ISy = 3 mA
ISx, ISy = 0.2 mA
0.8
0.67
ISx, ISy = 0.2 mA
VSx, VSy > 2 V,
VRx, VRy = low
7
VSx, VSy = 2.5 V,
VRx, VRy = high
VTx, VTy > 1 V,
VSx, VSy = low on
I2C bus = 0.4 V
0.88
0.73
MAX
mV/°C
1
0.79
See
(2)
See
(2)
V
mV/°C
1.8
2
mA
1.7
2.75
3
mA
18
0.1
60
5.5
1
mA
1
100
60
–1
1
Bus low, VRx,
VRy = 0.4 V
–1
1
1
1.5
Input logic level low
threshold (4)
on normal I2C bus
0.65
0.6
1
0.7
0.65
0.58 x
VCC
1
See
(2)
See
(2)
μA
mA
Bus low, VRx,
VRy = high
Input logic level high
threshold (4)
on normal I2C bus
UNIT
0.9
μA
μA
V
0.58 x
VCC
0.5 x
VCC
Input threshold
0.42 x
VCC
Input logic level low
VIOdiff
Input/output logic level
difference (5)
Sx, Sy
(VSx output low
at 3 mA) –
(VSx input high max)
for I2C applications
100
VIOrel
VCC voltage at which all
buses are released
Sx, Sy
Tx, Ty
Sx, Sy are low, VCC
ramping, voltage on
Tx, Ty lowered until
released
1
ΔV/ΔTREL
Temperature coefficient of release
voltage
–4
Cin
Input capacitance
2.5
6
MIN
0.1
Input logic level high
(1)
(2)
(3)
(4)
(5)
MAX
VTx, VTy = VCC =
2.5 V,
VSx, VSy = high
Input threshold
Rx, Ry
TA = –40°C to 85°C
–1.8
VRx, VRy = VCC
Sx, Sy
TYP
(1)
–2
Tx, Ty
IIOT
Input current from I2C bus
MIN
Sx = Sy = VCC
Leakage current on I2C bus
Dynamic output sink
capability on buffered bus
TA = 25°C
Rx, Ry
150
0.42 x
VCC
100
mV
1
V
mV/°C
4
4
pF
Typical value is at VCC = 2.5 V, TA = 25°C
See the Typical Characteristics section of this data sheet.
The output logic low depends on the sink current.
The input logic threshold is independent of the supply voltage.
The minimum value requirement for pullup current, 200 μA, ensures that the minimum value for VSX output low always exceeds the
minimum VSx input high level to eliminate any possibility of latching. The specified difference is specified by design within any device.
While the tolerances on absolute levels allow a small probability that the low from one Sx output is recognized by an Sx input of another
P82B96, this has no consequences for normal applications.
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7.6 Electrical Characteristics: VCC = 3 V to 3.6 V
VCC = 3 V to 3.6 V, voltages are specified with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ΔV/ΔTIN
Temperature
coefficient of
input thresholds
Sx, Sy
VOL
Low-level output
voltage
Sx, Sy
ΔV/ΔTOUT
Temperature
coefficient of
output low
levels (3)
Sx, Sy
ICC
Quiescent supply current
ΔICC
Additional supply
current per pin
low
Dynamic output
sink capability
on I2C bus
IIOS
IIOT
ISx, ISy = 0.2 mA
0.8
0.67
ISx, ISy = 0.2 mA
VSx, VSy > 2 V, VRx, VRy = low
Dynamic output
sink capability
on buffered bus
VTx, VTy > 1 V,
VSx, VSy = low on I2C bus =
0.4 V
Tx, Ty
Sx, Sy
MIN
0.88
0.73
7
UNIT
MAX
mV/°C
1
0.79
See
(2)
See
(2)
V
mV/°C
0.9
1.8
2
mA
1.7
2.75
3
mA
18
5.7
mA
0.1
60
1
μA
1
100
60
mA
VTx, VTy = VCC = 3.3 V,
VSx, VSy = high
0.1
Bus low, VRx, VRy = high
–1
1
Bus low, VRx, VRy = 0.4 V
–1
1
1
1.5
1
μA
1
μA
Rx, Ry
VRx, VRy = VCC
Sx, Sy
Input threshold
Input logic-level high
threshold (4) on normal I2C bus
Input logic-level low
threshold (4) on normal I2C bus
Input logic level high
Rx, Ry
0.65
0.6
0.7
0.65
0.58 x
VCC
Input threshold
See
(2)
See
(2)
V
0.58 x VCC
0.5 x VCC
0.42 x
VCC
Input logic level low
VIOdiff
Input/output logic
level difference (5)
Sx, Sy
(VSx output low at 3 mA) –
(VSx input high max) for I2C
applications
VIOrel
VCC voltage at
which all buses
are released
Sx, Sy
Tx, Ty
Sx, Sy are low, VCC ramping,
voltage on Tx, Ty lowered until
released
ΔV/ΔTREL
Temperature coefficient of
release voltage
–4
Cin
Input capacitance Rx, Ry
2.5
(1)
(2)
(3)
(4)
(5)
MAX
–1.8
Sx = Sy = VCC
VSx, VSy = 5 V,
VRx, VRy = high
Leakage current
on buffered bus
input
TYP
TA = –40°C to 85°C
Sx, Sy
Input current
from buffered bus
VIT
ISx, ISy = 3 mA
Tx, Ty
Leakage current
on buffered bus
II
MIN
(1)
–2
Leakage current
on I2C bus
Input current
from I2C bus
TA = 25°C
100
150
0.42 x
VCC
100
1
mV
1
V
mV/°C
4
4
pF
Typical value is at VCC = 3.3 V, TA = 25°C
See the Typical Characteristics section of this data sheet.
The output logic low depends on the sink current.
The input logic threshold is independent of the supply voltage.
The minimum value requirement for pullup current, 200 μA, ensures that the minimum value for VSX output low always exceeds the
minimum VSx input high level to eliminate any possibility of latching. The specified difference is specified by design within any device.
While the tolerances on absolute levels allow a small probability that the low from one Sx output is recognized by an Sx input of another
P82B96, this has no consequences for normal applications.
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P82B96
SCPS144C – MAY 2006 – REVISED MAY 2015
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7.7 Electrical Characteristics: VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V, voltages are specified with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ΔV/ΔTIN
Temperature
coefficient of input Sx, Sy
thresholds
VOL
Low-level output
voltage
Sx, Sy
ΔV/ΔTOUT
Temperature
coefficient of
output low
levels (3)
Sx, Sy
ICC
Quiescent supply current
ΔICC
Additional supply
current
per pin low
Dynamic output
sink capability
on I2C bus
IIOS
IIOT
Sx, Sy
ISx, ISy = 0.2 mA
0.67
VSx, VSy > 2 V,
VRx, VRy = low
VTx, VTy > 1 V,
VSx, VSy = low on I2C bus =
0.4 V
Tx, Ty
Sx, Sy
TYP
MIN
MAX
0.88
0.73
7
1
0.79
See
(2)
See
(2)
V
mV/°C
0.9
1.8
2
mA
1.7
2.75
3
mA
18
0.1
60
UNIT
mV/°C
6
1
mA
1
100
60
0.1
Bus low, VRx, VRy = high
–1
1
Bus low, VRx, VRy = 0.4 V
–1
1
1
1.5
1
μA
mA
VTx, VTy = VCC = 5 V,
VSx, VSy = high
VRx, VRy = VCC
Input threshold
Input logic-level high
threshold (4)
on normal I2C bus
Input logic-level low
threshold (4)
on normal I2C bus
Input logic level high
Rx, Ry
0.65
0.6
1
μA
μA
Input/output logic
level difference (5)
Sx, Sy
(VSx output low at 3 mA) –
(VSx input high max) for I2C
applications
VIOrel
VCC voltage at
which all buses
are released
Sx, Sy
Tx, Ty
Sx, Sy are low, VCC
ramping, voltage on Tx, Ty
lowered until released
See
(2)
See
(2)
V
0.58 x
VCC
Input threshold
VIOdiff
0.7
0.65
0.58 x VCC
0.5 x VCC
0.42 x
VCC
Input logic level low
8
MAX
Rx, Ry
Sx, Sy
(1)
(2)
(3)
(4)
(5)
TA = –40°C to 85°C
–1.8
Sx = Sy = VCC
Dynamic output
sink capability
on buffered bus
Leakage current
on buffered bus
input
0.8
ISx, ISy = 0.2 mA
VSx, VSy = 5 V,
VRx, VRy = high
Input current
from buffered bus
VIT
ISx, ISy = 3 mA
Tx, Ty
Leakage current
on buffered bus
II
MIN
(1)
–2
Leakage current
on I2C bus
Input current
from I2C bus
TA = 25°C
100
1
150
0.42 x
VCC
100
1
mV
V
Typical value is at VCC = 5 V, TA = 25°C
See the Typical Characteristics section of this data sheet.
The output logic low depends on the sink current.
The input logic threshold is independent of the supply voltage.
The minimum value requirement for pullup current, 200 μA, ensures that the minimum value for VSX output low always exceeds the
minimum VSx input high level to eliminate any possibility of latching. The specified difference is specified by design within any device.
While the tolerances on absolute levels allow a small probability that the low from one Sx output is recognized by an Sx input of another
P82B96, this has no consequences for normal applications.
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SCPS144C – MAY 2006 – REVISED MAY 2015
Electrical Characteristics: VCC = 4.5 V to 5.5 V (continued)
VCC = 4.5 V to 5.5 V, voltages are specified with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C
MIN
TYP
(1)
ΔV/ΔTREL
Temperature coefficient of
release voltage
–4
Cin
Input capacitance
2.5
Rx, Ry
TA = –40°C to 85°C
MAX
MIN
UNIT
MAX
mV/°C
4
4
pF
7.8 Electrical Characteristics: VCC = 15 V
VCC = 15 V, voltages are specified with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
ΔV/ΔTIN
Temperature
coefficient of
input thresholds
Sx, Sy
VOL
Low-level output
voltage
Sx, Sy
ΔV/ΔTOUT
Temperature
coefficient of
output low
levels (3)
Sx, Sy
ICC
Quiescent supply
current
ΔICC
Additional supply
current
per pin low
IIOS
IIOT
Dynamic output
sink capability
on I2C bus
0.67
ISx, ISy = 0.2 mA
VSx, VSy > 2 V,
VRx, VRy = low
VSx, VSy = 15 V,
VRx, VRy = high
Dynamic output
sink capability
on buffered bus
VTx, VTy > 1 V,
VSx, VSy = low on I2C bus
= 0.4 V
Tx, Ty
Sx, Sy
Input current
from buffered bus
Leakage current
on buffered bus
input
MIN
MAX
0.88
0.73
7
1
0.79
See
(2)
See
(2)
V
mV/°C
0.9
1.8
2
mA
1.7
2.75
3
mA
18
0.1
60
UNIT
mV/°C
–1.8
6.5
1
mA
1
100
60
0.1
Bus low, VRx, VRy = high
–1
1
Bus low, VRx, VRy = 0.4 V
–1
1
1
1.5
1
μA
mA
VTx, VTy = VCC = 15 V,
VSx, VSy = high
VRx, VRy = VCC
Input threshold
Rx, Ry
Input logic-level high
threshold (4)
on normal I2C bus
0.65
Input logic-level high
threshold (4)
on normal I2C bus
0.6
Input logic level high
0.58 x
VCC
1
μA
μA
0.7
0.65
See
(2)
See
(2)
V
Input threshold
Input logic level low
(1)
(2)
(3)
(4)
TA = –40°C to 85°C
MAX
Rx, Ry
Sx, Sy
VIT
ISx, ISy = 0.2 mA
0.8
Tx, Ty
Leakage current
on buffered bus
II
ISx, ISy = 3 mA
Sx = Sy = VCC
Sx, Sy
TYP (1)
–2
Leakage current
on I2C bus
Input current
from I2C bus
TA = 25°C
MIN
0.58 x VCC
0.5 x VCC
0.42 x
VCC
0.42 x
VCC
Typical value is at VCC = 15 V, TA = 25°C
See the Typical Characteristics section of this data sheet.
The output logic low depends on the sink current.
The input logic threshold is independent of the supply voltage.
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Electrical Characteristics: VCC = 15 V (continued)
VCC = 15 V, voltages are specified with respect to GND (unless otherwise noted)
PARAMETER
TA = 25°C
TEST CONDITIONS
MIN
TYP
VIOdiff
Input/output logic
level difference (5)
Sx, Sy
(VSx output low at 3 mA) –
(VSx input high max) for
I2C applications
VIOrel
VCC voltage at
which all buses
are released
Sx, Sy
Tx, Ty
Sx, Sy are low, VCC
ramping, voltage on Tx,
Ty lowered until released
ΔV/ΔTREL
Temperature coefficient of
release voltage
–4
Cin
Input capacitance Rx, Ry
2.5
(5)
100
TA = –40°C to 85°C
(1)
MAX
MIN
150
UNIT
MAX
100
1
mV
1
V
mV/°C
4
4
pF
The minimum value requirement for pullup current, 200 μA, ensures that the minimum value for VSX output low always exceeds the
minimum VSx input high level to eliminate any possibility of latching. The specified difference is specified by design within any device.
While the tolerances on absolute levels allow a small probability that the low from one Sx output is recognized by an Sx input of another
P82B96, this has no consequences for normal applications.
7.9 Switching Characteristics
VCC = 5 V, TA = 25°C, no capacitive loads, voltages are specified with respect to GND (unless otherwise noted)
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
TEST CONDITIONS
TYP UNIT
tpzl
Buffer delay time on falling
input
VSx (or VSy) = input switching
threshold
VTx (or VTy) output falling
50% of VLOAD (1)
RTx pullup = 160 Ω,
CTx = 7 pF + board
trace capacitance
70
ns
tplz
Buffer delay time on rising
input
VSx (or VSy) = input switching
threshold
VTx (or VTy) output
reaching 50% of VLOAD
RTx pullup = 160 Ω,
CTx = 7 pF + board
trace capacitance
90
ns
tpzl
Buffer delay time on falling
input
VRx (or VRy) = input switching
threshold
VSx (or VSy) output falling
50% of VLOAD (3)
RSx pullup = 1500 Ω,
CTx = 7 pF + board
trace capacitance
250
ns
tplz
Buffer delay time on rising
input
VRx (or VRy) = input switching
threshold
VSx (or VSy) output
reaching 50% of VLOAD
RSx pullup = 1500 Ω,
CTx = 7 pF + board
trace capacitance
270
ns
(1)
(2)
(3)
(4)
10
The
The
The
The
(2)
(4)
fall time of VTx from 5 V to 2.5 V in the test is approximately 15 ns.
rise time of VTx from 0 V to 2.5 V in the test is approximately 20 ns.
fall time of VSx from 5 V to 2.5 V in the test is approximately 50 ns.
rise time of VSx from 0.9 V to 2.5 V in the test is approximately 70 ns.
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7.10 Typical Characteristics
1200
800
600
Typical
0
25
Typical
800
600
Minimum
400
-50 –25
Maximum
1000
Maximum
VOL – mV
VOL – mV
1000
Minimum
400
-50 –25
50 75 100 125
0
Figure 2. VOL at Sx vs Junction Temperature, IOL = 3 mA
1000
1000
800
800
VIH(min) – mV
VIL(max) – mV
Figure 1. VOL at Sx vs Junction Temperature, IOL = 0.2 mA
600
400
0
50 75 100 125
Tj – °C
Tj – °C
200
-50 –25
25
600
400
200
-50 –25
25 50 75 100 125
Tj – °C
0
25 50 75 100 125
Tj – °C
Figure 4. VIH(min) at Sx vs Junction Temperature
Figure 3. VIL(max) at Sx vs Junction Temperature
1400
VCC(max) – mV
1200
1000
800
600
400
-50 –25
0
25 50 75 100 125
Tj – °C
Figure 5. VCC(max) vs Junction Temperature
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8 Parameter Measurement Information
VCC
VIN
VCC
VOUT
PULSE
GENERATOR
RL = 160 to 1500 W
S1
DUT
GND
CL = Probe and jig capacitance
(see Note A)
RT
TEST
S1
tPLZ/tPZL
VCC
TEST CIRCUIT FOR OPEN-DRAIN OUTPUT
VCC
0.6 V
0V
Sx or Sy
tPZL
tPLZ
VCC
0.5 ´ VCC
Tx or Ty
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
A.
CL includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
Figure 6. Test Circuit and Voltage Waveforms
12
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9 Detailed Description
9.1 Overview
The P82B96 is a bus buffer that supports bidirectional data transfer between an I2C bus and a range of other bus
configurations with different voltage and current levels.
One of the advantages of the P82B96 is that it supports longer cables/traces and allows for more devices per I2C
bus because it can isolate bus capacitance such that the total loading (devices and trace lengths) of the new bus
or remote I2C nodes are not apparent to other I2C buses (or nodes). The restrictions on the number of I2C
devices in a system due to capacitance, or the physical separation between them, are greatly improved.
The P82B96 is able to provide galvanic isolation (optocoupling) or use balanced transmission lines (twisted
pairs), because separate directional Tx and Rx signals are provided. The Tx and Rx signals may be connected
directly (without causing bus latching), to provide an bidirectional signal line with I2C properties (open-drain
driver). Likewise, the Ty and Ry signals may also be connected together to provide an bidirectional signal line
with I2C properties (open-drain driver). This allows for a simple communication design, saving design time and
costs.
Two or more Sx or Sy I/Os must not be connected to each other on the same node. The P82B96 design does
not support this configuration. Bidirectional I2C signals do not have a direction control pin so, instead, slightly
different logic low-voltage levels are used at Sx/Sy to avoid latching of this buffer. A standard I2C low applied at
the Rx/Ry of a P82B96 is propagated to Sx/Sy as a buffered low with a slightly higher voltage level. If this special
buffered low is applied to the Sx/Sy of another P82B96, the second P82B96 does not recognize it as a standard
I2C bus low and does not propagate it to its Tx/Ty output. The Sx/Sy side of P82B96 may not be connected to
similar buffers that rely on special logic thresholds for their operation.
The Sx/Sy side of the P82B96 is intended for I2C logic voltage levels of I2C master and slave devices or Tx/Rx
signals of a second P82B96, if required. If Rx and Tx are connected, Sx can function as either the SDA or SCL
line. Similarly, if Ry and Ty are connected, Sy can function as either the SDA or SCL line. There are no
restrictions on the interconnection of the Tx/Rx and Ty/Ry I/O pins to other P82B96s, for example in a star or
multi-point configuration (multiple P82B96 devices share the same Tx/Rx and Ty/Ry nodes) with the Tx/Rx and
Ty/Ry I/O pins on the common bus, and the Sx/Sy side connected to the line-card slave devices.
In any design, the Sx pins of different devices should never be linked, because the resulting system would be
very susceptible to induced noise and would not support all I2C operating modes.
9.2 Functional Block Diagram
VCC (2–15 V)
8
Sx (SDA)
3
1
2
Sy (SCL)
5
7
6
Tx (TxD, SDA)
Rx (RxD, SDA)
Ty (TxD, SCL)
Ry (RxD, SCL)
P82B96
4
GND
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9.3 Feature Description
9.3.1 Sx and Sy
The I2C pins, Sx and Sy, are designed to interface directly with an I2C bus. The logic threshold-voltage levels on
the I2C bus are independent of the supply VCC. The maximum I2C bus supply voltage is 15 V, and the specified
static sink current is 3 mA.
Sx and Sy have two identical buffers. Each buffer is made up of two logic signal paths. The first one, named Tx
or Ty, is a forward path from the I2C interface pin, which drives the buffered bus. The second one, named Rx or
Ry, is a reverse signal path from the buffered bus input to drive the I2C bus interface.
There are two purposes for these paths: to sense the voltage state of the I2C pin (Sx or Sy) and transmit this
state to Tx or Ty, respectively, and to detect the state of the Rx or Ry and pull the I2C pin low when Rx or Ry is
low.
9.3.2 Tx and Ty
Tx and Ty are open-collector outputs without ESD protection diodes to VCC. Each pin may be connected through
a pullup resistor to a supply voltage in excess of VCC, as long as the 15-V rating is not exceeded. Tx and Ty have
a larger current-sinking capability than a standard I2C device and can sink a static current of greater than 30 mA.
They also have dynamic pulldown capability of 100-mA, typically.
A logic low is transmitted to Tx or Ty only when the voltage at the I2C pin (Sx or Sy) is less than 0.6 V. A logic
low at Rx or Ry causes the I2C bus (Sx or Sy) to be pulled to a logic low level in accordance with I2C
requirements (maximum 1.5 V in 5-V applications), but not low enough to be looped back to the Tx or Ty output
and cause the buffer to latch low.
The minimum low level that the P82B96 can achieve on the I2C bus by a low at Rx or Ry typically is 0.8 V.
If VCC fails, neither the I2C pins nor the Tx or Ty outputs are held low. Their open-collector configuration allows
them to be pulled up to the rated maximum of 15 V without VCC present. The input configuration on Sx, Sy, Rx,
and Ry also presents no loading of external signals when VCC is not present. This ensures that communication
on the main I2C bus can continue if the P82B96 has no supply.
The effective input capacitance of any signal pin, measured by its effect on bus rise times, is less than 4 pF for
all bus voltages and supply voltages, including VCC = 0 V.
9.3.3 Long Cable Length
The P82B96 supports 400 pF on the main I2C bus (Sx/Sy side) and up to 4000 pF on the transmission side
(Tx/Ty). This allows for longer cables to be used due to the significant increase in capacitance allowed by the
device.
9.4 Device Functional Modes
The P82B96 begins functioning once VCC reaches 2 V. When VCC is low, the P82B96 does not hold the Sx/Sy
pins low, which ensures I2C communication can continue between other devices on the bus while the VCC is low.
14
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Calculating System Delays and Bus-Clock Frequency for Fast Mode System
Figure 7 through Figure 9 show the P82B96 used to drive extended bus wiring, with relatively large capacitance
(up to 4000 pF), linking two Fast mode I2C bus nodes. It includes simplified expressions for making the relevant
timing calculations for 3.3-/5-V operation. It may be necessary to decrease the nominal SCL frequency below
400 kHz, because the buffers and the wiring introduce timing delays. In most cases, the actual bus frequency is
lower than the nominal master timing, due to bit-wise stretching of the clock periods.
Buffered Expansion Bus
Local Master Bus
Remote Slave Bus
VCCB
VCCM
MASTER
VCCS
Rb
Rm
SCL
Sx
I2C
P82B96
Tx/Rx
Rs
SCL
SLAVE
Sx
Tx/Rx
P82B96
Cb = Buffered Bus
Wiring Capacitance
Cm = Master Bus
Capacitance
Cs = Slave Bus
Capacitance
I2C
GND
Falling edge of SCL at master is delayed by the buffers and bus fall times.
9
Effective Delay of SCL at Slave = 255 + 17 VCCM + (2.5 + 4 × 10 Cb) VCCB (ns)
C = F, V = Volts
Figure 7. Linking Two I2C Bus Nodes Over a Long Cable, Master to Slave
Buffered Expansion Bus
Local Master Bus
VCCB
VCCM
MASTER
SCL
Rb
Rm
Sx
P82B96
Tx/Rx
Tx/Rx
2
IC
Cm = Master Bus
Capacitance
Cb = Buffered Bus
Wiring Capacitance
GND
Rising edge of SCL at master is delayed (clock stretch) by buffer and bus rise times.
Effective delay of SCL at master = 270 + RmCm + 0.7RbCb (ns)
C = F, R = Ω
Figure 8. Master I2C Node Connection to P82B96
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Application Information (continued)
Buffered Expansion Bus
Local Master Bus
VCCM
Remote Slave Bus
VCCS
VCCB
MASTER
SDA
Rm
Rs
Rb
Sx
P82B96
Tx/Rx
Tx/Rx
P82B96
SDA
SLAVE
Sx
I2C
I2C
Cm = Master Bus
Capacitance
Cb = Buffered Bus
Wiring Capacitance
Cs = Slave Bus
Capacitance
GND
Rising edge of SDA at slave is delayed by the buffers and bus rise times.
Effective delay of SDA at master = 270 + 0.2RsCs + 0.7(RbCb + RmCm) (ns)
C = F, R = Ω
Figure 9. Linking Two I2C Bus Nodes Over a Long Cable, Slave to Master
The delay factors involved in calculation of the allowed bus speed are:
• The propagation delay of the master signal through the buffers and wiring to the slave. The important delay is
that of the falling edge of SCL, because this edge requests the data or ACK from a slave.
• The effective stretching of the nominal low period of SCL at the master, caused by the buffer and bus rise
times.
• The propagation delay of the slave response signal through the buffers and wiring back to the master. The
important delay is that of a rising edge in the SDA signal. Rising edges always are slower and, therefore, are
delayed by a longer time than falling edges. (The rising edges are limited by the passive pullup, while falling
edges actively are driven.)
The timing requirement in any I2C system is that a slave’s data response (which is provided in response to a
falling edge of SCL) must be received at the master before the end of the corresponding low period of SCL as it
appears on the bus wiring at the master. Because all slaves, as a minimum, satisfy the worst-case timing
requirements of a 400-kHz part, they must provide their response within the minimum allowed clock low period of
1300 ns. Therefore, in systems that introduce additional delays, it is necessary only to extend that minimum clock
low period by any effective delay of the slave response. The effective delay of the slave's response equals the
total delays in SCL falling edge from the master reaching the slave (A) minus the effective delay (stretch) of the
SCL rising edge (B) plus total delays in the slave response data, carried on SDA, and reaching the master (C).
The master microcontroller should be programmed to produce a nominal SCL low period
of (1300 + A – B + C) ns and should be programmed to produce the nominal minimum SCL high period of
600 ns. Then, a check should be made to ensure the cycle time is not shorter than the minimum 2500 ns. If
found to be necessary, increase either clock period.
Due to clock stretching, the SCL cycle time always is longer than (600 + 1300 + A + C) ns.
10.1.1.1 Sample Calculations
The master bus has an RmCm product of 100 ns and VCCM = 5 V.
The buffered bus has a capacitance of 1 nF and a pullup resistor of 160 Ω to 5 V, giving an RbCb product of
160 ns. The slave bus also has an RsCs product of 100 ns.
The master low period should be programmed to be ≥(1300 + 372.5 – 482 + 472) ns, which calculates to
≥1662.5 ns.
The master high period may be programmed to the minimum 600 ns. The nominal master clock period is
≥(1662.5 + 600) ns = 2262.5 ns, equivalent to a frequency of 442 kHz.
The
actual
bus-clock
period,
including
the
482-ns
clock
stretch
effect,
is
(nominal + stretch) = (2262.5 + 482) ns or ≥2745 ns, equivalent to an allowable frequency of 364 kHz.
16
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10.2 Typical Applications
10.2.1 Driving Ribbon or Flat Telephone Cables
+V Cable Drive
VCC1
R2
VCC2
R2
R2
VCC
SCL
Sx
2
IC
MASTER
SDA
Sy
R1
R1
R1
R1
Rx
Rx
Tx
Tx
Ty
Ty
Sx
SCL
2
IC
SLAVE(S)
Sy
Ry
Ry
R2
VCC
SDA
Cable
P82B96
C2
P82B96
Propagation
Delay = 5 ns/m
C2
C2
C2
GND
GND
BAT54A
BAT54A
Figure 10. Driving Ribbon or Flat Telephone Cables
10.2.1.1 Design Requirements
In this application, the P82B96 is used to drive a ribbon cable. The following are assumed to be true
• Sy/Sx side of I2C bus is at a known voltage from 3.3 V to 5 V
• Tx/Ty and Rx/Ry side of I2C bus is at a known voltage from 2 V to 15V
• SCL Clock Speed
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