PCA9536
SCPS125H – APRIL 2006 – REVISED MARCH 2022
PCA9536 Remote 4-Bit I2C and SMBus I/O Expander with Configuration Registers
1 Features
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3 Description
Available in the Texas Instruments NanoFree™
Package
Low standby current consumption of 1 μA Max
I2C to parallel port expander
Operating power-supply voltage range of 2.3 V to
5.5 V
5-V Tolerant I/O ports
400-kHz fast I2C bus
Input and output configuration register
Polarity inversion register
Internal power-on reset
No glitch on power up
Power-up with all channels configured as inputs
Noise filter on SCL/SDA inputs
Latched outputs with high-current drive maximum
capability for directly driving LEDs
Latch-up performance exceeds 100 mA per JESD
78, class II
ESD Protection exceeds JESD 22
– 2000-V Human-body model (A114-A)
– 200-V Machine model (A115-A)
– 1000-V Charged-device model (C101)
This 4-bit I/O expander for the two-line bidirectional
bus (I2C) is designed for 2.3-V to 5.5-V VCC operation.
It provides general-purpose remote I/O expansion for
most microcontroller families through the I2C interface
[serial clock (SCL), serial data (SDA)].
The PCA9536 features 4-bit Configuration (input or
output selection), Input Port, Output Port, and Polarity
Inversion (active high or active low) registers. At
power on, the I/Os are configured as inputs with a
weak pullup to VCC. However, the system controller
can enable the I/Os as either inputs or outputs by
writing to the I/O configuration bits. If no signals are
applied externally to the PCA9536, the voltage level
is 1, or high, because of the internal pullup resistors.
The data for each input or output is stored in the
corresponding Input Port or Output Port register. The
polarity of the Input Port register can be inverted
with the Polarity Inversion register and the system
controller reads all registers.
The system controller resets the PCA9536 in the
event of a timeout or other improper operation by
utilizing the power-on reset feature, which puts the
registers in their default state and initializes the I2C/
SMBus state machine.
2 Applications
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Personal electronics
– Wearables
– Mobile phones
– Gaming consoles
Servers
Routers
The device outputs (latched) have high-current drive
capability for directly driving LEDs, but has low current
consumption.
Device Information
PART NUMBER
PCA9536
(1)
P0
SCL
P1
GND
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
Peripheral Devices
SDA
PCA9536
BODY SIZE (NOM)
SOIC (8)
For all available packages, see the orderable addendum at
the end of the datasheet.
VCC
I2C or SMBus Controller
(e.g. Processor)
PACKAGE(1)
P2
P3
RESET, ENABLE, or
control inputs
INT or status outputs
LEDs
Buttons
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
PCA9536
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SCPS125H – APRIL 2006 – REVISED MARCH 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 I2C Interface Timing Requirements.............................6
6.7 Switching Characteristics............................................6
6.8 Typical Characteristics................................................ 7
7 Parameter Measurement Information.......................... 10
8 Detailed Description......................................................12
8.1 Overview................................................................... 12
8.2 Functional Block Diagram......................................... 12
8.3 Feature Description...................................................13
8.4 Device Functional Modes..........................................13
8.5 Programming............................................................ 13
8.6 Register Maps...........................................................15
9 Application Information Disclaimer............................. 19
9.1 Application Information............................................. 19
9.2 Typical Application.................................................... 19
10 Power Supply Recommendations..............................22
10.1 Power-On Reset Errata...........................................22
10.2 System Impact........................................................ 22
11 Layout........................................................................... 23
11.1 Layout Guidelines................................................... 23
11.2 Layout Example...................................................... 23
12 Device and Documentation Support..........................24
12.1 Documentation Support.......................................... 24
12.2 Receiving Notification of Documentation Updates..24
12.3 Support Resources................................................. 24
12.4 Trademarks............................................................. 24
12.5 Electrostatic Discharge Caution..............................24
12.6 Glossary..................................................................24
13 Mechanical, Packaging, and Orderable
Information.................................................................... 24
4 Revision History
Changes from Revision G (June 2014) to Revision H (March 2022)
Page
• Changed all instances of legacy terminology to controller and target where I2C is mentioned..........................1
• Deleted the DSBGA (YZP) package information................................................................................................ 1
• Added the Simplified Schematic to the front page..............................................................................................1
• Removed packaging information from the Absolute Maximum Ratings table.................................................... 4
• Added Tstg to the Absolute Maximum Ratings table........................................................................................... 4
• Added the Thermal Information table................................................................................................................. 4
• Deleted VPOR from the Electrical Characteristics ...............................................................................................5
• Added VPORR and VPORF to the Electrical Characteristics ................................................................................. 5
• Changed the ICC stand by mode current max values for 5.5 V from 1 to 1.8 μA; 3.6 V from 0.9 to 1.2 μA; and
2.7 V from 0.8 to 1 μA in the Electrical Characteristics ......................................................................................5
• Changed the tvd(data) and tvd(ack) MAX values from: 1 μs to: 3.45 μs in the Standard Mode timing....................6
• Changed the ticr, tocf, and tocf MIN values in the Fast Mode timing.....................................................................6
• Added the Overview section............................................................................................................................. 12
• Added the Device Functional Modes section....................................................................................................13
• Added Detailed Design Procedure section....................................................................................................... 20
• Added Application Curves section.................................................................................................................... 21
• Added the Layout section................................................................................................................................. 23
Changes from Revision F (September 2008) to Revision G (June 2014)
Page
• Added Power-On Reset Errata section.............................................................................................................22
2
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SCPS125H – APRIL 2006 – REVISED MARCH 2022
5 Pin Configuration and Functions
P0
1
8
VCC
P1
2
7
SDA
P2
3
6
SCL
GND
4
5
P3
P0
1
8
VCC
P1
2
7
SDA
P2
3
6
SCL
GND
4
5
P3
Not to scale
Figure 5-2. DGK Package, 8-Pin VSSOP,
Top View
Not to scale
Figure 5-1. D Package, 8-Pin SOIC
(Top View)
Table 5-1. Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
P0
I/O
P-port input-output. Push-pull design structure
2
P1
I/O
P-port input-output. Push-pull design structure
3
P2
I/O
P-port input-output. Push-pull design structure
4
GND
—
Ground
5
P3
I/O
P-port input-output. Push-pull design structure
6
SCL
I/O
Serial clock bus. Connect to VCC through a pullup resistor
7
SDA
I/O
Serial data bus. Connect to VCC through a pullup resistor
8
VCC
—
Supply voltage
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) See (1)
MIN
MAX
UNIT
VCC
Supply voltage
–0.5
6
V
VI
Input voltage (2)
–0.5
6
V
VO
Output voltage (2)
–0.5
6
V
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–20
mA
IIOK
Input/output clamp current
VO < 0 or VO > VCC
±20
mA
IOL
Continuous output low current
VO = 0 to VCC
50
mA
IOH
Continuous output high current
VO = 0 to VCC
–50
mA
ICC
Tstg
(1)
(2)
Continuous current through GND
–200
Continuous current through VCC
160
Storage temperature
–65
mA
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
V(ESD)
(1)
(2)
Electrostatic discharge
MIN
MAX
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
0
2000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins(2)
0
1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
MAX
2.3
5.5
0.7 × VCC
5.5
2
5.5
SCL, SDA
–0.5
0.3 × VCC
P3–P0
–0.5
0.8
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
P3–P0
IOL
Low-level output current
P3–P0
TA
Operating free-air temperature
SCL, SDA
P3–P0
–40
UNIT
V
V
V
–10
mA
25
mA
85
°C
6.4 Thermal Information
THERMAL METRIC(1)
DGK (VSSOP)
8 PINS
8 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
141.9
183.7
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
82.6
76.9
°C/W
RθJB
Junction-to-board thermal resistance
85.3
104.9
°C/W
ψJT
Junction-to-top characterization parameter
32.3
18.7
°C/W
ψJB
Junction-to-board characterization parameter
84.6
103.4
°C/W
(1)
4
D (SOIC)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
Input diode clamp voltage
II = –18 mA
VPORR
Power-on reset voltage, VCC rising
VI = VCC or GND, IO = 0
VPORF
Power-on reset voltage, VCC falling
VI = VCC or GND, IO = 0
IOH = –8 mA
VOH
P-port high-level
output voltage(2)
IOH = –10 mA
SDA
VOL = 0.4 V
VOL = 0.5 V
IOL
P-port(3)
VOL = 0.7 V
VCC
MIN
2.3 V to 5.5 V
–1.2
TYP(1)
1.2
0.75
2.3 V
1.8
3V
2.6
4.5 V
4.1
4.75 V
4.1
2.3 V
1.7
3V
2.5
MAX
UNIT
0
V
1.6
V
1
V
V
4.5 V
4
4.75 V
4
2.3 V to 5.5 V
3
10
2.3 V
8
10
3V
8
14
4.5 V
8
17
4.75 V
8
32
2.3 V
10
13
3V
10
19
4.5 V
10
24
4.75 V
10
44
mA
II
SCL, SDA
VI = VCC or GND
2.3 V to 5.5 V
±1
μA
IIH
P-port
VI = VCC
2.3 V to 5.5 V
1
μA
IIL
P-port
VI = GND
2.3 V to 5.5 V
–100
μA
VI = VCC, IO = 0,
I/O = inputs, fscl = 400 kHz
Operating mode
VI = VCC, IO = 0,
I/O = inputs, fscl = 100 kHz
ICC
VI = GND, IO = 0,
I/O = inputs, fscl = 0 kHz
Standby mode
VI = VCC, IO = 0,
I/O = inputs, fscl = 0 kHz
ΔICC
Ci
Cio
(1)
(2)
(3)
Additional current in
standby mode
SCL
SDA
P-port
5.5 V
73
150
3.6 V
9
50
2.7 V
7
30
5.5 V
14
25
3.6 V
9
20
2.7 V
6
15
5.5 V
225
350
3.6 V
175
250
2.7 V
125
200
5.5 V
0.25
1.8
3.6 V
0.2
1.2
2.7 V
0.1
1
One input at VCC – 0.6 V,
Other inputs at VCC or GND
2.3 V to 5.5 V
0.35
Every LED I/O at VI = 4.3 V,
fscl = 0 kHz
5.5 V
0.4
VI = VCC or GND
VIO = VCC or GND
μA
mA
2.3 V to 5.5 V
2.3 V to 5.5 V
4
5
5
6.5
7.5
9.5
pF
pF
All typical values are at nominal supply voltage (2.5-, 3.3-, or 5-V VCC) and TA = 25°C.
The total current sourced by all I/Os must be limited to 85 mA.
Each I/O must be limited externally to a maximum of 25 mA, and the P-port (P3–P0) must be limited to a maximum current of 100 mA.
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6.6 I2C Interface Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
MIN
MAX
UNIT
100
kHz
Standard Mode
fscl
I2C clock frequency
0
tsch
I2C clock high time
4
tscl
I2C
tsp
I2C spike time
tsds
I2C serial-data setup time
tsdh
I2C serial-data hold time
ticr
I2C input rise time
ticf
I2C
tocf
I2C output fall time, 10-pF to 400-pF bus
tbuf
I2C bus free time between Stop and Start
4.7
μs
tsts
I2C Start or repeated Start condition setup time
4.7
μs
tsth
I2C Start or repeated Start condition hold time
4
μs
tsps
I2C
4
tvd(data)
Valid data time, SCL low to SDA output valid
3.45
tvd(ack)
Valid data time of ACK condition, ACK signal from SCL low to SDA (out) low
3.45
μs
Cb
I2C bus capacitive load
400
pF
400
kHz
clock low time
μs
4.7
μs
50
250
ns
0
ns
input fall time
1000
ns
300
ns
300
Stop condition setup time
ns
ns
μs
μs
Fast Mode
fscl
I2C clock frequency
tsch
I2C
tscl
I2C clock low time
tsp
I2C spike time
tsds
I2C serial-data setup time
tsdh
I2C serial-data hold time
ticr
I2C
ticf
I2C
tocf
I2C output fall time, 10-pF to 400-pF bus
tbuf
I2C bus free time between Stop and Start
1.3
μs
tsts
I2C
0.6
μs
tsth
I2C Start or repeated Start condition hold time
0.6
μs
tsps
I2C Stop condition setup time
0.6
tvd(data)
Valid data time, SCL low to SDA output valid
0.9
tvd(ack)
Valid data time of ACK condition, ACK signal from SCL low to SDA (out) low
0.9
μs
Cb
I2C bus capacitive load
400
pF
MAX
UNIT
200
ns
(1)
0
clock high time
0.6
μs
1.3
μs
50
ns
0
ns
20(1)
input rise time
20x(Vdd/5.5V)
input fall time
(1)
20x(Vdd/5.5V)
(1)
Start or repeated Start condition setup time
ns
100
300
ns
300
ns
300
ns
μs
μs
Cb = Total capacitive load of one bus in pF
6.7 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
STANDARD MODE and FAST MODE
6
tpv
Output data valid
SCL
P3–P0
tps
Input data setup time
P-port
SCL
100
ns
tph
Input data hold time
P-port
SCL
1
μs
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6.8 Typical Characteristics
TA = 25°C (unless otherwise noted)
300
55
VCC = 5 V
50
VCC = 5 V
250
ICC – Supply Current – nA
ICC – Supply Current – µA
45
40
f SCL = 400 kHz
I/Os unloaded
35
30
25
VCC = 3.3 V
20
15
VCC = 2.5 V
10
200
VCC = 3.3 V
150
VCC = 2.5 V
100
50
5
SCL = VCC
0
-50
-25
0
25
50
75
0
-50
100
Figure 6-1. Supply Current vs Temperature
0
25
50
75
100
Figure 6-2. Quiescent Supply Current vs Temperature
300
70
f SCL = 400 kHz
I/Os unloaded
60
VCC = 5 V
275
250
ICC – Supply Current – µA
ICC – Supply Current – µA
-25
TA – Free-Air Temperature – °C
TA – Free-Air Temperature – °C
50
40
30
20
225
200
TA = –40°C
175
150
TA = 25°C
125
100
TA = 85°C
75
50
10
25
0
0
0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
1
5.5
2
3
4
Number of I/Os Held Low
VCC – Supply Voltage – V
Figure 6-3. Supply Current vs Supply Voltage
Figure 6-4. Supply Current vs Number of I/Os Held Low
300
300
VCC = 2.5 V, ISINK = 10 mA
275
(V CC – V OH ) – Output High Voltage – mV
275
VOL – Output Low Voltage – mV
250
225
200
175
150
VCC = 5 V, ISINK = 10 mA
125
100
75
VCC = 2.5 V, ISINK = 1 mA
50
VCC = 5 V, ISINK = 1 mA
25
0
-50
-25
0
25
50
75
250
VCC = 2.5 V, IOL = 10 mA
225
200
175
150
125
VCC = 5 V, IOL = 10 mA
100
75
50
25
0
-50
100
TA – Free-Air Temperature – °C
-25
0
25
50
75
100
TA – Free-Air Temperature – °C
Figure 6-5. I/O Output Low Voltage vs Temperature
Figure 6-6. I/O Output High Voltage vs Temperature
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6.8 Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
30
40
VCC = 3.3 V
VCC = 2.5 V
35
TA = –40°C
ISINK – I/O Sink Current – mA
ISINK – I/O Sink Current – mA
25
20
TA = 25°C
15
TA = 85°C
10
5
TA = –40°C
30
TA = 25°C
25
20
15
TA = 85°C
10
5
0
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.0
0.1
VOL – Output Low Voltage – V
Figure 6-7. I/O Sink Current vs Output Low Voltage
0.3
0.4
0.5
0.6
0.7
Figure 6-8. I/O Sink Current vs Output Low Voltage
30
60
VCC = 5 V
VCC = 2.5 V
ISOURCE – I/O Source Current – mA
55
50
ISINK – I/O Sink Current – mA
0.2
VOL – Output Low Voltage – V
45
TA = –40°C
40
35
TA = 25°C
30
25
20
TA = 85°C
15
10
25
TA = –40°C
20
TA = 25°C
15
TA = 85°C
10
5
5
0
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.0
0.7
Figure 6-9. I/O Sink Current vs Output Low Voltage
0.3
0.4
0.5
0.6
0.7
70
VCC = 3.3 V
VCC = 5 V
65
40
TA = –40°C
ISOURCE – I/O Source Current – mA
ISOURCE – I/O Source Current – mA
0.2
Figure 6-10. I/O Source Current vs Output High Voltage
45
35
30
TA = 25°C
25
20
15
10
TA = 85°C
5
60
55
50
TA = –40°C
45
40
35
TA = 25°C
30
25
TA = 85°C
20
15
10
5
0
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.0
0.7
0.1
0.2
0.3
0.4
0.5
0.6
0.7
(VCC – VOH) – Output High Voltage – V
(VCC – VOH) – Output High Voltage – V
Figure 6-11. I/O Source Current vs Output High Voltage
8
0.1
(VCC – VOH) – Output High Voltage – V
VOL – Output Low Voltage – V
Figure 6-12. I/O Source Current vs Output High Voltage
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6.8 Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
6
TA = 25°C
VOH – Output High Voltage – V
5
4
IOH = –8 mA
3
IOH = –10 mA
2
1
0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VCC – Supply Voltage – V
Figure 6-13. Output High Voltage vs Supply Voltage
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7 Parameter Measurement Information
VCC
RL = 1 NŸ
DUT
SDA
CL = 50 pF
(see Note A)
SDA LOAD CONFIGURATION
Three Bytes for Complete
Device Programming
Stop
Condition
(P)
Start
Condition
(S)
Address
Bit 7
(MSB)
Address
Bit 6
tscl
Address
Bit 1
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 7
(MSB)
Data
Bit 0
(LSB)
Stop
Condition
(P)
tsch
0.7 x VCC
SCL
0.3 x VCC
ticr
tbuf
tsts
tPHL
ticf
tPLH
tsp
0.7 x VCC
SDA
0.3 x VCC
tsdh
ticf
tsds
tsps
Repeat
Start
Condition
Start or
Repeat
Start
Condition
Stop
Condition
VOLTAGE WAVEFORMS
A.
B.
C.
CL include probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
All parameters and waveforms are not applicable to all devices.
Figure 7-1. I2C Interface Load Circuit and Voltage Waveforms
10
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500
Pn
DUT
2 x VCC
CL = 50 pF
(see Note A)
500
P-PORT LOAD CONFIGURATION
0.7 x VCC
SCL
P0
A
P3
0.3 x VCC
Target
ACK
SDA
tpv
(see Note B)
Unstable Data
Last Stable Bit
WRITE MODE (R/W = 0)
0.7 x VCC
P0
SCL
A
P3
0.3 x VCC
tph
tps
0.7 x VCC
Pn
0.3 x VCC
READ MODE (R/W = 1)
A.
B.
C.
D.
E.
CL include probe and jig capacitance.
tpv is measured from 0.7 × VCC on SCL to 50% I/O (Pn) output.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf ≤ 30 ns.
The outputs are measured one at a time, with one transition per measurement.
All parameters and waveforms are not applicable to all devices.
Figure 7-2. P-Port Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The PCA9536 device is a 4-bit I/O expander for the I2C bus and is designed for 1.65-V to 5.5-V VCC operation. It
provides general-purpose remote I/O expansion for most microcontroller families through the I2C interface.
The PCA9536 consists of a configuration (input or output selection), Input Port, Output Port, and Polarity
Inversion (active-high or active-low operation) registers. At power-on, the I/Os are configured as inputs. The
system controller enables the I/Os as either inputs or outputs by writing to the I/O configuration register bits. The
data for each input or output is kept in the corresponding input or output register. The polarity of the Input Port
register can be inverted with the Polarity Inversion register and the system controller reads all registers.
The device outputs (latched) have high-current drive capability for directly driving LEDs.
8.2 Functional Block Diagram
SCL
SDA
6
7
Input
Filter
I2C Bus
Control
Shift
Register
4 Bits
I/O
Port
P3-P0
Write Pulse
Read Pulse
VCC
GND
8
Power-On
Reset
4
Figure 8-1. Logic Diagram
12
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Data From
Shift Register
Output Port
Register Data
VCC
Configuration
Register
Data From
Shift Register
Q1
D Q
FF
Write Configuration
Pulse
CK Q
Write Pulse
100 NŸ
D Q
FF
P0 to P3
CK Q
Output Port
Register
Q2
Input Port
Register
D Q
FF
CK Q
Read Pulse
Data From Shift
Register
D Q
FF
CK Q
Write Polarity
Pulse
ESD Protection
Diode
GND
Input Port
Register Data
Polarity
Register Data
Polarity Inversion
Register
Figure 8-2. Simplified Schematic Of P0 To P3
8.3 Feature Description
8.3.1 I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 (in Figure 8-2) are off, creating a high-impedance input
with a weak pullup (100 kΩ typical) to VCC. The input voltage may be raised above VCC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register.
In this case, there are low-impedance paths between the I/O pin and either VCC or GND. The external voltage
applied to this I/O pin should not exceed the recommended levels for proper operation.
8.4 Device Functional Modes
8.4.1 Power-On Reset
When power (from 0 V) is applied to VCC, an internal power-on reset holds the PCA9536 in a reset condition until
VCC has reached VPOR. At that time, the reset condition is released and the PCA9536 registers and I2C/SMBus
state machine initialize to their default states. After that, VCC must be lowered to below 0.2 V and then back up to
the operating voltage for a power-reset cycle.
Refer to the Section 10.1 section.
8.4.2 Powered-Up
When power has been applied to VCC above VPORR, and the POR has taken place, the device is in a functioning
mode. In this state, the device is ready to accept any incoming I2C requests and monitors for changes on the
input ports.
8.5 Programming
8.5.1 I2C Interface
The bidirectional I2C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I2C communication with this device is initiated by a controller sending a Start condition, which is a high-to-low
transition on the SDA input and output while the SCL input is high (see Figure 8-3). After the Start condition, the
device address byte is sent, most-significant bit (MSB) first, including the data direction bit (R/ W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA input
and output during the high of the ACK-related clock pulse.
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On the I2C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (Start or Stop) (see Figure 8-4).
A Stop condition, a low-to-high transition on the SDA input and output while the SCL input is high, is sent by the
controller (see Figure 8-3).
Any number of data bytes can be transferred from the transmitter to receiver between the Start and the Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse, so that the SDA line is stable low during the high pulse of the ACK-related clock period (see Figure
8-5). When a target receiver is addressed, it must generate an ACK after each byte is received. Similarly, the
controller must generate an ACK after each byte that it receives from the target transmitter. Setup and hold times
must be met to ensure proper operation.
A controller receiver signals an end of data to the target transmitter by not generating an acknowledge (NACK)
after the last byte has been clocked out of the target. This is done by the controller receiver, by holding the SDA
line high. In this event, the transmitter must release the data line to enable the controller to generate a Stop
condition.
SDA
SCL
S
P
Start Condition
Stop Condition
Figure 8-3. Definition of Start and Stop Conditions
SDA
SCL
Data Line
Stable;
Data Valid
Change
Of Data
Allowed
Figure 8-4. Bit Transfer
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Data Output
By Transmitter
NACK
Data Output
By Receiver
ACK
SCL From
Controller
1
2
8
9
S
Clock Pulse for
Acknowledgment
Start
Condition
Figure 8-5. Acknowledgment on the I2C Bus
8.6 Register Maps
Table 8-1 shows the PCA9536 interface definition.
Table 8-1. Interface Definition
BYTE
I2C
BIT
7 (MSB)
6
5
4
3
2
1
0 (LSB)
H
L
L
L
L
L
H
R/ W
P3
P2
P1
P0
target address
Px I/O data bus
Does not affect operation of the PCA9536
P7
P6
P5
P4
8.6.1 Device Address
Figure 8-6 shows the address byte of the PCA9536.
Target Address
1
0
0
0
0
0
1
1
Fixed
Figure 8-6. PCA9536 Address
The target address equates to 65 (decimal) and 41 (hexadecimal).
The last bit of the target address defines the operation (read or write) to be performed. When it is high (1), a read
is selected, while a low (0) selects a write operation.
8.6.2 Control Register and Command Byte
Following the successful acknowledgment of the address byte, the bus controller sends a command byte that is
stored in the control register in the PCA9536. Two bits of this data byte state the operation (read or write) and
the internal register (Input, Output, Polarity Inversion, or Configuration) that will be affected. This register can be
written or read through the I2C bus. The command byte is sent only during a write transmission.
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Once a command byte has been sent, the addressed register is continuosly accessed by reads until a new
command byte is sent.
Figure 8-7 shows the PCA9536 control register bits and Table 8-2 shows the command byte.
0
0
0
0
0
0
B1
B0
Figure 8-7. Control Register Bits
Table 8-2. Command Byte
CONTROL REGISTER BITS
B1
B0
COMMAND BYTE
(HEX)
REGISTER
PROTOCOL
POWER-UP
DEFAULT
0
0
0×00
Input Port
Read byte
1111 XXXX
0
1
0×01
Output Port
Read/write byte
1111 1111
1
0
0×02
Polarity Inversion
Read/write byte
0000 0000
1
1
0×03
Configuration
Read/write byte
1111 1111
8.6.3 Register Descriptions
The Input Port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin
is defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these
registers have no effect. The default value, X, is determined by the externally applied logic level. See Table 8-3.
Before a read operation, a write transmission is sent with the command byte to instruct the I2C device that the
Input Port register will be accessed next.
Table 8-3. Register 0 (Input Port Register)
BIT
DEFAULT
I7
I6
I5
I4
Not Used
1
1
1
1
I3
I2
I1
I0
X
X
X
X
The Output Port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the
Configuration register. The bit values in this register have no effect on pins defined as inputs. In turn, reads from
this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. See
Table 8-4.
Table 8-4. Register 1 (Output Port Register)
BIT
DEFAULT
O7
O6
O5
O4
Not Used
1
1
1
1
O3
O2
O1
O0
1
1
1
1
The Polarity Inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration
register. If a bit in this register is set (written with 1), the corresponding port pin's polarity is inverted. If a bit in this
register is cleared (written with a 0), the corresponding port pin's original polarity is retained. See Table 8-5.
Table 8-5. Register 2 (Polarity Inversion Register)
BIT
DEFAULT
N7
N6
N5
N4
Not Used
0
0
0
0
N3
N2
N1
N0
0
0
0
0
The Configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to
1, the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is
cleared to 0, the corresponding port pin is enabled as an output. See Table 8-6.
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Table 8-6. Register 3 (Configuration Register)
C7
BIT
C6
C5
C4
Not Used
DEFAULT
1
1
1
C3
C2
C1
C0
1
1
1
1
1
8.6.4 Bus Transactions
Data is exchanged between the controller and PCA9536 through write and read commands.
8.6.4.1 Writes
Data is transmitted to the PCA9536 by sending the device address and setting the least-significant bit (LSB) to a
logic 0 (see Figure 8-6 for device address). The command byte is sent after the address and determines which
register receives the data that follows the command byte. There is no limitation on the number of data bytes sent
in one write transmission (see Figure 8-8 and Figure 8-9).
1
SCL
3
2
4
6
7
9
8
Target Address
SDA S
1
0
0
0
0
Command Byte
0
1
Start Condition
0
A
0
0
0
0
0
0
Data to Register
1
1
R/W ACK From Target
Data 1
A
A
P
ACK From Target
ACK From Target
Write to
Port
Data Out
From Port
Data 1 Valid
tpv
Figure 8-8. Write to Output Port Register
1
SCL
2
3
4
6
7
8
9
Target Address
SDA
S
1
0
0
0
0
Command Byte
0
Start Condition
1
0
A
()
0
0
0
R/W ACK From Target
0
0
Data to Register
1
1
A
Data
A
P
ACK From Target
ACK From Target
Data to
Register
Figure 8-9. Write to Configuration or Polarity Inversion Registers
8.6.4.2 Reads
The bus controller first must send the PCA9536 address with the LSB set to a logic 0 (see Figure 8-6 for
device address). The command byte is sent after the address and determines which register is accessed. After a
restart, the device address is sent again but, this time, the LSB is set to a logic 1. Data from the register defined
by the command byte then is sent by the PCA9536 (see Figure 8-10 and Figure 8-11). After a restart, the value
of the register defined by the command byte matches the register being accessed when the restart occurred.
Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number
of data bytes received in one read transmission, but when the final byte is received, the bus controller must not
acknowledge the data.
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Target
Target
Target
Target
Controller
Target
At this time, the controller-transmitter
becomes controller-receiver and
target-receiver becomes target-transmitter
Controller
Figure 8-10. Read From Register
1
SCL
2
3
4
5
6
7
8
9
Data From Port
Target Address
SDA
S
1
0
0
Start
Condition
0
0
0
1
1
R/W
Data 1
A
Data From Port
Data 4
A
ACK From
Controller
ACK From
Target
NA P
NACK From
Controller
Stop
Condition
Read From
Port
Data Into
Port
Data 2
t ph
Data 3
Data 4
Data 5
t ps
INT
t iv
A.
B.
C.
t ir
This figure assumes that the command byte previously has been programmed with 00h.
Transfer of data can be stopped at any moment by a Stop condition.
This figure eliminates the command byte transfer, a restart, and the target address call between the initial target address call and actual
data transfer from the P-port (see Figure 8-10).
Figure 8-11. Read Input Port Register
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9 Application Information Disclaimer
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
9.2 Typical Application
Figure 9-1 shows an application in which the PCA9536 can be used.
VCC
10 kΩ
VCC
10 kΩ
2 kΩ
Subsystem 1
(e.g., temperature
sensor)
VCC
SCL
SCL
I2C
SDA
Controller
SDA
P0
INT
P1
P2
RESET
PCA9536 P3
GND
Subsystem 2
(e.g., counter)
A
GND
ENABLE
B
A.
B.
C.
Device address is 10000001.
P0, P2, and P3 are configured as outputs.
P1 is configured as an input.
Figure 9-1. Typical Application
9.2.1 Design Requirements
9.2.1.1 Minimizing ICC When I/Os Control LEDs
When the I/Os are used to control LEDs, they are normally connected to VCC through a resistor as shown
in Figure 9-1. The LED acts as a diode so, when the LED is off, the I/O VIN is about 1.2 V less than VCC.
The supply current, ICC, increases as VIN becomes lower than VCC and is specified as ΔICC in Electrical
Characteristics.
Designs needing to minimize current consumption, such as battery power applications, should consider
maintaining the I/O pins greater than or equal to VCC when the LED is off. Figure 9-2 shows a high-value
resistor in parallel with the LED. Figure 9-3 shows VCC less than the LED supply voltage by at least 1.2 V. Both
of these methods maintain the I/O VIN at or above VCC and prevent additional supply-current consumption when
the LED is off.
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VCC
LED
100 NŸ
VCC
Pn
Figure 9-2. High-Value Resistor in Parallel with the LED
3.3 V
5V
LED
VCC
Pn
Figure 9-3. Device Supplied by a Lower Voltage
9.2.2 Detailed Design Procedure
The pull-up resistors, RP, for the SCL and SDA lines need to be selected appropriately and take into
consideration the total capacitance of all targets on the I2C bus. The minimum pull-up resistance is a function of
VCC, VOL,(max), and IOL as shown in Equation 1:
Rp(min) =
VCC - VOL(max)
IOL
(1)
The maximum pull-up resistance is a function of the maximum rise time, tr (300 ns for fast-mode operation, fSCL
= 400 kHz) and bus capacitance, Cb as shown in Equation 2:
Rp(max) =
tr
0.8473 ´ Cb
(2)
The maximum bus capacitance for an I2C bus must not exceed 400 pF for standard-mode or fast-mode
operation. The bus capacitance can be approximated by adding the capacitance of the PCA9536, Ci for SCL
or Cio for SDA, the capacitance of wires,connections or traces, and the capacitance of additional targets on the
bus.
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9.2.3 Application Curves
1.8
Standard-Mode
Fast-Mode
Minimum Pull-Up Resistance (k:)
Maximum Pull-Up Resistance (k:)
25
20
15
10
5
VDPUX > 2 V
VDUPX 2 V
Standard-mode: fSCL = 100 kHz, tr = 1 µs
Fast-mode: fSCL = 400 kHz, tr = 300 ns
Figure 9-4. Maximum Pull-Up Resistance (Rp(max))
vs Bus Capacitance (Cb)
Figure 9-5. Minimum Pull-Up Resistance (Rp(min))
vs Pull-up Reference Voltage (VCC)
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10 Power Supply Recommendations
10.1 Power-On Reset Errata
A power-on reset condition can be missed if the VCC ramps are outside specification listed in Figure 10-1.
Figure 10-1. Power-On Reset Cycle
10.2 System Impact
If ramp conditions are outside timing allowances above, POR condition can be missed, causing the device to
lock up.
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11 Layout
11.1 Layout Guidelines
For printed circuit board (PCB) layout of the PCA9536, common PCB layout practices must be followed but
additional concerns related to high-speed data transfer such as matched impedances and differential pairs are
not a concern for I2C signal speeds.
In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from
each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher
amounts of current that commonly pass through power and ground traces. By-pass and de-coupling capacitors
are commonly used to control the voltage on the VCC pin, using a larger capacitor to provide additional power
in the event of a short power supply glitch and a smaller capacitor to filter out high-frequency ripple. These
capacitors must be placed as close to the PCA9536 as possible.
For the layout example provided, it would be possible to fabricate a PCB with only 2 layers by using the top layer
for signal routing and the bottom layer as a split plane for power (VCC) and ground (GND). However, a 4-layer
board is preferable for boards with higher density signal routing. On a 4-layer PCB, it is common to route signals
on the top and bottom layer, dedicate one internal layer to a ground plane, and dedicate the other internal layer
to a power plane. In a board layout using planes or split planes for power and ground, vias are placed directly
next to the surface mount component pad which needs to attach to VCC or GND and the via is connected
electrically to the internal layer or the other side of the board. Vias are also used when a signal trace needs to be
routed to the opposite side of the board, but this technique is not demonstrated.
11.2 Layout Example
GND
CAP
P0
VCC
P1
SDA
PCA9536
P2
SCL
GND
P3
Figure 11-1. Layout Example (DGK)
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
•
•
•
•
•
I2C Bus Pull-Up Resistor Calculation
Maximum Clock Frequency of I2C Bus Using Repeaters
Introduction to Logic
Understanding the I2C Bus
Choosing the Correct I2C Device for New Designs
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
NanoFree™ and TI E2E™ are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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3-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
PCA9536D
NRND
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD536
PCA9536DG4
NRND
SOIC
D
8
75
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD536
PCA9536DGKR
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green NIPDAU | NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
(7CF, 7CL)
Samples
PCA9536DGKRG4
ACTIVE
VSSOP
DGK
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
(7CF, 7CL)
Samples
PCA9536DR
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD536
Samples
PCA9536DRG4
ACTIVE
SOIC
D
8
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
PD536
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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