PCM1723
PCM
172
3E
49%
FPO
SBAS057A – JANUARY 1996 – REVISED MAY 2007
Stereo Audio
DIGITAL-TO-ANALOG CONVERTER
With Programmable PLL
TM
FEATURES
DESCRIPTION
● ACCEPTS 16-, 20-, OR 24-BIT INPUT DATA
The PCM1723 is a complete, low-cost, stereo audio
digital-to-analog converter (DAC) with a phase-locked
loop (PLL) circuit included. The PLL derives either a
256fS or 384fS system clock from an external 27MHz
reference frequency. The DAC contains a 3rd-order
delta-sigma (∆Σ) modulator, a digital interpolation filter,
and an analog output amplifier. The PCM1723 can
accept 16-, 20-, or 24-bit input data in either normal or
I2S formats.
● COMPLETE STEREO DAC: Includes Digital Filter
and Output Amp
● DYNAMIC RANGE: 94dB
● MULTIPLE SAMPLING FREQUENCIES:
16kHz, 22.05kHz, 24kHz
32kHz, 44.1kHz, 48kHz
64kHz, 88.2kHz, 96kHz
● PROGRAMMABLE PLL CIRCUIT:
256fS/384fS from 27MHz Master Clock
The digital filter performs an 8X interpolation function
and includes selectable features such as soft mute,
digital attenuation and digital de-emphasis. The PLL
can be programmed for sampling at standard digital
audio frequencies as well as one-half and double
sampling frequencies.
● NORMAL OR I2S™ DATA INPUT FORMATS
● SELECTABLE FUNCTIONS:
Soft Mute
Digital Attenuator (256 Steps)
Digital De-emphasis
The PCM1723 is ideal for applications which combine
compressed audio and video data such as DVD, DVDROM, set-top boxes and MPEG sound cards.
● OUTPUT MODE: Left, Right, Mono, Mute
Multi-level
Delta-Sigma
Modulator
BCKIN
LRCIN
DIN
Serial
Input
I/F
8X Oversampling
Digital Filter
with Function
Controller
Low-Pass
Filter
DAC
VOUTL
CAP
Multi-level
Delta-Sigma
Modulator
ML
Low-Pass
Filter
DAC
VOUTR
MC
MD
Mode
Control
I/F
ZERO
BPZ-Cont.
256fS/384fS
Open Drain
RSTB
PLL
SCKO
OSC
MCKO
XTI XTO
Power Supply
VCP PGND VCC AGND VDD DGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SoundPLUS is a trademark of Texas Instruments.
I2S is a trademark of NXP Semiconductors.
All other trademarks are the property of their respective owners.
Copyright © 1996-2007, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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ELECTROSTATIC
DISCHARGE SENSITIVITY
PIN CONFIGURATION
TOP VIEW
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause
damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
SSOP
XTI
1
24
XTO
SCKO
2
23
PGND
VCP
3
22
DGND
NC
4
21
VDD
MCKO
5
20
RES
ML
6
19
NC
MC
7
18
LRCIN
MD
8
17
DIN
RSTB
9
16
BCKIN
ZERO 10
15
CAP
VOUTR 11
14
VOUTL
AGND 12
13
VCC
ABSOLUTE MAXIMUM RATINGS(1)
Power Supply Voltage ...................................................................... +6.5V
+VCC to +VDD Difference ................................................................... ±0.1V
Input Logic Voltage .................................................. –0.3V to (VDD + 0.3V)
Input Current (except power supply) ............................................... ±10mA
Power Dissipation .......................................................................... 530mW
Operating Temperature Range ......................................... –25°C to +85°C
Storage Temperature ...................................................... –55°C to +125°C
Lead Temperature (soldering, 5s) .................................................. +260°C
Thermal Resistance, θJA ....................................................................................... +70°C/W
NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
PACKAGE
INFORMATION(1)
PRODUCT
PACKAGE
PACKAGE
DESIGNATOR
PCM1723E
24-Pin SSOP
DB
NOTE: (1) For the most current package and ordering information, see the
Package Option Addendum at the end of this data sheet, or see the TI web
site at www.ti.com
PIN ASSIGNMENTS
PIN
NAME
TYPE
1
XTI
IN
FUNCTION
2
SCKO
OUT
System Clock Out. This output is 256fS or 384fS.
system clock generated by the internal PLL.
3
VCP
PWR
PLL Power Supply (+5V).
4
NC
N/A
No connection.
5
MCKO
Out
Buffered clock output of crystal oscillator.
Master Clock Input.
6(1)
ML
IN
Latch for serial control data.
7(1)
MC
IN
Clock for serial control data.
8(1)
MD
IN
Data for serial control.
9(1)
RSTB
IN
Reset Input. When this pin is low, the digital
filters and modulators are held in reset.
10
ZERO
OUT
Zero Data Flag. This pin is low when the input
data is continuously zero for more than 65, 535
cycles of BCKIN.
11
VOUTR
OUT
Right Channel Analog Output.
12
AGND
GND
Analog Ground.
Analog Power Supply (+5V).
13
VCC
PWR
14
VOUTL
OUT
15
CAP
Left Channel Analog Output.
Common pin for analog output amplifiers.
16(2)
BCKIN
IN
17(2)
DIN
IN
Serial audio data input.
18(2)
LRCIN
IN
Left/Right Word Clock. Frequency is equal to fS.
Bit clock for clocking in the audio data.
19
NC
N/A
No connection.
20
RES
N/A
Reserved for factory use, do not connect.
21
VDD
PWR
Analog Power Supply (+5V).
22
DGND
GND
Digital Ground.
23
PGND
GND
24
XTO
Out
PLL Ground.
Crystal oscillator output.
NOTES: (1) Schmitt trigger input with internal pull-up resistors.
(2) Schmitt triger input.
2
PCM1723
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SBAS057A
ELECTRICAL CHARACTERISTICS
All specifications at +25°C, +VCC = +VDD = +VCP = +5V, fS = 44.1kHz, and 16-bit input data, SYSCLK = 384fS, unless otherwise noted.
PCM1723
PARAMETER
RESOLUTION
DATA FORMAT
Audio Data Interface Format
Data Bit Length
Audio Data Format
Sampling Frequency (fS)
PLL PERFORMANCE
Master Clock Input Frequency(4)
Master Clock Output Frequency
Generated SYSCLK Frequency
Output Logic Level
VOH
(MCKO, SCKO)
VOL
Generated SYSCLK Jitter
Generated SYSCLK Transient(1)
Power-Up Time
Generated SYSCLK Duty Cycle
CONDITIONS
MIN
TYP
Standard fS
One-half fS
Double fS
MSB
32
16
64
THD+N at –60dB
Dynamic Range (EIAJ Method)
Signal-to-Noise Ratio(3) (EIAJ Method)
Channel Separation
DC ACCURACY
Gain Error
Gain Mismatch, Channel-to-Channel
Bipolar Zero Error
ANALOG OUTPUT
Output Voltage
Center Voltage
Load Impedance
Standard/I2S Selectable
16/20/24 Selectable
First, Binary Two’s Complement
44.1
48
22.05
24
88.2
96
26.73
4.096
POWER SUPPLY REQUIREMENTS
Voltage Range
Supply Current: ICC + IDD + ICP
27.27
36.864
MHz
MHz
VDD – 0.4
0.5
±150
40
15
50
20
30
60
VDC
VDC
ps
ms
ms
%
TTL
fs = 44.1kHz
fs = 96kHz
fs = 44.1kHz
fs = 96kHz
fs = 44.1kHz
fs = 96kHz
fs = 44.1kHz
fs = 96kHz
fs = 44.1kHz
90
90
88
VOUT = VCC/2 at BPZ
Full Scale (–0dB)
AC Load
–89
–87
–31
–29
94
91
96
95
93
–80
dB
dB
dB
dB
dB
dB
dB
dB
dB
±1.0
±1.0
±30
±3.0
±2.0
% of FSR
% of FSR
mV
VPP
VDC
kΩ
0.62 x VCC
VCC/2
5
0.445
0.555
±0.17
–35
11.125/fS
–0.2
VCC = VDD = VCP
fS = 44.1kHz
+0.55
100
–0.16
f = 20kHz
TEMPERATURE RANGE
Operating
Storage
NOTES: (1)
(2)
(3)
(4)
27
kHz
kHz
kHz
256fS/384fS
IOH = 2mA
IOL = 4mA
Standard Dev
fM = 27MHz
To Programmed Frequency
fM = 27MHz, CL = 15pF
DIGITAL FILTER PERFORMANCE
Passband
Stop Band
Passband Ripple
Stop Band Attenuation
Delay Time
De-emphasis Error
INTERNAL ANALOG FILTER
–3dB Bandwidth
Passband Response
UNITS
Bits
DIGITAL INPUT LOGIC LEVEL
DYNAMIC PERFORMANCE(2)
THD+N at fS (0dB)
MAX
16
4.5
–25
–55
5
20
fS
fS
dB
dB
sec
dB
kHz
dB
5.5
24
VDC
mA
+85
+100
°C
°C
Sysclk transient is the maximum frequency lock time when the PLL frequency is changed.
Dynamic performance specs are tested with 20kHz low pass filter and THD+N specs are tested with 30kHz LPF, 400Hz HPF, Average-Mode.
SNR is tested at Infinite Zero Detection off.
PLL evaluations tested with 1ns maximum jitter on the 27MHz input clock.
PCM1723
SBAS057A
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3
TYPICAL CHARACTERISTICS
At TA = +25°C, VCC = VDD = VCP = +5V, fS = 44.1kHz, 16-bit input data, 384fS, unless otherwise noted. Measurement bandwidth is 20kHz.
DYNAMIC PERFORMANCE
THD+N (0dB) vs TEMPERATURE and
VCC = 5V, 384fS
THD+N (0dB) vs POWER SUPPLY VOLTAGE
TA = 25°C, 384fS
–70
–70
–75
fS = 96k
THD+N (dB)
THD+N (dB)
–75
–80
–85
fS = 44.1k
–90
fS = 96k
–80
–85
fS = 44.1k
–90
–95
–95
–25
0
25
50
75
85
4.5
5.0
5.5
Temperature (°C)
Power Supply Voltage (V)
THD+N (0dB) vs SAMPLING RATE (fS)
VCC = 5V, TA = 25°C
POWER SUPPLY CURRENT vs SAMPLING RATE (fS)
VCC = 5V, TA = 25°C
30
–70
–80
Supply Current (mA)
THD+N (dB)
–75
256fS
–85
384fS
–90
–95
44.1k
48k
88.2k
256fS
20
10
44.1k
96k
Sampling Rate, fS (Hz)
4
384fS
48k
88.2k
96k
Sampling Rate, fS (Hz)
PCM1723
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SBAS057A
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, RL = 44.1kHz, and fSYS = 384fS, unless otherwise noted.
DIGITAL FILTER
PASSBAND RIPPLE CHARACTERISTIC
OVERALL FREQUENCY CHARACTERISTIC
0
–20
–0.2
–40
–0.4
dB
dB
0
–60
–0.6
–80
–0.8
–1
–100
0 0.4536fS
1.3605fS
2.2675fS
3.1745fS
4.0815fS
0
0.1134fS
5k
10k
15k
20k
25k
0
3628
15k
20k
25k
0
4999.8375
15k
20k
19999.35
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
0
25k
Frequency (Hz)
5442
10884
16326
21768
Frequency (Hz)
PCM1723
SBAS057A
14999.5125
DE-EMPHASIS ERROR (48kHz)
Error (dB)
Level (dB)
DE-EMPHASIS FREQUENCY RESPONSE (48kHz)
10k
9999.675
Frequency (Hz)
0
–2
–4
–6
–8
–10
–12
5k
14512
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
Frequency (Hz)
0
10884
DE-EMPHASIS ERROR (44.1kHz)
Error (dB)
Level (dB)
DE-EMPHASIS FREQUENCY RESPONSE (44.1kHz)
10k
7256
Frequency (Hz)
0
–2
–4
–6
–8
–10
–12
5k
0.4535fS
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
Frequency (Hz)
0
0.3402fS
DE-EMPHASIS ERROR (32kHz)
Error (dB)
Level (dB)
DE-EMPHASIS FREQUENCY RESPONSE (32kHz)
0
–2
–4
–6
–8
–10
–12
0
0.2268fS
Frequency (Hz)
Frequency (Hz)
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5
TYPICAL CONNECTION DIAGRAM
Figure 1 illustrates the typical connection diagram for the
PCM1723 in an MPEG-2 application. The 27MHz master
video clock (fM) drives XTI (pin 1) of the PCM1723. A
programmable system clock is generated by the PCM1723
PLL, with SCKO used to drive the MPEG-2 decoder system
clock input. The standard audio signals (data, bit clock, and
word clock) are generated in the decoder from the PCM1723
system clock, providing synchronization of audio and video
signals.
PLL CIRCUIT
The PCM1723 has a programmable internal PLL circuit, as
shown in Figure 2. The PLL is designed to accept a 27MHz
master clock or crystal oscillator and generate all internal
system clocks required to operate the digital filter and ∆Σ
modulator, either at 256fS or 384fS. If an external master clock
is used, XTO must be connected to GND. In both cases, the
signal amplitude on XTI must satisfy the specification described in Figure 3. Therefore, careful C1 and C2 determination is required to keep this specification satisfied when
+5V Analog
23
22
PGND DGND
17
SERO
Audio
Decoder
16
SCKO
18
LRCKO
2
SYSCKI
Master
PLL
VDD
3
VCP
VOUTL
DIN
BCKIN
CAP
SCKO
VOUTR
PCM1723
ZERO
1
27MHz CLK OUT
24
14
15
+
LRCIN
Buffer
256/384fS
SCR(1)
or
PCR
21
XTI
Lch Analog Out
Post
LPF
Analog
Mute
Rch Analog Out
10
MC
MD
RSTB
AGND
Analog
Mute
10µF
11
ML
XTO
Post
LPF
6
STRB
7
SCKO
8
SDO
9
System
Controller
PIO
VCC
12
13
+5V Analog
NOTE: (1) SCR: System Clock Reference
PCR: Program Clock Reference
FIGURE 1. Connection Diagram for External Master Clock in a Typical MPEG-2 Application.
Sampling Frequency Selection
256fS/384fS Selection
N Counter
Frequency
Selection ROM
Oscillator
Phase Detector
and Loop Filter
VCO
M Counter
24
1
5
2
XTO
XTI
MCKO
PLL Generated
System Clock Out
FIGURE 2. PLL Block Diagram.
1/27MHz
tCH: 10ns (min)
tCL: 15ns (min)
tCH
XTI
IIH (VIH = VDD) : 4mA max
IIL (VIL = 0) : 700µA max
1.2V
0.4V
tCL
FIGURE 3. XTI Input Timing.
6
PCM1723
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SBAS057A
MCKO
27MHz
Out
MCKO
Buffer
27MHz Internal Master Clock
C1
X’tal
XTI
27MHz Internal Master Clock
XTI
External Clock
R
R
C2
XTO
C1, C2 = 10 to 33pF
XTO
PCM1723
PCM1723
CRYSTAL RESONATOR CONNECTION
EXTERNAL CLOCK INPUT
FIGURE 4. System Clock Connection.
1/fS
L_ch
R_ch
LRCIN (pin 4)
BCKIN (pin 6)
AUDIO DATA WORD = 16-BIT
DIN (pin 5)
14 15 16
1
2
MSB
AUDIO DATA WORD = 20-BIT
DIN (pin 5)
18 19 20
1
2
23 24
1
18
3
2
15 16
1
2
LSB
MSB
AUDIO DATA WORD = 24-BIT
DIN (pin 5)
14
3
MSB
19 20
1
2
LSB
22
3
MSB
14
3
LSB
18
3
MSB
23 24
1
LSB
2
15 16
19 20
LSB
22
3
MSB
23 24
LSB
FIGURE 5. Normal Data Input Timing.
1/fS
L_ch
LRCIN (pin 4)
R_ch
BCKIN (pin 6)
AUDIO DATA WORD = 16-BIT
DIN (pin 5)
1
2
MSB
AUDIO DATA WORD = 20-BIT
DIN (pin 5)
1
2
3
MSB
AUDIO DATA WORD = 24-BIT
DIN (pin 5)
3
1
2
3
MSB
14
15 16
1
2
3
MSB
LSB
18
19 20
1
2
LSB
22
3
MSB
23 24
LSB
1
2
3
MSB
14
1
2
19 20
1
2
23 24
1
2
15 16
LSB
18
LSB
22
LSB
FIGURE 6. I2S Data Input Timing.
PCM1723
SBAS057A
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7
LRCKIN
1.4V
tBCH
tBCL
tLB
BCKIN
1.4V
tBL
tBCY
1.4V
DIN
tDS
tDH
BCKIN Pulse Cycle Time
: tBCY
: 100ns (min)
BCKIN Pulse Width High
: tBCH
: 50ns (min)
BCKIN Pulse Width Low
: tBCL
: 50ns (min)
BCKIN Rising Edge to LRCIN Edge : tBL
: 30ns (min)
LRCIN Edge to BCKIN Rising Edge : tLB
: 30ns (min)
DIN Set-up Time
: tDS
: 30ns (min)
DIN Hold Time
: tDH
: 30ns (min)
FIGURE 7. Audio Data Input Timing.
using a crystal oscillator. The PLL will directly track any
variations in the master clock frequency, and jitter on the
system clock is specified at 250ps maximum. Figure 3 illustrates the timing requirements for the 27MHz master clock.
Figure 4 illustrates the system clock connections for an
external clock or crystal oscillator.
The PCM1723 internal PLL can be programmed for nine
different sampling frequencies (LRCIN), as shown in Table
I. The internal sampling clocks generated by the various
programmed frequencies are shown in Table II. The system
clock output frequency for the PCM1723 is 100% accurate.
To provide MCKO clock and SCKO clock for external
circuit, external buffer circuit is effective to avoid degrading
audio performance.
Sampling Frequencies-LRCIN (kHz)
SPECIAL FUNCTIONS
The PCM1723 includes several special functions, including
digital attenuation, digital de-emphasis, soft mute, data format selection and input word resolution. These functions are
controlled using a three-wire interface. MD (pin 8) is used
for the program data, MC (pin 7) is used to clock in the
program data, and ML (pin 6) is used to latch in the program
data. Table III lists the selectable special functions.
FUNCTION
Input Audio Data Format Selection
Normal Format
I2S Format
Input Audio Data Bit Selection
16/20/24 Bits
Input LRCIN Polarity Selection
Lch/Rch = High/Low
Lch/Rch = Low/High
Normal Format
16 Bits
Lch/Rch = High/Low
Half of Standard Sampling Freq
16
22.05
24
De-emphasis Control
OFF
Standard Sampling Freq
32
44.1
48
Soft Mute Control
OFF
Double of Standard Sampling Freq
64
88.2
96
Attenuation Control
Lch, Rch Individually
Lch, Rch Common
TABLE I. Sampling Frequencies.
Infinite Zero Detection Circuit Control
Sampling
Frequency
(LRCIN)
System Clock
256fS
System Clock
384fS
16kHz
Half
4.096MHz
6.144MHz
32kHz
Standard
8.192MHz
12.288MHz
64kHz
Double
16.384MHz
24.576MHz
22.05kHz
Half
5.6448MHz
8.4672MHz
44.1kHz
Standard
11.2896MHz
16.9344MHz
88.2kHz
Double
22.5792MHz
33.8688MHz
24kHz
Half
6.144MHz
9.216MHz
48kHz
Standard
12.288MHz
18.432MHz
96kHz
Double
24.576MHz
36.864MHz
TABLE II. Sampling Frequencies vs Internal System
Clock (= Output Frequencies of PLL).
8
DEFAULT MODE
Operation Enable (OPE)
Sample Rate Selection
Internal System Clock Selection
256fS
384fS
Double Sampling Rate Selection
Standard Sampling Rate—44.1/48/32kHz
Double Sampling Rate—88.2/96/32kHz
Half Sampling Rate—22.05/24/16kHz
Sampling Frequency
44.1kHz Group
48kHz Group
32kHz Group
Analog Output Mode
L, R, Mono, Mute
0dB
Lch, Rch Individually Fixed
OFF
Enabled
384fS
Standard Sampling Rate
44.1kHz
Stereo
TABLE III. Selectable Functions.
PCM1723
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SBAS057A
MAPPING OF PROGRAM REGISTERS
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
MODE0
res
res
res
res
res
A1
A0
LDL
AL7
AL6
AL5
AL4
AL3
AL2
AL1
AL0
MODE1
res
res
res
res
res
A1
A0
LDR
AR7
AR6
AR5
AR4
AR3
AR2
AR1
AR0
MODE2
res
res
res
res
res
A1
A0
PL3
PL2
PL1
PL0
IW1
IW0
OPE
DEM
MUT
MODE3
res
res
res
res
res
A1
A0
IZD
SF1
SF0
DSR1
DSR0
SYS
ATC
LRP
I2S
PROGRAM REGISTER BIT MAPPING
The PCM1723 special functions are controlled using four
program registers that are 16 bits long. These registers are all
loaded using MD. After the 16 data bits are clocked in, ML
is used to latch in the data to the appropriate register. Table
IV shows the complete mapping of the four registers and
Figure 8 illustrates the serial interface timing.
REGISTER
NAME
BIT
NAME
Register 0
AL (7:0)
LDL
A (1:0)
Res
DAC Attenuation Data for Lch
Attenuation Data Load Control for Lch
Register Address
Reserved
Register 1
AR (7:0)
LDL
A (1:0)
Res
DAC Attenuation Data for Rch
Attenuation Data Load Control for Rch
Register Address
Reserved
MUT
DEM
OPE
IW (1:0)
PL (3:0)
A (1:0)
res
Left and Right DACs Soft Mute Control
De-emphasis Control
Left and Right DACs Operation Control
Input Audio Data Bit Select
Output Mode Select
Register Address
Reserved
Register 2
Register 3
I2S
LRP
ATC
SYS
DSR (1:0)
SF (1:0)
IZD
A (1:0)
Res
level until LDL is set to 1. LDR in Register 1 has the same
function for right channel attenuation.
Attenuation Level (ATT) can be controlled as following
Resistor set AL (R) (7:0).
AL (R) (7:0)
ATT LEVEL
00h
01h
.
.
.
FEh
FFh
–∞dB (Mute)
–48.16dB
.
.
.
–0.07dB
0dB
DESCRIPTION
REGISTER 1 (A1 = 0, A0 = 1)
B15 B14 B13 B12 B11 B10 B9 B8
res res res res res
Register 1 is used to control right channel attenuation. As
in Register 1, bits 0 - 7 (AR0 - AR7) control the level of
attenuation.
Audio Data Format Select
Polarity of LRCIN (pin 7) Select
Attenuator Control
System Clock Select
Double Sampling Rate Select
Sampling Rate Select
Infinite Zero Detection Circuit Control
Register Address
Reserved
REGISTER 2 (A1 = 1, A0 = 0)
B15 B14 B13 B12 B11 B10 B9 B8
res res res res res A1
TABLE IV. Internal Register Mapping.
REGISTER 0 (A1 = 0, A0 = 0)
B15 B14 B13 B12 B11 B10 B9 B8
B7 B6 B5 B4 B3 B2 B1 B0
res res res res res A1 A0 LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0
Register 0 is used to control left channel attenuation. Bits
0 - 7 (AL0 - AL7) are used to determine the attenuation
level. The level of attenuation is given by:
B6 B5
B4
B3
B2
B1
B0
Bit 2 (OPE) is used for operational control. Table V illustrates the features controlled by OPE.
OPE = 1
ATTENUATION DATA LOAD CONTROL
Bit 8 (LDL) is used to control the loading of attenuation data
in B0:B7. When LDL is set to 0, attenuation data will be
loaded into AL0:AL7, but it will not affect the attenuation
B7
A0 PL3 PL2 PL1 PL0 IW1 IW0 OPE DEM MUTE
Register 2 is used to control soft mute, de-emphasis, operation enable, input resolution, and output format. Bit 0 is used
for soft mute: a HIGH level on bit 0 will cause the output to
be muted (this is ramped down in the digital domain, so no
click is audible). Bit 1 is used to control de-emphasis. A
LOW level on bit 1 disables de-emphasis, while a HIGH
level enables de-emphasis.
ATT = [20 log10 (ATT_DATA/255)] dB
OPE = 0
DATA INPUT
DAC OUTPUT
SOFTWARE MODE
INPUT
Zero
Forced to BPZ(1)
Enabled
Other
Forced to BPZ(1)
Enabled
Zero
Controlled by IZD
Enabled
Other
Normal
Enabled
NOTE: (1) ∆∑ is disconnected from output amplifier.
TABLE V. Operation Enable (OPE) Function.
PCM1723
SBAS057A
B7 B6 B5 B4 B3 B2 B1 B0
A1 A0 LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0
www.ti.com
9
OPE controls the operation of the DAC: when OPE is LOW,
the DAC will convert all non-zero input data. If the input
data is continuously zero for 65,536 cycles of BCKIN, the
output will be forced to zero only if IZD is HIGH. When
OPE is HIGH, the output of the DAC will be forced to
bipolar zero, irrespective of any input data.
DATA INPUT
DAC OUTPUT
Zero
Forced to BPZ(1)
Other
Normal
IZD = 1
IZD = 0
Zero
Zero(2)
Other
Normal
TABLE VI. Infinite Zero Detection (IZD) Function.
DATA INPUT
DAC OUTPUT
SOFTWARE
MODE
INPUT
Enabled
RSTB = LOW
Zero
Controlled by OPE and IZD
Other
Controlled by OPE and IZD
Enabled
Zero
Forced to BPZ(1)
Disabled
Other
Forced to BPZ(1)
Disabled
TABLE VII. Reset (RSTB) Function.
Bits 3 (IW0) and 4 (IW1) are used to determine input word
resolution. PCM1723 can be set up for input word resolutions of 16, 20, or 24 bits:
Bit 3 (IW0)
Input Resolution
0
0
1
1
0
1
0
1
16-bit Data Word
20-bit Data Word
24-bit Data Word
Reserved
Bits 5, 6, 7, and 8 (PL0:3) are used to control output format.
The output of PCM1723 can be programmed for 16 different
states, as shown in Table VIII.
PL0
PL1
PL2
PL3
Lch OUTPUT
Rch OUTPUT
NOTE
0
0
0
0
MUTE
MUTE
MUTE
0
0
0
1
MUTE
R
0
0
1
0
MUTE
L
0
0
1
1
MUTE
(L + R)/2
0
1
0
0
R
MUTE
R
0
1
0
1
R
0
1
1
0
R
L
0
1
1
1
R
(L + R)/2
1
0
0
0
L
MUTE
1
0
0
1
L
R
1
0
1
0
L
L
1
0
1
1
L
(L + R)/2
1
1
0
0
(L + R)/2
MUTE
1
1
0
1
(L + R)/2
R
1
1
1
0
(L + R)/2
L
1
1
1
1
(L + R)/2
(L + R)/2
TABLE VIII. Programmable Output Format.
10
B8 B7 B6
res
IZD SF1 SF0 DSR1 DSR0 SYS ATC LRP I2S
res res res res A1
A0
B5
B4
B3 B2 B1 B0
Register 3 is used to control input data format and polarity,
attenuation channel control, system clock frequency, sampling frequency, and infinite zero detection.
Bit 2 (ATC) is used for controlling the attenuator. When
bit 2 is HIGH, the attenuation data loaded in program
Register 0 are used for both left and right channels. When
bit 2 is LOW, the attenuation data for each register are
applied separately to left and right channels.
Bit 3 (SYS) is the system clock selection. When bit 3 is
LOW, the system clock frequency is set to 384fS. When bit
3 is HIGH, the system clock frequency is set to 256fS.
NOTE: (1) ∆∑ is disconnected from output amplifier.
Bit 4 (IW1)
B15 B14 B13 B12 B11 B10 B9
Bits 0 (I2S) and 1 (LRP) are used to control the input data
format. A LOW on bit 0 sets the format to Normal (MSBfirst, right-justified Japanese format), and a HIGH sets the
format to I2S (Philips serial data protocol). Bit 1 (LRP) is
used to select the polarity of LRCIN (sample rate clock).
When bit 1 is LOW, left channel data are assumed when
LRCIN is in a HIGH phase and right channel data are
assumed when LRCIN is in a LOW phase. When bit 1 is
HIGH, the polarity assumption is reversed.
NOTES: (1) ∆∑ is disconnected from output amplifier.
(2) ∆∑ is connected to output amplifier.
RSTB = HIGH
REGISTER 3 (A1 = 1, A0 = 1)
Bits 4 (DSR0) and 5 (DSR1) are used to control multiples
of the sampling rate:
DSR1
DSR0
0
0
1
1
0
1
0
1
Multiple
Normal
Double
One-half
Reserved
32/44.1/48kHz
64/88.2/96kHz
16/22.05/24kHz
Not Defined
Bits 6 (SF0) and 7 (SF1) are used to select the sampling
frequency. Frequency selection must be made with an
interval time greater than 20µs.
SF1
SF0
0
0
1
1
0
1
0
1
Sampling Frequency
44.1kHz group
48kHz group
32kHz group
Reserved
22.05/44.1/88.2kHz
24/48/96kHz
16/32/64kHz
Not Defined
Bit 8 is used to control the infinite zero detection function
(IZD).
REVERSE
STEREO
MONO
When IZD is LOW, the zero detect circuit is off. Under
this condition, no automatic muting will occur if the input
is continuously zero. When IZD is HIGH, the zero detect
feature is enabled. If the input data are continuously zero
for 65,536 cycles of BCKIN, the output will be immediately forced to a bipolar zero state (VCC/2). The zero
detection feature is used to avoid noise which may occur
when the input is DC. When the output is forced to bipolar
zero, there may be an audible click. PCM1723 allows the
zero detect feature to be disabled so the user can implement an external muting circuit.
PCM1723
www.ti.com
SBAS057A
ML (pin 6)
MC (pin 7)
MD (pin 8)
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
FIGURE 8. Three-Wire Serial Interface.
tMHH
tMLH
tMLS
1.4V
ML
tMCH
tMCL
tMLL
1.4V
MC
tMCY
LSB
MD
tMDS
1.4V
tMDH
MC Pulse Cycle Time
MC Pulse Width LOW
MC Pulse Width HIGH
MD Setup Time
MD Hold Time
ML Low Level Time
ML High Level Time
ML Setup Time
ML Hold Time
tMCY
tMCL
tMCH
tMDS
tMDH
tMLL
tMLH
tMLS
tMHH
100ns (min)
50ns (min)
50ns (min)
30ns (min)
30ns (min)
30ns + 1SYSCLK (min)
30ns + 1SYSCLK (min)
30ns (min)
30ns (min)
SYSCLK: 1/256fS or 1/384fS
FIGURE 9. Program Register Input Timing.
APPLICATION
CONSIDERATIONS
DELAY TIME
There is a finite delay time in delta-sigma converters. In
analog-to-digital converters (ADCs), this is commonly referred to as latency. For a delta-sigma DAC, delay time is
determined by the order number of the FIR filter stage, and
the chosen sampling rate. The following equation expresses
the delay time of PCM1723:
tD = 11.125 x 1/fS
For fS = 44.1kHz, tD = 11.125/44.1kHz = 251.4µs
Applications using data from a disc or tape source, such as
CD audio, CD-Interactive, Video CD, DAT, Minidisc, etc.,
generally are not affected by delay time. For some profes-
sional applications such as broadcast audio for studios, it is
important for total delay time to be less than 2ms.
OUTPUT FILTERING
For testing purposes all dynamic tests are done on the
PCM1723 using a 20kHz low-pass filter. This filter limits
the measured bandwidth for THD+N, etc. to 20kHz. Failure
to use such a filter will result in higher THD+N and lower
SNR and Dynamic Range readings than are found in the
specifications. The low-pass filter removes out of band
noise. Although it is not audible, it may affect dynamic
specification numbers.
PCM1723
SBAS057A
www.ti.com
11
The performance of the internal low-pass filter from DC to
24kHz is shown in Figure 10. The higher frequency rolloff
of the filter is shown in Figure 11. If an application has the
PCM1723 driving a wideband amplifier, it is recommended
to use an external low-pass filter. A simple 3rd-order filter
is shown in Figure 12. For some applications, a passive RC
filter or 2nd-order filter may be adequate.
RSTB = LOW. For internal power on reset, initialize (reset)
is done automatically at power on VDD >2.2V (typ). During
internal reset = LOW, the output of the DAC is invalid and
the analog outputs are forced to VCC/2. Figure 13 illustrates
the timing of internal power on reset.
The PCM1723 accepts an external forced reset when
RSTB = L. During RSTB = L, the output of the DAC is
invalid and the analog outputs are forced to VCC/2 after
internal initialize (1024 system clocks count after RSTB = H).
Figure 14 illustrates the timing of RSTB pin reset.
Reset
The PCM1723 has both internal power-on reset circuit and
the RSTB pin (pin 9) that accepts an external forced reset by
INTERNAL ANALOG FILTER FREQUENCY RESPONSE
(10Hz~10MHz)
INTERNAL ANALOG FILTER FREQUENCY RESPONSE
(20Hz~24kHz, Expanded Scale)
1.0
dB
dB
0.5
0
–0.5
–1.0
20
100
1k
Frequency (Hz)
10k
10
5
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
10
24k
100
1k
10k
100k
1M
10M
Frequency (Hz)
FIGURE 11. Low-Pass Filter Wideband Frequency Response.
FIGURE 10. Low-Pass Filter Frequency Response.
GAIN vs FREQUENCY
6
90
+
VSIN
10kΩ
10kΩ
OPA604
10kΩ
680pF
–14
0
–34
–90
–54
–180
Phase (°)
1500pF
Gain (dB)
Gain
Phase
100pF
–
–74
–270
–94
–360
100
1k
10k
Frequency (Hz)
100k
1M
FIGURE 12. 3rd-Order Low-Pass Filter.
12
PCM1723
www.ti.com
SBAS057A
2.6V
VCC/VDD 2.2V
1.8V
Reset
Reset Removal
Internal Reset
1024 system (= XTI) clocks
XTI Clock
FIGURE 13. Internal Power-On Reset Timing.
RSTB
50% of VDD
tRST(1)
Reset
Reset Removal
Internal Reset
1024 system (XTI) clocks
XTI Clock
NOTE: (1) tRST = 20ns min
FIGURE 14. RSTB-Pin Reset Timing.
POWER SUPPLY
CONNECTIONS
The PCM1723 has three power supply connections: digital
(VDD), analog (VCC), and PLL (VCP). Each connection also
has a separate ground return pin. It is acceptable to use a
common +5V power supply for all three power pins. If
separate supplies are used without a common connection,
the delta between the supplies during ramp-up time must be
less than 0.6V. An application circuit to avoid a power-on
latch-up condition is shown in Figure 15.
Digital
Power Supply
Analog
Power Supply
VDD
DGND
BYPASSING POWER SUPPLIES
The power supplies should be bypassed as close as
possible to the unit. Refer to Figure 18 for optimal values of
bypass capacitors. It is also recommended to include a
0.1µF ceramic capacitor in parallel with the 10µF tantalum
capacitor.
AGND
FIGURE 15. Latch-up Prevention Circuit.
PCM1723
SBAS057A
VCP VCC
www.ti.com
13
The delta-sigma section of the PCM1723 is based on a 5level amplitude quantizer and a 3rd-order noise shaper. This
section converts the oversampled input data to 5-level deltasigma format.
A block diagram of the 5-level delta-sigma modulator is
shown in Figure 16. This 5-level delta-sigma modulator has
the advantage of stability and clock jitter sensitivity over the
typical one-bit (2 level) delta-sigma modulator.
The combined oversampling rate of the delta-sigma modulator and the internal 8X interpolation filter is 48fS for a
384fS system clock, and 64fS for a 256fS system clock. The
theoretical quantization noise performance of the 5-level
delta-sigma modulator is shown in Figure 17.
AC-3 APPLICATION CIRCUIT
A typical application for the PCM1723 is AC-3 5.1 channel
audio decoding and playback. This circuit uses the PCM1723
to develop the audio system clock from the 27MHz video
clock, with the SCKO pin used to drive the AC-3 decoder
and two PCM1720 units, the non-PLL version of the
PCM1723.
3rd ORDER ∆Σ MODULATOR
20
0
–20
Gain (–dB)
THEORY OF OPERATION
–40
–60
–80
–100
–120
–140
–160
0
5
10
15
20
25
Frequency (kHz)
FIGURE 17. Quantization Noise Spectrum.
+
In
+
8fS
18-Bit
+
+
Z–1
+
–
+
Z–1
Z–1
–
+
+
5-level Quantizer
+
4
3
Out
48fS (384fS)
64fS (256fS)
2
1
0
FIGURE 16. 5-Level ∆Σ Modulator Block Diagram.
14
PCM1723
www.ti.com
SBAS057A
10µF
+
BCKO
AC-3
Audio
Decoder
+5V Analog
20
LRCKO
14
16
DO_0
DO_1
15
DO_2
2
SYSCKI
19
DGND
VDD
VOUTL
BCKIN
DIN
CAP
6
7
13
Analog
Mute
Right-Channel
Front Speaker
200Ω
+
10µF
Post
Low-Pass
Filter
9
ML
MC
ZERO
8
Mute
Control
MD
RSTB
AGND
STRB
µP
Left-Channel
Front Speaker
SCKI
VOUTR
5
Analog
Mute
LRCIN
PCM1720
4
Post
Low-Pass
Filter
12
VCC
10
11
3.3µF
+
SCKO
+5V Analog
SDO
10µF
+
Three-wire I/F
(Serial I/O)
+5V Analog
20
3
DGND
14
16
15
2
19
VDD
VOUTL
BCKIN
Post
Low-Pass
Filter
12
DIN
CAP
13
6
7
+
Post
Low-Pass
Filter
9
MC
ZERO
8
Mute
Control
MD
RSTB
AGND
VCC
11
+5V Analog
10µF
+
23
Master Clock
Generator
or
PLL
18
17
2
22
+5V Analog
21
3
PGND DGND VDD
VDP
VOUTL
BCKIN
14
Post
Low-Pass
Filter
Analog
Mute
Center Channel
Post
Low-Pass
Filter
Analog
Mute
Sub-Woofer
LRCIN
DIN
CAP
15
+
10µF
SCKO
PCM1723
Buffer
1
6
7
8
Reset
Left-Channel
Surround Speaker
10µF
ML
10
3.3µF
+
16
Analog
Mute
200Ω
SCKI
VOUTR
5
Left-Channel
Surround Speaker
LRCIN
PCM1720
4
Analog
Mute
9
VOUTR
XTI
11
ML
MC
ZERO
10
Mute
Control
MD
24
RSTB
AGND
VCC
12
13
+
3.3µF
+5V Analog
FIGURE 18. Connection Diagram for a 6-Channel AC-3 Application.
PCM1723
SBAS057A
www.ti.com
15
Revision History
DATE
REVISION
PAGE
SECTION
—
Entire Document
2
Electrical Characteristics
DESCRIPTION
Updated format and added missing overbars to RSTB and ZERO pins.
Added "Selectable" to Audio Data Interface Format typical value column.
Deleted "Selectable" from Audio Data Format unit column.
5/07
A
PLL Circuit
6
Changed "XTO should be connected" to "XTO must be connected."
Added sentence regarding XTI signal amplitude and C1, C2 determination.
Figure 3
Changed 2.0V/0.8V to 1.2V/0.4V.
8
PLL Circuit
Deleted paragraph regarding frequency error.
10
Register 3
Added sentence to Bit 6 regarding interval time must be greater than 20µs.
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
16
PCM1723
www.ti.com
SBAS057A
PACKAGE OPTION ADDENDUM
www.ti.com
17-May-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
PCM1723E
ACTIVE
SSOP
DB
24
58
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-25 to 85
PCM1723E
Samples
PCM1723E/2K
ACTIVE
SSOP
DB
24
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-25 to 85
PCM1723E
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of