®
PCM1737
PCM
173
7
For most current data sheet and other product
information, visit www.burr-brown.com
24-Bit, 192kHz Sampling
Enhanced Multi-Level, Delta-Sigma, Audio
DIGITAL-TO-ANALOG CONVERTER
TM
FEATURES
APPLICATIONS
● 24-BIT RESOLUTION
● A/V RECEIVERS
● ANALOG PERFORMANCE (VCC = +5V):
Dynamic Range: 106dB typ
SNR: 106dB typ
THD+N: 0.0015% typ
Full-Scale Output: 3.1Vp-p typ
● DVD MOVIE AND AUDIO PLAYERS
● DVD ADD-ON CARDS FOR HIGH-END PCs
● HDTV RECEIVERS
● CAR AUDIO SYSTEMS
● OTHER APPLICATIONS REQUIRING 24-BIT
AUDIO
● 4x/8x OVERSAMPLING DIGITAL FILTER:
Passband: 0.454fS
Stopband: 0.546fS
Stopband Attenuation: –82dB
Passband Ripple: ±0.002dB
DESCRIPTION
● SAMPLING FREQUENCY: 10kHz to 192kHz
● SYSTEM CLOCK: 128, 192, 256, 384, 512, or
768fS with Auto Detect
● ACCEPTS 16-, 18-, 20-, AND 24-BIT AUDIO DATA
● DATA FORMATS: Standard, I2S, and Left-Justified
● USER-PROGRAMMABLE MODE CONTROLS:
Digital Attenuation: 0dB to –63dB, 0.5dB/Step
Digital De-Emphasis
Digital Filter Roll-Off: Sharp or Slow
Soft Mute
Variable Oversampling for ∆Σ DACs
Zero Detect Mute
Zero Flags for Each Output
The PCM1737 is a CMOS, monolithic, integrated
circuit which includes stereo digital-to-analog converters and support circuitry in a small SSOP-28
package. The data converters utilize Burr-Brown’s
enhanced multi-level delta-sigma architecture, which
employs 4th-order noise shaping and 8-level amplitude quantization to achieve excellent dynamic performance and improved tolerance to clock jitter.
The PCM1737 accepts industry standard audio data
formats with 16- to 24-bit data, providing easy
interfacing to audio DSP and decoder chips. Sampling rates up to 192kHz are supported. A full set
of user-programmable functions are accessible through
a 4-wire serial control port which supports register
write and read back functions.
● DUAL SUPPLY OPERATION:
+5V Analog, +3.3V Digital
● 5V TOLERANT DIGITAL INPUTS
● SMALL SSOP-28 PACKAGE
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1999 Burr-Brown Corporation
SBAS129
PDS-1552C
Printed in U.S.A. March, 2000
SPECIFICATIONS
All specifications at +25°C, +VCC = +5V, +VDD = +3.3V, system clock = 384fS (fS = 44.1kHz) and 24-bit data, unless otherwise noted.
PCM1737E
PARAMETER
CONDITIONS
MIN
RESOLUTION
DATA FORMAT
Audio Data Interface Formats
Audio Data Bit Length
Audio Data Format
System Clock Frequency
Sampling Frequency (fS)
DIGITAL INPUT/OUTPUT
Logic Family
Input Logic Level
VIH
VIL
Input Logic Current
IIH
IIL
IIH(1)
IIL(1)
Output Logic Current, Pin 25 (MDO)
IIZH
IIZL
Output Logic Level
VOH(2)
VOL(2)
VOH(3)
VOL(3)
DYNAMIC PERFORMANCE(4)
THD+N, VOUT = 0dB
VOUT = –60dB
Dynamic Range
Signal-to-Noise Ratio(5)
Channel Separation
DC ACCURACY
Gain Error
Gain Mismatch, Channel-to-Channel
Bipolar Zero Error
ANALOG OUTPUT
Output Voltage
Center Voltage
Load Impedance
DIGITAL FILTER PERFORMANCE
Filter Characteristic, Sharp Roll-Off
Passband
Stopband
Passband Ripple
Stopband Attenuation
Filter Characteristics, Slow Roll-Off 1
Passband
Stopband
Passband Ripple
Stopband Attenuation
User Selectable
User Selectable
TYP
MAX
UNITS
24
Bits
Standard, I2S, Left-Justified
16-, 18-, 20-, 24-Bit
MSB-First, Binary Two’s Complement
128, 192, 256, 384, 512, 768fS
10
200
kHz
TTL-Compatible
2.0
VIN = VDD
VIN = 0V
VIN = VDD
VIN = 0V
65
At Output Disable, VIN = VDD
At Output Disable, VIN = 0V
IOH = –2mA
IOL = +2mA
IOH = –4mA
IOL = +4mA
0.8
V
V
0.1
–0.1
100
–0.1
µA
µA
µA
µA
2.0
–0.1
µA
µA
2.4
1.0
2.4
1.0
fS = 44.1kHz, SCLK = 384fS
fS = 96kHz, SCLK = 256fS
fS = 192kHz, SCLK = 128fS
fS = 44.1kHz
fS = 96kHz
fS = 192kHz
EIAJ, A-Weighted, fS =44.1kHz
A-Weighted, fS = 96kHz
A-Weighted, fS =192kHz
EIAJ, A-Weighted, fS =44.1kHz
A-Weighted, fS = 96kHz
A-Weighted, fS = 192kHz
fS = 44.1kHz
fS = 96kHz
fS = 192kHz
102
100
98
100
100
100
96
96
VO = 0.5VCC at Bipolar Zero
Full Scale (0dB)
AC Load
0.0015
0.0020
0.0025
0.6
0.7
0.8
106
105
104
105
104
104
102
101
102
0.0035
0.0050
0.0060
0.8
1.0
1.2
%
%
%
%
%
%
dB
dB
dB
dB
dB
dB
dB
dB
dB
±1.0
±1.0
±30
±3.0
±3.0
±60
% of FSR
% of FSR
mV
62% of VCC
50% VCC
Vp-p
V
kΩ
5
±0.002dB
–3dB
0.454fS
0.490fS
0.546fS
Stopband = 0.546fS
Stopband = 0.567fS
±0.002
–75
–82
±0.002dB
–3dB
0.274fS
0.454fS
0.732fS
Stopband = 0.732fS
–82
V
V
V
V
±0.002
Hz
Hz
Hz
dB
dB
dB
Hz
Hz
Hz
dB
dB
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
PCM1737
2
SPECIFICATIONS (Cont.)
All specifications at +25°C, +VCC = +5V, +VDD = +3.3V, system clock = 384fS (fS = 44.1kHz) and 24-bit data, unless otherwise noted.
PCM1737E
PARAMETER
CONDITIONS
DIGITAL FILTER PERFORMANCE (cont.)
Filter Characteristics, Slow Roll-Off 2
Passband
MIN
TYP
MAX
UNITS
0.072fS
0.363fS
34/fS
±0.1
Hz
Hz
Hz
dB
dB
sec
dB
–0.03
–0.20
190
dB
dB
kHz
±0.01dB
–3dB
Stopband
Passband Ripple
Stopband Attenuation
Delay Time
De-Emphasis Error
0.952f S
Stopband = 0.732fS
ANALOG FILTER PERFORMANCE
Frequency Response
±0.002
–49
f = 20kHz
f = 44kHz
–3dB
Cut-Off Frequency
POWER SUPPLY REQUIREMENTS
Voltage Range
VDD
VCC
Supply Current
IDD(6)
+3.0
+4.5
VDD = +3.3V
fS = 44.1kHz
fS = 96kHz, 256fS
f S = 192kHz, 128fS
VCC = 5.0V
fS = 44.1kHz
fS = 96kHz, 256fS
f S = 192kHz, 128fS
VDD = 3.3V, VCC = 5.0V
fS = 44.1kHz
fS = 96kHz, 256fS
f S = 192kHz, 128fS
ICC
Power Dissipation
TEMPERATURE RANGE
Operation
Storage
Thermal Resistance, θJA
+3.3
+5.0
+3.6
+5.5
V
V
8.5
16.5
19.5
12.0
mA
mA
mA
13.0
14.0
14.5
18.0
mA
mA
mA
93
124
137
130
mW
mW
mW
+70
+125
°C
°C
°C/W
0
–55
100
NOTES: (1) Pins 8, 9, 26, 27, 28 (TEST1, TEST2, MDI, MC, ML). (2) Pins 23, 24 (ZEROL, ZEROR). (3) Pin 4 (CLKO). (4) Analog performance specifications
are tested with Shibasoku #725 THD Meter 400Hz, HPF on, 30kHz LPF on, average mode with 20kHz bandwidth limiting. The load connected to the analog
output is 5kΩ or larger, AC-coupled. (5) SNR is tested with Infinite Zero Detection off. (6) CLKO is disabled.
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
DISCHARGE SENSITIVITY
Power Supply Voltage, +VDD ............................................................ +4.0V
+VCC ............................................................ +6.5V
+VCC to +VDD Difference ................................................................... ±0.1V
Digital Input Voltage ........................................................... –0.2V to +5.5V
Digital Output Voltage(1) ........................................... –0.2V to (VDD + 0.2V)
Input Current (except power supply) ............................................... ±10mA
Power Dissipation .......................................................................... 650mW
Operating Temperature Range ............................................. 0°C to +70°C
Storage Temperature ...................................................... –55°C to +125°C
Lead Temperature (soldering, 5s) ................................................. +260°C
Package Temperature (IR reflow, 10s) .......................................... +235°C
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER
PCM1737E
28-Lead SSOP
324
0°C to +70°C
PCM1737E
"
"
"
"
"
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(1)
TRANSPORT
MEDIA
PCM1737E
PCM1737E/2K
Rails
Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces
of “PCM1737E/2K” will get a single 2000-piece Tape and Reel.
®
3
PCM1737
BLOCK DIAGRAM
PCM1737
BCLK
LRCK
DATA
4x/8x
Oversampling
Digital Filter
with
Function
Controller
TEST1
TEST2
RSTB
MC
VOUTL
VCOML
Enhanced
Multi-level
Delta-Sigma
Modulator
Mode
Control
I/F
ML
Output Amp and
Low-Pass Filter
DAC
Audio
Serial
I/F
Output Amp and
Low-Pass Filter
DAC
MDI
VOUTR
VCOMR
MDO
System Clock
PIN CONFIGURATION
VCCR
GNDR
VCCL
VCCA
VSS
VDD
ZEROL
CLKO
GNDL
Power Supply
Zero Detect
GNDA
System Clock
Manager
ZEROR
SCLK
PIN ASSIGNMENTS
Top View
SSOP
PIN
NAME
I/O
1
LRCK
I
DESCRIPTION
Left/Right Word Clock(1)
2
DATA
I
Data In for Left/Right Channels(1)
Bit Clock(1)
3
BCLK
I
4
CLKO
O
System Clock Output
5
SCLK
I
System Clock Input(1)
6
VSS
—
Digital Ground
7
VDD
—
Digital Supply, +3.3V.
8
TEST1
I
Test Pin(2). Must be connected to
ground (VSS).
9
TEST2
I
Test Pin(2). Must be connected to
ground (VSS).
LRCK
1
28
ML
DATA
2
27
MC
BCLK
3
26
MDI
CLKO
4
25
MDO
SCLK
5
24
ZEROR
10
—
Analog Supply for Right Channel, +5V
6
23
VCCR
VSS
ZEROL
11
GNDR
—
Analog Ground for Right Channel
VDD
7
22
RSTB
12
VCOMR
—
Common for Right Channel
13
VOUTR
O
Analog Output for Right Channel
14
GNDA
—
Analog Ground
15
VCCA
—
Analog Supply, +5V
PCM1737E
TEST1
8
21
NC
TEST2
9
20
NC
VCCR
10
19
VCCL
GNDR
11
18
GNDL
VCOMR
12
VOUTR
13
GNDA
14
17
16
15
VCOML
VOUTL
VCCA
16
VOUTL
O
Analog Output for Left Channel
17
VCOML
—
Common for Left Channel
18
GNDL
—
Analog Ground for Left Channel
19
VCCL
—
Analog Supply for Left Channel, +5V
20
NC
—
Not Connected
21
NC
—
Not Connected
22
RSTB
I
Reset, Active Low(2).
23
ZEROL
O
Zero Flag for Left Channel
24
ZEROR
O
Zero Flag for Right Channel
25
MDO
O
Mode Data Out(3)
26
MDI
I
Mode Data In(2)
27
MC
I
Mode Clock(2)
28
ML
I
Mode Latch(2)
NOTES: (1) Schmitt-Trigger input, 5V tolerant. (2) Schmitt-Trigger input with
internal pull-down, 5V tolerant. (3) Tri-state output.
®
PCM1737
4
TYPICAL PERFORMANCE CURVES
All specifications at TA = +25°C, VDD = VCC = 5V, SYSCLK = 384fS (fS = 44.1kHz), and 24-bit input data, unless otherwise noted.
DIGITAL FILTER
Digital Filter (De-Emphasis Off, fS = 44.1kHz)
PASSBAND RIPPLE
(Sharp Roll-Off)
FREQUENCY RESPONSE
(Sharp Roll-Off)
0
0.003
–20
0.002
Amplitude (dB)
Amplitude (dB)
–40
–60
–80
–100
0.001
0
–0.001
–120
–0.002
–140
–160
–0.003
0
0.5
1
1.5
2
2.5
3
3.5
0
4
0.1
0.2
0.3
0.4
Frequency (x fS)
Frequency (x fS)
FREQUENCY RESPONSE
(Slow Roll-Off 1)
TRANSITION CHARACTERISTICS
(Slow Roll-Off 1)
0.5
0
0
–2
–20
–4
Amplitude (dB)
Amplitude (dB)
–40
–60
–80
–100
–6
–8
–10
–12
–14
–16
–120
–18
–20
–140
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
4.0
0.2
0.3
0.4
Frequency (x fS)
FREQUENCY RESPONSE
(Slow Roll-Off 2)
TRANSITION CHARACTERISTICS
(Slow Roll-Off 2)
0.5
0.6
0.5
0.6
0
0
–1
–20
–2
Amplitude (dB)
–40
Amplitude (dB)
0.1
Frequency (x fS)
–60
–80
–100
–3
–4
–5
–6
–7
–8
–120
–9
–10
–140
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
4.0
0.1
0.2
0.3
0.4
Frequency (x fS)
Frequency (x fS)
®
5
PCM1737
TYPICAL PERFORMANCE CURVES (Cont.)
All specifications at TA = +25°C, VDD = VCC = 5V, SYSCLK = 384fS (fS = 44.1kHz), and 24-bit input data, unless otherwise noted.
DIGITAL FILTER
DE-EMPHASIS FREQUENCY RESPONSE (fS = 32kHz)
0
–2
–4
–6
–8
–10
Level (dB)
Level (dB)
De-Emphasis Error
0
2
4
6
8
10
12
DE-EMPHASIS ERROR (fS = 32kHz)
0.5
0.3
0.1
–0.1
–0.3
–0.5
0
14
2
4
Level (dB)
Level (dB)
DE-EMPHASIS FREQUENCY RESPONSE (fS = 44.1kHz)
0
–2
–4
–6
–8
–10
0
2
4
6
8
10
12
14
16
18
0
20
Level (dB)
Level (dB)
2
4
6
8
10
12
14
10
12
14
2
4
6
8
10
12
14
16
18
20
20
22
Frequency (kHz)
DE-EMPHASIS FREQUENCY RESPONSE (fS = 48kHz)
0
8
DE-EMPHASIS ERROR (fS = 44.1kHz)
0.5
0.3
0.1
–0.1
–0.3
–0.5
Frequency (kHz)
0
–2
–4
–6
–8
–10
6
Frequency (kHz)
Frequency (kHz)
16
18
20
DE-EMPHASIS ERR0R (fS = 48kHz)
0.5
0.3
0.1
–0.1
–0.3
–0.5
0
22
2
4
6
8
10
12
14
16
18
Frequency (kHz)
Frequency (kHz)
ANALOG DYNAMIC PERFORMANCE
Supply Voltage Characteristics
TOTAL HARMONIC DISTORTION + NOISE vs VCC
(VDD = 3.3V)
10
110
192kHz, 128fS
108
1
–60dB
Dynamic Range (dB)
THD+N (%)
DYNAMIC RANGE vs VCC
(VDD = 3.3V)
44.1kHz, 384fS
0.1
0.01
192kHz, 128fS
0dB
0.001
44.1kHz, 384fS
106
104
102
192kHz, 128fS
100
98
44.1kHz, 384fS
0.0001
96
4.0
4.5
5.0
5.5
6.0
4.0
VCC (V)
5.0
VCC (V)
®
PCM1737
4.5
6
5.5
6.0
TYPICAL PERFORMANCE CURVES (Cont.)
All specifications at TA = +25°C, VDD = VCC = 5V, SYSCLK = 384fS (fS = 44.1kHz), and 24-bit input data, unless otherwise noted.
ANALOG DYNAMIC PERFORMANCE (con.t)
Supply Voltage Characteristics
SIGNAL-TO-NOISE RATIO vs VCC
(VDD = 3.3V)
110
CHANNEL SEPARATION vs VCC
110
108
44.1kHz, 384fS
106
SNR (dB)
Channel Separation (dB)
108
104
102
192kHz, 128fS
100
106
44.1kHz, 384fS
104
102
100
192kHz, 128fS
98
98
96
96
4.0
4.5
5.0
5.5
4.0
6.0
4.5
5.0
5.5
6.0
VCC (V)
VCC (V)
Temperature Characteristics
TOTAL HARMONIC DISTORTION + NOISE
vs TEMPERATURE
10
110
192kHz, 128fS
108
1
–60dB
Dynamic Range (dB)
THD+N (%)
DYNAMIC RANGE vs TEMPERATURE
(VDD = 3.3V)
44.1kHz, 384fS
0.1
192kHz, 128fS
0.01
0dB
44.1kHz, 384fS
106
104
102
192kHz, 128fS
100
0.001
98
44.1kHz, 384fS
0.0001
96
4.0
4.5
5.0
5.5
6.0
–25
25
50
75
Temperature (°C)
SIGNAL-TO-NOISE RATIO vs TEMPERATURE
(VDD = 3.3V)
CHANNEL SEPARATION vs TEMPERATURE
(VDD = 3.3V)
110
110
108
100
Channel Separation (dB)
108
44.1kHz, 384fS
106
SNR (dB)
0
VCC (V)
104
102
192kHz, 128fS
100
98
106
44.1kHz, 384fS
104
102
100
192kHz, 128fS
98
96
96
–25
0
25
50
75
100
–25
Temperature (°C)
0
25
50
75
100
Temperature (°C)
®
7
PCM1737
SYSTEM CLOCK AND RESET
FUNCTIONS
POWER-ON AND EXTERNAL RESET FUNCTIONS
The PCM1737 includes a power-on reset function. Figure 2
shows the operation of this function. The system clock input
at SCLK should be active for at least one clock period prior
to VDD = 2.0V. With the system clock active and VDD >
2.0V, the power-on reset function will be enabled. The
initialization sequence requires 1024 system clocks from the
time VDD > 2.0V. After the initialization period, the PCM1737
will be set to its reset default state, as described in the Mode
Control Register section of this data sheet.
SYSTEM CLOCK INPUT
The PCM1737 requires a system clock for operating the
digital interpolation filters and multi-level delta-sigma modulators. The system clock is applied at the SCLK input (pin 5).
Table I shows examples of system clock frequencies for
common audio sampling rates.
Figure 1 shows the timing requirements for the system clock
input. For optimal performance, it is important to use a clock
source with low phase jitter and noise. Burr-Brown’s
PLL1700 multi-clock generator is an excellent choice for
providing the PCM1737 system clock.
The PCM1737 also includes an external reset capability
using the RSTB input (pin 22). This allows an external
controller or master reset circuit to force the PCM1737 to
initialize to its reset default state.
Figure 3 shows the external reset operation and timing. The
RSTB pin is set to logic ‘0’ for a minimum of 20ns. The
RSTB pin is then set to a logic “1” state, which starts the
initialization sequence which lasts for 1024 system clock
periods. After the initialization sequence is complete, the
PCM1737 will be set to its reset default state, as described
in the Mode Control Register section of this data sheet.
SYSTEM CLOCK OUTPUT
A buffered version of system clock input is available at the
CLKO output (pin 4). CLKO can operate at either full
(fSCLK) or half (fSCLK/2) rate. The CLKO output frequency
may be programmed using the CLKD bit of Control Register
20. The CLKO output pin can also be enabled or disabled
using the CLKE bit of Control Register 20. The default is
CLKO enabled.
SYSTEM CLOCK FREQUENCY (fSCLK)
(MHz)
SAMPLING FREQUENCY
(fS)
128fS
192fS
256fS
384fS
512fS
768fS
16kHz
32kHz
44.1kHz
48kHz
88.2kHz
96kHz
176.4kHz
192
—
—
—
—
—
12.2880
22.5792
24.5760
—
—
—
—
—
18.4320
33.8688
36.8640
4.0960
8.1920
11.2896
12.2880
22.5792
24.5760
See Note 2
See Note 2
6.1440
12.2880
16.9344
18.4320
33.8688
36.8640
See Note 2
See Note 2
8.1920
16.3840
22.5792
24.5760
45.1584
49.1520
See Note 2
See Note 2
12.2880
24.5760
33.8688
36.8640
See Note 1
See Note 1
See Note 2
See Note 2
NOTE: (1) The 768fS system clock rate is not supported for fS > 64kHz. (2) This system clock rate is not supported for the given sampling frequency.
TABLE I. System Clock Rates for Common Audio Sampling Frequencies.
tSCLKH
2.0V
“H”
SCLK
0.8V
“L”
fSCLK
tSCLKL
System Clock Pulse Width High tSCLKH
System Clock Pulse Width Low tSCLKL
FIGURE 1. System Clock Input Timing.
®
PCM1737
8
: 7ns min
: 7ns min
Audio Data Formats and Timing
The external reset is especially useful in applications
where there is a delay between PCM1737 power up and
system clock activation. In this case, the RSTB pin should
be held at a logic ‘0’ level until the system clock has been
activated. The RSTB pin may then be set to a logic ‘1”
state to start the initialization sequence.
The PCM1737 supports industry-standard audio data formats,
including standard, I2S, and left-justified. The data formats
are shown in Figure 4. Data formats are selected using the
format bits, FMT[2:0], in Control Register 20. The default
data format is 24-bit standard. All formats require Binary
Two’s Complement, MSB-first audio data. Figure 5 shows a
detailed timing diagram for the serial audio interface.
AUDIO SERIAL INTERFACE
The audio serial interface for the PCM1737 is comprised of
a 3-wire synchronous serial port. It includes LRCK (pin 1),
BCLK (pin 3), and DATA (pin 2). BCLK is the serial
audio bit clock, and it is used to clock the serial data
present on DATA into the audio interface’s serial shift
register. Serial data is clocked into the PCM1737 on the
rising edge of BCLK. LRCK is the serial audio left/right
word clock. It is used to latch serial data into the serial
audio interface’s internal registers.
SERIAL CONTROL INTERFACE
The serial control interface is a 4-wire serial port which
operates asynchronously to the serial audio interface. The
serial control interface is utilized to program and read the onchip mode registers. The control interface includes MDO (pin
25), MDI (pin 26), MC (pin 27), and ML (pin 28). MDO is the
serial data output, used to read back the values of the mode
registers. MDI is the serial data input, used to program the
mode registers. MC is the serial bit clock, used to shift data in
and out of the control port. ML is the control port latch clock.
Both LRCK and BCLK must be synchronous to the system
clock. Ideally, it is recommended that LRCK and BCLK be
derived from the system clock input or output, SCLK or
CLKO. The left/right clock, LRCK, is operated at the
sampling frequency, fS. The bit clock, BCLK, may be
operated at 48 or 64 times the sampling frequency.
2.4V
VCC = VDD
2.0V
1.6V
Reset
Reset Removal
Internal Reset
1024 system clocks
System Clock
(SCLK)
FIGURE 2. Power-On Reset Timing.
RSTB
tRST(1)
Reset
Reset Removal
Internal Reset
1024 system clocks
System Clock
(SCLK)
NOTE: (1) tRST = 20ns min.
FIGURE 3. External Reset Timing.
®
9
PCM1737
®
PCM1737
10
16 17 18
18 19 20
22 23 24
18-Bit Right-Justified
DATA
20-Bit Right-Justified
DATA
24-Bit Right-Justified
DATA
MSB
1
2
3
4
5
MSB
1
2
3
MSB
1
2
Lch
3
MSB
1
1
2
3
FIGURE 4. Audio Data Input Formats.
DATA
BCLK
(= 48fS or 64fS)
LRCK
MSB
1
2
3
Lch
(3) 24-Bit I2S Data Format; Lch = LOW, Rch = HIGH
DATA
BCLK
(= 48fS or 64fS)
LRCK
22
22
Lch
LSB
23 24
23 24
(2) 24-Bit Left-Justified Data Format; Lch = HIGH, Rch = LOW
14 15 16
16-Bit Right-Justified
DATA
BCLK
(= 48fS or 64fS)
LRCK
(1) Standard Data Format; Lch = HIGH, Rch = LOW
2
3
1/fS
2
MSB
1
2
MSB
1
1/fS
3
3
LSB
22 23 24
LSB
18 19 20
LSB
16 17 18
LSB
14 15 16
MSB
1
1/fS
Rch
2
3
22
22
Rch
4
LSB
23 24
2
LSB
23 24
5
MSB
1
3
MSB
1
2
Rch
3
MSB
1
1
2
2
3
LSB
22 23 24
LSB
18 19 20
LSB
16 17 18
LSB
14 15 16
REGISTER WRITE OPERATION
MC, corresponding to the 16 bits of the control data word on
MDI. After the sixteenth clock cycle has completed, ML is
set to logic ‘1’ to latch the data into the indexed mode control
register.
All Write operations for the serial control port use 16-bit
data words. Figure 6 shows the control data word format.
The most significant bit is the Read/Write (R/W) bit. When
set to ‘0’, this bit indicates a Write operation. There are
seven bits, labeled IDX[6:0], that set the register index (or
address) for the Write operation. The least significant eight
bits, D[7:0], contain the data to be written to the register
specified by IDX[6:0].
SINGLE REGISTER READ OPERATION
Read operations utilize the 16-bit control word format shown
in Figure 6. For Read operations, the Read/Write (R/W) bit
is set to ‘1’. Read operations ignore the index bits, IDX[6:0],
of the control data word. Instead, the REG[6:0] bits in
Control Register 21 are used to set the index of the register
that is to be read during the Read operation. Bits IDX[6:0]
should be set to 00H for Read operations.
Figure 7 shows the functional timing diagram for writing the
serial control port. ML is held at a logic ‘1’ state until a
register needs to be written. To start the register write cycle,
ML is set to logic ‘0’. Sixteen clocks are then provided on
LRCK
50% of VDD
tBCH
tBCL
tLB
BCK
50% of VDD
tBCY
tBL
50% of VDD
DATA1-DATA3
tDH
tDS
SYMBOL
PARAMETER
MIN
BCK Pulse Cycle Time
BCK High Level Time
BCK Low Level Time
BCK Rising Edge to LRCK Edge
LRCK Falling Edge to BCK Rising Edge
DIN Set Up Time
DIN Hold Time
t BCY
t BCH
t BCL
t BL
t LB
t DS
t DH
MAX
48 or 64fS
UNITS
(1)
35
35
10
10
10
10
ns
ns
ns
ns
ns
ns
NOTE: (1) fS is the sampling frequency (e.g., 44.1kHz, 48kHz, 96kHz, etc.)
FIGURE 5. Audio Interface Timing.
MSB
R/W
LSB
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0
D7
D6
D5
D4
Register Index (or Address)
D3
D2
D5
D4
D3
D2
D1
D0
Register Data
Read/Write Operation
0 = Write Operation
1 = Read Operation (register index is ignored)
FIGURE 6. Control Data Word Format for MDI.
ML
MC
MDI
X
0
IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7
D6
D5
D4
D3
D2
D1
D0
X
X
D15 D14
FIGURE 7. Write Operation Timing.
®
11
PCM1737
®
PCM1737
12
I
O
I
O
I
O
I
O
Write
0
1
X = Don't care
0
0
0
0
1
0
1
0
0
0
0
High Impedance
0
0
0
D7
X
D6
X
D5
X
D3
X
INDEX “1”
D4
X
D2
X
FIGURE 9. Read Operation Timing with INC = 1 (Auto-Increment Read).
MDO
MDI
MC
ML
D1
X
High Impedance
Read Register Index
D0
X
D7
X
REG6 REG5 REG4 REG3 REG2 REG1 REG0
Writing Register 21 with INC and REG[6:0] Data
0
FIGURE 8. Read Operation Timing with INC = 0 (Single Register Read).
MDO
MDI
MC
ML
X
D6
X
X
D4
X
D3
X
Read
0
0
X
D2
INDEX “N – 1”
D5
X
1
0
D1
X
0
D0
X
0
0
X
D7
X
D6
X
D7
D5
X
X
X
X
X
X
X
X
INDEX “N”
D4
X
D5
D3
D6
D2
X
X
D3
D1
D4
D0
X
D2
D0
High Impedance
X
D1
Data from Register Indexed by REG[6:0]
X
Register Read Cycle
0
Figure 8 details the Read operation. First, Control Register
21 must be written with the index of the register to be read
back. In addition, the INC bit must be set to logic ‘0’ in
order to disable the auto-increment read function. The Read
cycle is then initiated by setting ML to logic ‘0’ and setting
the R/W bit of the control data word to logic ‘1’, indicating
a Read operation. MDO remains at a high impedance state
until the last 8 bits of the 16-bit read cycle, which corresponds to the 8 data bits of the register indexed by the
REG[6:0] bits of Control Register 21. The Read cycle is
complete when ML is set to ‘1’, immediately after the MC
clock cycle for the least significant bit of indexed control
register has completed.
Figure 9 shows the timing for the Auto-Increment Read
operation. The operation begins by writing Control Register
21, setting INC to ‘1’ and setting REG[6:0] to the last
register to be read in the sequence. The actual Read operation starts on the next High to Low transition of the ML pin.
The Read cycle starts by setting the R/W bit of the control
word to ‘1’, and setting all of the IDX[6:0] bits to ‘0’. All
subsequent bits input on the MDI are ignored while ML is
set to ‘0’. For the first 8 clocks of the Read cycle, MDO is
set to a high impedance state. This is followed by a sequence
of 8-bit words, each corresponding the data contained in
Control Registers 1 through N, where N is defined by the
REG[6:0] bits in Control Register 21. The Read cycle is
complete when ML is set to ‘1’, immediately after the MC
clock cycle for the least significant bit of Control Register N
has completed.
AUTO-INCREMENT READ OPERATION
The Auto-Increment Read function allows for multiple registers to be read sequentially. The Auto-Increment function
is enabled by setting the INC bit of Control Register 21 to
‘1’. The sequence always starts with Register 1, and ends
with the register indexed by the REG[6:0] bits in Control
Register 21.
CONTROL INTERFACE TIMING REQUIREMENTS
Figure 10 shows a detailed timing diagram for the serial
control interface. Pay special attention to the setup and hold
times, as well as tMLS and tMLH, which define minimum delays
between edges of the ML and MC clocks. These timing
parameters are critical for proper control port operation.
tMHH
50% of VDD
ML
tMLS
tMCH
tMCL
tMLH
50% of VDD
MC
tMCY
LSB
MDI
50% of VDD
tMOS
tMDS
tMDI
LSB
50% of VDD
MDO
SYMBOL
tMCY
tMCL
tMCH
tMHH
tMLS
tMLH
tMDI
tMDS
tMOS
PARAMETER
MIN
MC Pulse Cycle Time
MC Low Level Time
MC High Level Time
ML High Level Time
ML Falling Edge to MC Rising Edge
ML Hold Time(1)
Hold Time
MDL Set Up Time
MC Falling Edge to MDSO Stable
100
50
50
300
20
20
15
20
MAX
UNITS
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE: (1) MC rising edge for LSB to ML rising edge.
FIGURE 10. Control Interface Timing.
®
13
PCM1737
MODE CONTROL REGISTERS
User-Programmable Mode Controls
Register Map
The PCM1737 includes a number of user programmable
functions which are accessed via control registers. The
registers are programmed using the Serial Control Interface
which was previously discussed in this data sheet. Table II
lists the available mode control functions, along with their
reset default conditions and associated register index.
The mode control register map is shown in Table IV. Each
register includes a R/W bit, which determines whether a
register read (R/W =1) or write (R/W = 0) operation is
performed. Each register also includes an index (or address)
indicated by the IDX[6:0] bits.
FUNCTION
Digital Attenuation Control, 0dB to –63dB in 0.5dB Steps
Soft Mute Control
RESET DEFAULT
REGISTER
0dB, No Attenuation
16 and 17
AT1[7:0]
Mute Disabled
18
MUT[2:0]
Digital Attenuation Speed Select
Digital Attenuation Control
2/fS
18
ATTS
Attenuator Disabled
18
ATLD
Infinite Zero Detect Mute
Disabled
18
INZD
64fS Oversampling
18
OVER
DAC1 and DAC2 Enabled
19
DAC[2:1]
De-Emphasis Disabled
19
DM12
44.1kHz
19
DMF[2:1]
24-Bit Standard Format
20
FMT[2:0]
CLKO Enabled
20
CLKE
Full Rate (= fSCLK)
20
CLKD
FLT[1:0]
Oversampling Rate Control (64fS or 128fS)
DAC Operation Control
De-Emphasis Function Control
De-Emphasis Sample Rate Selection
Audio Data Format Control
BIT(S)
CLKO Output Enable
CLKO Frequency Selection
Digital Filter Roll-Off Control
Sharp Roll-Off
20
4x/8x Digital Interpolation Control
8x Interpolation
20
X4DS
Read Register Index Control
REG[6:0] = 01H
21
REG[6:0]
Read Auto-Increment Control
Auto-Increment Disabled
21
INC
TABLE II. User-Programmable Mode Controls.
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 16
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT17
AT16
AT15
AT14
AT13
AT12
AT11
AT10
Register 17
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT27
AT26
AT25
AT24
AT23
AT22
AT21
AT20
Register 18
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
res
OVER
res
INZD
ATLD
ATTS
MUT2 MUT1
Register 19
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
res
DMF1
DMF0
DM12
res
res
DAC2 DAC1
Register 20
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
X4DS
FLT1
FLT0
CLKD
CLKE
FMT2
FMT1 FMT0
Register 21
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
INC
REG6
REG5
REG4
REG3
REG2
REG1 REG0
TABLE III. Mode Control Register Map.
®
PCM1737
14
REGISTER DEFINITIONS
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Register 16
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT17
AT16
AT15
AT14
AT13
AT12
AT11
AT10
Register 17
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
AT27
AT26
AT25
AT24
AT23
AT22
AT21
AT20
R/W
Read/Write Mode Select
When R/W = 0, a Write operation is performed.
When R/W = 1, a Read operation is performed.
Default Value: 0
ATx[7:0]
Digtial Attenuation Level Setting
Where x = 1 or 2, corresponding to the DAC output VOUTL (x = 1) and VOUTR (x = 2).
These bits are Read/Write.
Default Value: 1111 1111B
Each DAC output (VOUTL and VOUTR) has a digital attenuator associated with it. The attenuator may be set from
0dB to –63dB, in 0.5dB steps. Alternately, the attenuator may be set to infinite attenuation (or mute).
The attenuation data for each channel can be set individually. However, the data load control (ATLD bit of
Control Register 18) is common to both attenuators. ATLD must be set to ‘1’ in order to change an attenuator’s
setting. The attenuation level may be set using the following formula:
Attenuation Level (dB) = 0.5dB • (ATx[7:0]DEC – 255)
Where: ATx[7:0]DEC = 0 through 255
For: ATx[7:0]DEC = 0 through 128, the attenuator is set to infinite attenuation.
The following table shows attenuator levels for various settings:
ATx[7:0]
1111 1111B
1111 1110B
1111 1101B
•
•
•
1000 0010B
1000 0001B
1000 0000B
•
•
•
0000 0000B
Decimal Value
255
254
253
•
•
•
130
129
128
•
•
•
0
Attenuator Level Setting
0dB, No Attenuation (default)
–0.5dB
–1.0dB
•
•
•
–62.5dB
–63.0dB
Mute
•
•
•
Mute
®
15
PCM1737
Register 18
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
res
OVER
res
INZD
ATLD
ATTS
R/W
Read/Write Mode Select
When R/W = 0, a Write operation is performed.
When R/W = 1, a Read operation is performed.
Default Value: 0
MUTx
Soft Mute Control
Where, x = 1 or 2, corresponding to the DAC output VOUTL (x = 1) and VOUTR ( x = 2).
These bits are Read/Write.
Default Value: 0
MUTx = 0
MUTx = 1
B1
B0
MUT2 MUT1
Mute Disabled (default)
Mute Enabled
The mute bits, MUT1 and MUT2, are used to enable or disable the Soft Mute function for the corresponding
DAC outputs, VOUTL and VOUTR. The Soft Mute function is incorporated into the digital attenuators. When Mute
is disabled (MUTx = 0), the attenuator and DAC operate normally. When Mute is enabled by setting MUTx =
1, the digital attenuator for the corresponding output will be decremented from the current setting to the infinite
attenuation, one attenuator step (0.5dB) at a time, with the rate of change programmed by the ATTS bit. This
provides ‘pop-free’ muting of the DAC output.
By setting MUTx = 0, upon returning from Soft Mute, the attenuator will be incremented one step at a time to
the previously-programeed attenuator level.
ATTS
Attenuation Rate Select
This bit is Read/Write.
Default Value: 0
ATTS = 0
ATTS = 1
Attenuation rate is 2/fS (default)
Attenuation rate is 4/fS
Changes in attenuator levels are made by incrementing or decrementing the attenuator by one step (0.5dB) for
every 2/fS or 4/fS time interval until the programmed attenuator setting is reached. This helps to minimize audible
‘clicking’, or zipper noise while the attenuator is changing levels. The ATTS bit allows the user to select the rate
at which the attenuator is decremented/incremented during level transitions.
ATLD
Attenuation Control
This bit is Read/Write.
Default Value: 0
ATLD = 0
ATLD = 1
Attenuator Disabled (default)
Attenuator Enabled
The ATLD bit must be set to logic ‘1’ in order for the attenuators to function. Setting ATLD to logic ‘0’ will
disable the attenuator function and cause the current attenuator data to be lost.
Set ATLD = 1 immediately after reset.
®
PCM1737
16
Register 18 (cont.)
INZD
Infinite Zero Detect Mute Control
This bit is Read/Write.
Default Value: 0
INZD = 0
INZD = 1
Infinite Zero Detect Mute Disabled (default)
Infinite Zero Detect Mute Enabled
The INZD bit is used to enable or disable the Zero Detect Mute function described in the Zero Flag and Infinite
Zero Detect Mute section in this data sheet. The Zero Detect Mute function is independent of the Zero Flag
output operation, so enabling or disabling the INZD bit has no effect on the Zero Flag outputs (ZEROL and
ZEROR).
OVER
Oversampling Rate Control
This bit is Read/Write.
Default Value: 0
OVER = 0
OVER = 1
64x Oversampling (default)
128x Oversampling
Sets the oversampling rate of the delta-sigma D/A converters. The 128x setting can only be used for sampling
frequencies up to 96kHz. The 64x setting must be used for sampling frequencies greater than 96kHz.
®
17
PCM1737
REGISTER 19
R/W
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
res
DMF1
DMF0
DM12
res
res
B1
B0
DAC2 DAC1
Read/Write Mode Select
When R/W = 0, a Write operation is performed.
When R/W = 1, a Read operation is performed.
Default Value: 0
DACx
DAC Operation Control
Where x = 1 or 2, corresponding to the DAC output VOUTL (x = 1) or VOUTR (x = 2).
These bits are Read/Write.
Default Value: 0
DACx = 0
DACx = 1
DAC Operation Enabled (default)
DAC Operation Disabled
The DAC operation controls are used to enable and disable the DAC outputs, V OUTL and VOUTR. When
DACx = 0, the corresponding output will generate the audio waveform dictated by the data present on the
DATA pin. When DACx = 1, the corresponding output will be set to the bipolar zero level, or V CC/2.
DM12
Digital De-Emphasis Function Control
This bit is Read/Write.
Default Value: 0
DM12 = 0
DM12 = 1
De-Emphasis Disabled (default)
De-Emphasis Enabled
The DM12 bit is used to enable or disable the digital de-emphasis function. Refer to the plots shown in the
Typical Performance Curves section of this data sheet.
DMF[1:0]
Sampling Frequency Selection for the De-Emphasis Function
These bits are Read/Write.
Default Value: 00B
The DMF[1:0] bits are used to select the sampling frequency used for the digital de-emphasis function when it
is enabled.
DMF[1:0]
De-Emphasis Same Rate Selection
00
01
10
11
44.1kHz (default)
48kHz
32kHz
Reserved
®
PCM1737
18
REGISTER 20
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
X4DS
FLT1
FLT0
CLKD
CLKE
FMT2
FMT1
FMT0
R/W
Read/Write Mode Select
When R/W = 0, a Write operation is performed.
When R/W = 1, a Read operation is performed.
Default Value: 0
FMT[2:0]
Audio Interface Data Format
These bits are Read/Write.
Default Value: 000B
The FMT[2:0] bits are used to select the data format for the serial audio interface. The table below shows the
available format options.
FMT[2:0]
000
001
010
011
100
101
110
111
CLKE
Audio Data Format Selection
24-Bit Standard Format, Right-Justified Data (default)
20-Bit Standard Format, Right -Justified Data
18-Bit Standard Format, Right-Justified Data
16-Bit Standard Format, Right-Justified Data
I2S Format, 16 to 24 Bits
Right-Justified Format, 16 to 24 Bits
Reserved
Reserved
CLKO Output Enable
This bit is Read/Write.
Default Value: 0
CLKE = 0
CLKE = 1
CLKO Enabled (default)
CLKO Disabled
The CLKE bit is used to enable or disable the system clock output pin, CLKO. When CLKO is enabled, it will
output either a full or half rate clock, based upon the setting of the CLKD bit. When CLKO is disabled, it is
set to a high impedance state.
CLKD
CLKO Frequency Selection
This bit is Read/Write.
Default Value: 0
CKLD = 0
CKLD = 1
Full Rate, fCLKO = fSCLK (default)
Half Rate, fCLKO = fSCLK/2
The CLKD bit is used to select the clock frequency for the CLKO pin.
®
19
PCM1737
REGISTER 20 (cont.)
FLT[1:0]
Digital Filter Roll-Off Control
These bits are Read/Write.
Default Value: 00B
FLT[1:0] = 00B
FLT[1:0] = 01B
FLT[1:0] = 10B
Sharp Roll-Off (default)
Slow Roll-Off 1
Slow Roll-Off 2
Bits FLT[1:0] allow the user to select the digital filter roll-off that is best suited to their application. Three filter
roll-off selections are available: Sharp, Slow 1, and Slow 2
The filter responses for these selections are shown in the Typical Performance Curves section of this data sheet.
Slow roll-off performance is specified for 8x interpolation (X4DS = 0) only.
X4DS
4x/8x Digital Interpolation Control
This bit is Read/Write.
Default Value: 0
X4DS = 0
X4DS = 1
8x Interpolation (default)
4x Interpolation, used for fS = 192kHz or 176.4kHz
Bit X4DS allows the user to select the oversampling rate of the digital interpolation filter. For sampling
frequencies up to 96kHz, 8x interpolation is used, while 4x interpolation is used for sampling frequencies,
greater than 96kHz.
®
PCM1737
20
REGISTER 21
R/W
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
R/W
IDX6
IDX5
IDX4
IDX3
IDX2
IDX1
IDX0
INC
REG6
REG5
REG4
REG3
REG2
REG1
REG0
Read/Write Mode Select
When R/W = 0, a Write operation is performed.
When R/W = 1, a Read operation is performed.
Default Value: 0
INC
Auto-Increment Read Control
This bit is Read/Write.
Default Value: 0
INC = 0
INC = 1
Auto-Increment Read Disabled (default)
Auto-Increment Read Enabled
The INC bit is used to enable or disable the Auto-Increment Read feature of the Serial Control Interface. Refer
to the Serial Control Interface section of this data sheet for details regarding Auto-Increment Read operation.
REG[6:0]
Read Register Index
These bits are Read/Write.
Default Value: 01H
Bits REG[6:0] are used to set the index of the register to be read when performing a Single Register Read
operation. In the case of an Auto-Increment Read operation, bits REG[6:0] indicate the index of the last register
to be read in the in the Auto-Increment Read sequence. For example, if Registers 1 through 6 are to be read
during an Auto-Increment Read operation, bits REG[6:0] would be set to 06H.
Refer to the Serial Control Interface section of this data sheet for details regarding the Single Register and AutoIncrement Read operations.
®
21
PCM1737
ANALOG OUTPUTS
VCOML AND VCOMR OUTPUTS
The PCM1737 includes two independent output channels:
VOUTL and VOUTR. These are unbalanced outputs, each
capable of driving 3.1Vp-p typical into a 5kΩ AC-coupled
load (VCC = +5V). The internal output amplifiers for VOUTL
and VOUTR are DC biased to a DC common-mode (or
bipolar zero) voltage, equal to VCC/2.
Two unbuffered common-mode voltage output pins, VCOML
(pin 17) and VCOMR (pin 12), are brought out for decoupling
purposes. These pins are nominally biased to a DC voltage
level equal to VCC/2. These pins may be used to bias external
circuits, a voltage follower is required for buffering purposes. Figure 12 shows an example of using the VCOML and
VCOMR pins for external biasing applications.
The output amplifiers include an RC continuous-time filter,
which helps to reduce the out-of-band noise energy present
at the DAC outputs due to the noise shaping characteristics
of the PCM1737’s delta-sigma D/A converters. The frequency response of this filter is shown in Figure 11. By
itself, this filter is not enough to attenuate the out-of-band
noise to an acceptable level for most applications. An
external low-pass filter is required to provide sufficient outof-band noise rejection. Further discussion of DAC postfilter circuits is provided in the Applications Information
section of this data sheet.
ZERO FLAG AND INFINITE ZERO DETECT MUTE
FUNCTIONS
The PCM1737 includes circuitry for detecting an all ‘0’ data
condition for the data input pin, DATA. This includes two
independent functions: Zero Output Flags and Zero Detect
Mute. Although the flag and mute functions are independent
of one another, the zero detection mechanism is common to
both functions.
Zero Detect Condition
Zero Detection for each output channel is independent from
the other. If the data for a given channel remains at a ‘0’
level for 1024 sample periods (or LRCK clock periods), a
Zero Detect condition exists for that channel.
ANALOG FILTER RESPONSE
10
Zero Output Flags
0
Given that a Zero Detect condition exists for one or more
channels, the Zero flag pins for those channels will be set to
a logic ‘1’state. There are Zero Flag pins for each channel,
ZEROL (pin 23) and ZEROR (pin 24). These pins can be
used to operate external mute circuits, or used as status
indicators for a microcontroller, audio signal processor, or
other digitally-controlled functions.
Level (dB)
–10
–20
–30
–40
–50
Infinite Zero Detect Mute
–60
100
1k
10k
100k
1M
Infinite Zero Detect Mute is an internal logic function. The
Zero Detect Mute can be enabled or disabled using the INZD
bit of Control Register 18. The reset default is Zero Detect
Mute disabled, INZD = 0. Given that a Zero Detect Condition exists for one or more channels, the zero mute circuitry
will immediately force the corresponding DAC output(s) to
the bipolar zero level, or VCC/2.
10M
Frequency (Hz)
FIGURE 11. Output Filter Frequency Response.
®
PCM1737
22
PCM1737
VOUTx
R2
10µF
+
R1
AV = –1, where AV = –
C1
R3
VCC
R2
R1
2
C2
3
1/2
OPA2353
1
Filtered
Output
VCOMx
+
x = L or R
10µF
(a) Using VCOM to Bias a Single-Supply Filter Stage
VCC
PCM1737
Buffered
VCOM
OPA337
VCOMx
+
10µF
x = L or R
(b) Using a Voltage Follower to Buffer VCOM when Biasing Multiple Nodes
V+
VCC
25kΩ
49.9kΩ
1%
–IN
PCM1737
VOUTx
SENSE
25kΩ
OUT
25kΩ
+IN
VCOMx
+
10µF
25kΩ
To Low-Pass
Filter Stage
REF
INA134
x = L or R
V–
(c) Using an INA134 for DC-Coupled Output
FIGURE 12. Biasing External Circuits Using the VCOM1 and VCOM2 Pins.
®
23
PCM1737
NOTE: (1) RS = 20Ω to 100Ω
RS(1)
PCM1737
From/To
Audio
Source
C1
+
C2
+
+
LRCK
ML
DATA
MC
BCLK
MDI
CLKO
MDO
SCLK
ZEROR
VSS
ZEROL
VDD
RSTB
Zero Flag
Outputs
From Host or
Master Reset
TEST1
NC
x
TEST2
NC
x
VCCR
VCCL
GNDR
GNDL
VCOMR
VCOML
VOUTR
VOUTL
GNDA
VCCA
C3
C4
To/From
Host
Controller
+
+
C10
C9
+
To
Output
Filter
Circuits
C8
C7
+
Analog
Ground
C5
+3.3V
Regulator
C6
+
C1, C4, C6, C9 = 10µF Tantalum or Aluminum Electrolytic
C2, C5 = 0.1µF Ceramic
C3, C10 = 1µF Tantalum or Aluminum Electrolytic
C7, C8 = 1-10µF Aluminum Electrolytic
+5V Analog
FIGURE 13. Basic Connection Diagram.
APPLICATIONS INFORMATION
D/A OUTPUT FILTER CIRCUITS
Delta-sigma D/A converters utilize noise-shaping techniques
to improve in-band Signal-to-Noise Ratio (SNR) performance at the expense of generating increased out-of-band
noise above the Nyquist Frequency, or fS/2. The out-ofband noise must be low-pass filtered in order to provide the
optimal converter performance. This is accomplished by a
combination of on-chip and external low-pass filtering.
CONNECTION DIAGRAMS
A basic connection diagram is shown in Figure 13, with the
necessary power supply bypassing and decoupling components. Burr-Brown recommends using the component values
shown in Figure 13 for all designs.
The use of series resistors (22Ω to 100Ω) are recommended
for SCLK, LRCK, BCLK, DATA inputs. The series resistor
combines with the stray PCB and device input capacitance
to form a low-pass filter which reduces high frequency noise
emissions and helps to dampen glitches and ringing present
on clock and data lines.
Figures 12a and 14 show the recommended external lowpass active filter circuits for dual and single-supply applications. These circuits are 2nd-order Butterworth filters using
the Multiple Feedback (MFB) circuit arrangement, which
reduces sensitivity to passive component variations over
frequency and temperature. For more information regarding
MFB active filter design, please refer to Burr-Brown Applications Bulletin AB-034.
POWER SUPPLIES AND GROUNDING
The PCM1737 requires a +5V analog supply and a +3.3V
digital supply. The +5V supply is used to power the DAC
analog and output filter circuitry, while the +3.3V supply is
used to power the digital filter and serial interface circuitry.
For best performance, the +3.3V supply should be derived
from the +5V supply using a linear regulator, as shown in
Figure 13. Burr-Brown’s REG1117-3.3 is an ideal choice for
this application.
R2
R1
Proper power supply bypassing is shown in Figure 13. The
bypass capacitors should be tantalum or aluminum electrolytic, while the 0.1µF capacitors are ceramic (X7R type is
recommended for surface-mount applications).
2
1
C2
3
OPA2134
FIGURE 14. Dual-Supply Filter Circuit.
®
PCM1737
R3
VIN
AV ≈ –
C1
24
R2
R1
R4
VOUT
Since the overall system performance is defined by the
quality of the D/A converters and their associated analog
output circuitry, high quality audio op amps are recommended for the active filters. Burr-Brown’s OPA2134 and
OPA2353 dual op amps are shown in Figures 12a and 14,
and are recommended for use with the PCM1737.
plane split/cut to allow for short, direct connections to the
digital audio interface and control signals originating from
the digital section of the board.
Separate power supplies are recommended for the digital
and analog sections of the board. This prevents the switching
noise present on the digital supply from contaminating the
analog power supply and degrading the dynamic performance of the PCM1737. In cases where a common +5V
supply must be used for the analog and digital sections, an
inductance (RF choke, ferrite bead) should be placed between the analog and digital +5V supply connections to
avoid coupling of the digital switching noise into the analog
circuitry. Figure 16 shows the recommended approach for
single-supply applications.
PCB LAYOUT GUIDELINES
A typical PCB floor plan for the PCM1600 and PCM1601 is
shown in Figure 15. A ground plane is recommended, with
the analog and digital sections being isolated from one
another using a split or cut in the circuit board. The PCM1737
should be oriented with the digital I/O pins facing the ground
Digital Power
+VD
Analog Power
DGND
AGND +5VA
+VS –VS
REG
VCC
VDD
Digital Logic
and
Audio
Processor
Output
Circuits
DGND
PCM1737
Digital
Ground
AGND
DIGITAL SECTION
ANALOG SECTION
Analog
Ground
Return Path for Digital Signals
FIGURE 15. Recommended PCB Layout.
Power Supplies
RF Choke or Ferrite Bead
+5V
AGND
+VS –VS
REG
VCC
VDD
VDD
DGND
Output
Circuits
PCM1737
AGND
Common
Ground
DIGITAL SECTION
ANALOG SECTION
FIGURE 16. Single-Supply PCB Layout.
®
25
PCM1737
–
+
4fS or 8fS
Z–1
+
Z–1
+
Z–1
+
+
Z–1
+
8-Level Quantizer
64fS or 128fS
FIGURE 17. Eight-Level Delta-Sigma Modulator.
128x Oversampling
0
–20
–20
–40
–40
Amplitude (dB)
Amplitude (dB)
64x Oversampling
0
–60
–80
–100
–120
–60
–80
–100
–120
–140
–140
–160
–160
–180
–180
0
1
2
3
4
5
6
7
8
0
Frequency (fS)
1
2
3
4
5
6
7
8
Frequency (fS)
FIGURE 18. Quantization Noise Spectrum (64x/128x oversampling).
The combined oversampling rate of the delta-sigma modulator and the interpolation filter is 64fS or 128fS.
The theoretical quantization noise performance of the
8-level delta-sigma modulator is shown in Figure 18. The
enhanced multi-level delta-sigma architecture also has advantages for input clock jitter sensitivity due to the multilevel quantizer, with the simulated jitter sensitivity shown in
Figure 19.
CLOCK JITTER
125
Dynamic Range (dB)
120
115
110
105
100
KEY PERFORMANCE
PARAMETERS AND MEASUREMENT
95
90
0
100
200
300
400
500
600
This section provides information on how to measure key
dynamic performance parameters for the PCM1737. In all
cases, an Audio Precision System Two Cascade or equivalent
audio measurement system is utilized to perform the testing.
Jitter (ps)
FIGURE 19. Jitter Sensitivity.
THEORY OF OPERATION
TOTAL HARMONIC DISTORTION + NOISE
The delta-sigma section of PCM1737 is based on a 8-level
amplitude quantizer and a 4th-order noise shaper. This section
converts the oversampled input data to 8-level delta-sigma format.
A block diagram of the 8-level delta-sigma modulator is
shown in Figure 17. This 8-level delta-sigma modulator has
the advantage of stability and clock jitter sensitivity over the
typical one-bit (2-level) delta-sigma modulator.
Total Harmonic Distortion + Noise (THD+N) is a significant
figure of merit for audio D/A converters since it takes into
account both harmonic distortion and all noise sources
within a specified measurement bandwidth. The true rms
value of the distortion and noise is referred to as THD+N.
For the PCM1737, THD+N is measured with a full scale,
1kHz digital sine wave as the test stimulus at the input of the
®
PCM1737
26
The measurement setup for the dynamic range measurement
is shown in Figure 21, and is similar to the THD+N test
setup discussed previously. The differences include the
bandlimit filter selection, the additional A-Weighting filter,
and the –60dBFS input level.
DAC. The digital generator is set to 24-bit audio word
length and a sampling frequency of 44.1kHz, 96kHz, or
192kHz. The digital generator output is taken from the
unbalanced S/PDIF connector of the measurement system.
The S/PDIF data is transmitted via a coaxial cable to the
digital audio receiver on the DEM-DAI1737 demo board.
The receiver is then configured to output 24-bit data in
either I2S or left-justified data format. The DAC audio
interface format is programmed to match the receiver output
format. The analog output is then taken from the DAC post
filter and connected to the analog analyzer input of the
measurment system. The analog input is band limited using
filters resident in the analyzer. The resulting THD+N is
measured by the analyzer and displayed by the measurement
system.
IDLE CHANNEL SIGNAL-TO-NOISE RATIO
The SNR test provides a measure of the noise floor of the
D/A converter. The input to the D/A is all 0’s data, and the
D/A converter’s Infinite Zero Detect Mute function must
be disabled (default condition at power up for the PCM1737).
This ensures that the delta-sigma modulator output is connected to the output amplifier circuit so that idle tones (if
present) can be observed and effect the SNR measurement.
The dither function of the digital generator must also be
disabled to ensure an all ‘0’s data stream at the input of the
D/A converter.
DYNAMIC RANGE
Dynamic range is specified as A-Weighted, THD+N measured with a –60dBFS, 1kHz digital sine wave stimulus at
the input of the D/A converter. This measurement is designed to give a good indicator of how the DAC will
perform given a low-level input signal.
The measurement setup for SNR is identical to that used for
dynamic range, with the exception of the input signal level.
(see the notes provided in Figure 21).
Evaluation Board
DEM-DAI1737
S/PDIF
Receiver
2nd-Order
Low-Pass
Filter
PCM1737
f–3dB = 54kHz or 108kHz
S/PDIF
Output
Digital
Generator
Analyzer
and
Display
0dBFS,
1kHz Sine Wave
RMS Mode
20kHz
Apogee
Filter
Band Limit
HPF = 22Hz
LPF = 30kHz
Notch Filter
fC = 1kHz
FIGURE 20. Test Setup for THD+N Measurement.
Evaluation Board
DEM-DAI1737
S/PDIF
Receiver
PCM1737(1)
2nd-Order
Low-Pass
Filter
f–3dB = 54kHz or 108kHz
S/PDIF
Output
NOTES: (1) Infinite Zero Detect Mute disabled.
(2) Results without A-Weighting will be
approximately 3dB worse.
Digital
Generator
Analyzer
and
Display
0% Full Scale,
Dither Off (SNR) or
–60dBFS,
1kHz Sine Wave
(Dynamic Range)
RMS Mode
A-Weight
Filter(2)
Band Limit
HPF = 22Hz
LPF = 22kHz
Notch Filter
fC = 1kHz
FIGURE 21. Test Set-Up for Dynamic Range and SNR Measurements.
®
27
PCM1737
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
PCM1737E
ACTIVE
SSOP
DB
28
47
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
PCM1737E
PCM1737E/2K
ACTIVE
SSOP
DB
28
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
PCM1737E
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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