SM72482
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SNVS696C – JANUARY 2011 – REVISED APRIL 2013
Dual 5A Compound Gate Driver
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FEATURES
DESCRIPTION
•
•
The SM72482 Dual Gate Driver replaces industry
standard gate drivers with improved peak output
current and efficiency. Each “compound” output driver
stage includes MOS and bipolar transistors operating
in parallel that together sink more than 5A peak from
capacitive
loads.
Combining
the
unique
characteristics of MOS and bipolar devices reduces
drive current variation with voltage and temperature.
Under-voltage lockout protection is also provided.
The drivers can be operated in parallel with inputs
and outputs connected to double the drive current
capability. This device is available in the SOIC
package.
1
2
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•
•
•
•
•
•
•
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Renewable Energy Grade
Independently Drives Two N-Channel
MOSFETs
Compound CMOS and Bipolar Outputs Reduce
Output Current Variation
5A Sink, 3A Source Current Capability
Two Channels Can be Connected in Parallel to
Double the Drive Current
Independent Inputs (TTL Compatible)
Fast Propagation Times (25 ns Typical)
Fast Rise and Fall Times (14 ns Rise, 12 ns
Fall With 2 nF Load)
Available in Dual Noninverting, Dual Inverting,
and Combination Configurations
Supply Rail Under-Voltage Lockout Protection
(UVLO)
SM72482 UVLO Configured to Drive PFET
Through OUT_A and NFET Through OUT_B
Pin Compatible With Industry Standard Gate
Drivers
Packages
– SOIC
– Thermally Enhanced VSSOP
Connection Diagram
NC
IN_A
VEE
IN_B
1
8
2
7
3
6
4
5
NC
OUT A
VCC
OUT_B
APPLICATIONS
•
•
•
Synchronous Rectifier Gate Drivers
Switch-mode Power Supply Gate Driver
Solenoid and Motor Drivers
Figure 1. 8-Lead SOIC or VSSOP
See D or DGN Package
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
SM72482
SNVS696C – JANUARY 2011 – REVISED APRIL 2013
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PIN DESCRIPTIONS
Pin
Name
Description
Application Information
1
NC
No Connect
2
IN_A
‘A’ side control input
TTL compatible thresholds.
3
VEE
Ground reference for both inputs and
outputs
Connect to power ground.
4
IN_B
‘B’ side control input
TTL compatible thresholds.
5
OUT_B
Output for the ‘B’ side driver.
Voltage swing of this output is from VCC to VEE. The output stage is
capable of sourcing 3A and sinking 5A.
6
VCC
Positive output supply
Locally decouple to VEE.
7
OUT_A.
Output for the ‘A’ side driver.
Voltage swing of this output is from VCC to VEE. The output stage is
capable of sourcing 3A and sinking 5A.
8
NC
No Connect
Table 1. Configuration Table
“A” Output Configuration
“B” Output Configuration
Package
SM72482MY-1
Part Number
Non-Inverting (Low in UVLO)
Non-Inverting (Low in UVLO)
VSSOP
SM72482MA-4
Inverting (High in UVLO)
Non-Inverting (Low in UVLO)
SOIC
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)
VCC to VEE
−0.3V to 15V
IN to VEE
−0.3V to 15V
−55°C to +150°C
Storage Temperature Range, (TSTG)
Maximum Junction Temperature,
(TJ(max))
+150°C
Operating Junction Temperature
+125°C
ESD Rating
(1)
2kV
Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which
operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.
Electrical Characteristics
TJ = −40°C to +125°C, VCC = 12V, VEE = 0V, No Load on OUT_A or OUT_B, unless otherwise specified.
Symbol
Parameter
Conditions
Min
VCC−VEE
3.5
VCCR
VCC Under Voltage Lockout (rising) VCC−VEE
2.3
VCCH
VCC Under Voltage Lockout
Hysteresis
ICC
VCC Supply Current (ICC)
VCC Operating Range
Typ
2.9
Max
Units
14
V
3.5
V
230
mV
IN_A = IN_B = 0V (SM72482MY-1)
1
2
IN_A = VCC, IN_B = 0V
(SM72482MA-4)
1
2
mA
CONTROL INPUTS
VIH
Logic High
VIL
Logic Low
0.8
V
VthH
High Threshold
1.3
1.75
2.2
V
VthL
Low Threshold
0.8
1.35
2.0
HYS
Input Hysteresis
2
2.2
V
400
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V
mV
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Electrical Characteristics (continued)
TJ = −40°C to +125°C, VCC = 12V, VEE = 0V, No Load on OUT_A or OUT_B, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
IIL
Input Current Low
IN_A=IN_B=VCC
−1
0.1
1
IIH
Input Current High
IN_A=IN_B=VCC(SM72482MY-1)
10
18
25
IN_B=VCC (SM72482MA-4)
10
18
25
IN_A=VCC (SM72482MA-4)
-1
0.1
1
Units
µA
OUTPUT DRIVERS
ROH
Output Resistance High
IOUT = −10 mA (1)
30
50
Ω
ROL
Output Resistance Low
IOUT = + 10 mA (1)
1.4
2.5
Ω
ISource
Peak Source Current
OUTA/OUTB = VCC/2,
200 ns Pulsed Current
3
A
ISink
Peak Sink Current
OUTA/OUTB = VCC/2,
200 ns Pulsed Current
5
A
SWITCHING CHARACTERISTICS
td1
Propagation Delay Time Low to
High, IN rising (IN to OUT)
CLOAD = 2 nF, see Figure 2 and
Figure 3
25
40
ns
td2
Propagation Delay Time High to
Low, IN falling (IN to OUT)
CLOAD = 2 nF, see Figure 2 and
Figure 3
25
40
ns
tr
Rise Time
CLOAD = 2 nF, see Figure 2 and
Figure 3
14
25
ns
tf
Fall Time
CLOAD = 2 nF, see Figure 2 and
Figure 3
12
25
ns
TJ = 150°C
500
Junction to Ambient,
0 LFPM Air Flow
SOIC Package
170
VSSOP Package
60
Junction to Case
SOIC Package
70
VSSOP Package
4.7
LATCHUP PROTECTION
AEC - Q100, Method 004
mA
THERMAL RESISTANCE
θJA
θJC
(1)
°C/W
°C/W
The output resistance specification applies to the MOS device only. The total output current capability is the sum of the MOS and
Bipolar devices.
TIMING WAVEFORMS
INPUT
INPUT
OUTPUT
50%
50%
50%
50%
tD1
tD2
tD1
tD2
90%
90%
OUTPUT
10%
10%
tf
tf
tr
tr
Figure 2. Inverting
Figure 3. Non-Inverting
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Typical Performance Characteristics
Supply Current vs Frequency
Supply Current vs Capacitive Load
1000
100
TA = 25°C
10
VCC = 12V
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
VCC = 15V
VCC = 10V
VCC = 5V
1
f = 500kHz
100
10
f = 100kHz
1
TA = 25°C
f = 10kHz
CL = 2200pF
0.1
100
0.1
1
10
100
1000
10k
1k
CAPACITIVE LOAD (pF)
FREQUENCY (kHz)
Figure 4.
Figure 5.
Rise and Fall Time vs Supply Voltage
Rise and Fall Time vs Temperature
20
20
TA = 25°C
VCC = 12V
CL = 2200pF
CL = 2200pF
18
18
16
16
TIME (ns)
TIME (ns)
tr
tr
14
14
tf
tf
12
12
10
10
5 6
4
7
8
9 10 11 12 13 14 15 16
-75 -50 -25 0
25 50 75 100 125 150 175
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
Figure 6.
Figure 7.
Rise and Fall Time vs Capacitive Load
Delay Time vs Supply Voltage
32.5
50
TA = 25°C
TA = 25°C
VCC = 12V
CL = 2200pF
30
40
tr
20
tD2
TIME (ns)
TIME (ns)
27.5
30
tf
25
22.5
tD1
10
20
17.5
0
100
1k
CAPACITIVE LOAD (pF)
10k
6
8
10
12
14
16
SUPPLY VOLTAGE (V)
Figure 8.
4
4
Figure 9.
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Typical Performance Characteristics (continued)
Delay Time vs Temperature
RDSON vs Supply Voltage
32.5
3.25
VCC = 12V
CL = 2200pF
IOUT = 10mA
2.75
tD2
ROH
ROL (:)
TIME (ns)
27.5
55
25
tD1
45
2.25
1.75
35
22.5
ROH (:)
30
65
TA = 25°C
ROL
1.25
20
17.5
25
15
0.75
-75 -50 -25 0
0
25 50 75 100 125 150 175
TEMPERATURE (°C)
3
6
9
12
15
18
SUPPLY VOLTAGE (V)
Figure 10.
Figure 11.
UVLO Thresholds and Hysteresis vs Temperature
0.450
VCCR
2.800
2.500
VCCF
0.390
0.330
2.200
0.270
VCCH
1.900
1.600
-75 -50 -25 0
HYSTERESIS (V)
UVLO THRESHOLDS (V)
3.100
0.210
0.150
25 50 75 100 125 150 175
TEMPERATURE (°C)
Figure 12.
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BLOCK DIAGRAM
VCC
UVLO
VEE
OUT_A
IN_A
VEE
VCC
IN_B
OUT_B
VEE
Figure 13. Block Diagram of SM72482
6
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SNVS696C – JANUARY 2011 – REVISED APRIL 2013
DETAILED OPERATING DESCRIPTION
The SM72482 dual gate driver consists of two independent and identical driver channels with TTL compatible
logic inputs and high current totem-pole outputs that source or sink current to drive MOSFET gates. The driver
output consist of a compound structure with MOS and bipolar transistor operating in parallel to optimize current
capability over a wide output voltage and operating temperature range. The bipolar device provides high peak
current at the critical threshold region of the MOSFET VGS while the MOS devices provide rail-to-rail output
swing. The totem pole output drives the MOSFET gate between the gate drive supply voltage VCC and the power
ground potential at the VEE pin.
The control inputs of the drivers are high impedance CMOS buffers with TTL compatible threshold voltages. The
SM72482 pinout was designed for compatibility with industry standard gate drivers in single supply gate driver
applications.
The input stage of each driver should be driven by a signal with a short rise and fall time. Slow rising and falling
input signals, although not harmful to the driver, may result in the output switching repeatedly at a high
frequency.
The two driver channels of the SM72482 are designed as identical cells. Transistor matching inherent to
integrated circuit manufacturing ensures that the AC and DC peformance of the channels are nearly identical.
Closely matched propagation delays allow the dual driver to be operated as a single with inputs and output pins
connected. The drive current capability in parallel operation is precisely 2X the drive of an individual channel.
Small differences in switching speed between the driver channels will produce a transient current (shoot-through)
in the output stage when two output pins are connected to drive a single load. Differences in input thresholds
between the driver channels will also produce a transient current (shoot-through) in the output stage. Fast
transition input signals are especially important while operating in a parallel configuration. The efficiency loss for
parallel operation has been characterized at various loads, supply voltages and operating frequencies. The
power dissipation in the SM72482 increases less than 1% relative to the dual driver configuration when operated
as a single driver with inputs/ outputs connected.
An Under Voltage Lock Out (UVLO) circuit is included in the SM72482, which senses the voltage difference
between VCC and the chip ground pin, VEE. When the VCC to VEE voltage difference falls below 2.8V both driver
channels are disabled. The UVLO hysteresis prevents chattering during brown-out conditions and the driver will
resume normal operation when the VCC to VEE differential voltage exceeds approximately 3.0V.
The SM72482MY –1 device hold both outputs in the low state in the under-voltage lockout (UVLO) condition. The
SM72482MA–4 has an active high output state of OUT_A during UVLO. When VCC is less than the UVLO
threshold voltage, OUT_A will be locked in the high state while OUT_B will be disabled in the low state. This
configuration allows the SM72482MY –4 to drive a PFET through OUT_A and an NFET through OUT_B with
both FETs safely turned off during UVLO.
Layout Considerations
Attention must be given to board layout when using SM72482. Some important considerations include:
1. A Low ESR/ESL capacitor must be connected close to the IC and between the VCC and VEE pins to support
high peak currents being drawn from VCC during turn-on of the MOSFET.
2. Proper grounding is crucial. The drivers need a very low impedance path for current return to ground
avoiding inductive loops. The two paths for returning current to ground are a) between SM72482 VEE pin and
the ground of the circuit that controls the driver inputs, b) between SM72482 VEE pin and the source of the
power MOSFET being driven. All these paths should be as short as possible to reduce inductance and be as
wide as possible to reduce resistance. All these ground paths should be kept distinctly separate to avoid
coupling between the high current output paths and the logic signals that drive the SM72482. A good method
is to dedicate one copper plane in a multi-layered PCB to provide a common ground surface.
3. With the rise and fall times in the range of 10 ns to 30 ns, care is required to minimize the lengths of current
carrying conductors to reduce their inductance and EMI from the high di/dt transients generated by the
SM72482.
4. The SM72482 footprint is compatible with other industry standard drivers including the TC4426/27/28 and
UCC27323/4/5.
5. If either channel is not being used, the respective input pin (IN_A or IN_B) should be connected to either VEE
or VCC to avoid spurious output signals.
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Thermal Performance
INTRODUCTION
The primary goal of thermal management is to maintain the integrated circuit (IC) junction temperature (TJ) below
a specified maximum operating temperature to ensure reliability. It is essential to estimate the maximum TJ of IC
components in worst case operating conditions. The junction temperature is estimated based on the power
dissipated in the IC and the junction to ambient thermal resistance θJA for the IC package in the application board
and environment. The θJA is not a given constant for the package and depends on the printed circuit board
design and the operating environment.
DRIVE POWER REQUIREMENT CALCULATIONS IN SM72482
The SM72482 dual low side MOSFET driver is capable of sourcing/sinking 3A/5A peak currents for short
intervals to drive a MOSFET without exceeding package power dissipation limits. High peak currents are
required to switch the MOSFET gate very quickly for operation at high frequencies.
VGATE
VHIGH
Q1
RG
VTRIG
CIN
Q2
The schematic above shows a conceptual diagram of the SM72482 output and MOSFET load. Q1 and Q2 are
the switches within the gate driver. RG is the gate resistance of the external MOSFET, and CIN is the equivalent
gate capacitance of the MOSFET. The gate resistance Rg is usually very small and losses in it can be neglected.
The equivalent gate capacitance is a difficult parameter to measure since it is the combination of CGS (gate to
source capacitance) and CGD (gate to drain capacitance). Both of these MOSFET capacitances are not constants
and vary with the gate and drain voltage. The better way of quantifying gate capacitance is the total gate charge
QG in coloumbs. QG combines the charge required by CGS and CGD for a given gate drive voltage VGATE.
Assuming negligible gate resistance, the total power dissipated in the MOSFET driver due to gate charge is
approximated by
PDRIVER = VGATE x QG x FSW
where
•
FSW = switching frequency of the MOSFET
(1)
For example, consider the MOSFET MTD6N15 whose gate charge specified as 30 nC for VGATE = 12V.
The power dissipation in the driver due to charging and discharging of MOSFET gate capacitances at switching
frequency of 300 kHz and VGATE of 12V is equal to
PDRIVER = 12V x 30 nC x 300 kHz = 0.108W.
(2)
If both channels of the SM72482 are operating at equal frequency with equivalent loads, the total losses will be
twice as this value which is 0.216W.
In addition to the above gate charge power dissipation, - transient power is dissipated in the driver during output
transitions. When either output of the SM72482 changes state, current will flow from VCC to VEE for a very brief
interval of time through the output totem-pole N and P channel MOSFETs. The final component of power
dissipation in the driver is the power associated with the quiescent bias current consumed by the driver input
stage and Under-voltage lockout sections.
8
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Characterization of the SM72482 provides accurate estimates of the transient and quiescent power dissipation
components. At 300 kHz switching frequency and 30 nC load used in the example, the transient power will be 8
mW. The 1 mA nominal quiescent current and 12V VGATE supply produce a 12 mW typical quiescent power.
Therefore the total power dissipation
PD = 0.216 + 0.008 + 0.012 = 0.236W.
(3)
We know that the junction temperature is given by
TJ = PD x θJA + TA
(4)
Or the rise in temperature is given by
TRISE = TJ − TA = PD x θJA
(5)
For SOIC package, θJA is estimated as 170°C/W for the conditions of natural convection. For VSSOP, θJA is
typically 60°C/W.
Therefore for SOIC TRISE is equal to
TRISE = 0.236 x 170 = 40.1°C
(6)
CONTINUOUS CURRENT RATING OF SM72482
The SM72482 can deliver pulsed source/sink currents of 3A and 5A to capacitive loads. In applications requiring
continuous load current (resistive or inductive loads), package power dissipation, limits the SM72482 current
capability far below the 5A sink/3A source capability. Rated continuous current can be estimated both when
sourcing current to or sinking current from the load. For example when sinking, the maximum sink current can be
calculated as:
ISINK (MAX) :=
TJ(MAX) - TA
TJA · RDS (ON)
where
•
RDS(on) is the on resistance of lower MOSFET in the output stage of SM72482
(7)
Consider TJ(max) of 125°C and θJA of 170°C/W for an SOIC package under the condition of natural convection
and no air flow. If the ambient temperature (TA) is 60°C, and the RDS(on) of the SM72482 output at TJ(max) is
2.5Ω, this equation yields ISINK(max) of 391mA which is much smaller than 5A peak pulsed currents.
Similarly, the maximum continuous source current can be calculated as
TJ(MAX) - TA
ISOURCE (MAX) :=
TJA · VDIODE
where
•
VDIODE is the voltage drop across hybrid output stage which varies over temperature and can be assumed to
be about 1.1V at TJ(max) of 125°C
(8)
Assuming the same parameters as above, this equation yields ISOURCE(max) of 347mA.
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REVISION HISTORY
Changes from Revision B (April 2013) to Revision C
•
10
Page
Changed layout of National Data Sheet to TI format ............................................................................................................ 9
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SM72482MA-4/NOPB
ACTIVE
SOIC
D
8
95
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
S482
SM72482MAE-4/NOPB
ACTIVE
SOIC
D
8
250
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
S482
SM72482MAX-4/NOPB
ACTIVE
SOIC
D
8
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-40 to 125
S482
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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