SN65C1167
SN75C1167, SN65C1168, SN75C1168
www.ti.com
SLLS159F – MARCH 1993 – REVISED NOVEMBER 2009
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
Check for Samples: SN65C1167 SN75C1167 SN65C1168 SN75C1168
FEATURES
1
•
•
•
•
•
•
•
•
•
•
•
Meet or Exceed Standards TIA/EIA-422-B and
ITU Recommendation V.11
BiCMOS Process Technology
Low Supply-Current Requirements: 9 mA Max
Low Pulse Skew
Receiver Input Impedance . . . 17 kΩ Typ
Receiver Input Sensitivity . . . ±200 mV
Receiver Common-Mode Input Voltage Range
of −7 V to 7 V
Operate From Single 5-V Power Supply
Glitch-Free Power-Up/Power-Down Protection
Receiver 3-State Outputs Active-Low Enable
for SN65C1167 and SN75C1167 Only
Improved Replacements for the MC34050 and
MC34051
SN65C1167 . . . DB OR NS PACKAGE
SN75C1167 . . . DB, N, OR NS PACKAGE
(TOP VIEW)
1B
1A
1R
RE
2R
2A
2B
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
1D
1Y
1Z
DE
2Z
2Y
2D
SN65C1168 . . . N, NS, OR PW PACKAGE
SN75C1168 . . . DB, N, NS, OR PW PACKAGE
(TOP VIEW)
1B
1A
1R
1DE
2R
2A
2B
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
1D
1Y
1Z
2DE
2Z
2Y
2D
DESCRIPTION
The SN65C1167, SN75C1167, SN65C1168, and SN75C1168 dual drivers and receivers are integrated circuits
designed for balanced transmission lines. The devices meet TIA/EIA-422-B and ITU recommendation V.11.
The SN65C1167 and SN75C1167 combine dual 3-state differential line drivers and 3-state differential line
receivers, both of which operate from a single 5-V power supply. The driver and receiver have active-high and
active-low enables, respectively, which can be connected together externally to function as direction control. The
SN65C1168 and SN75C1168 drivers have individual active-high enables.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1993–2009, Texas Instruments Incorporated
SN65C1167
SN75C1167, SN65C1168, SN75C1168
SLLS159F – MARCH 1993 – REVISED NOVEMBER 2009
www.ti.com
ORDERING INFORMATION
PACKAGE (1)
TA
PDIP – N
SOP – NS
(2)
Tube
Tape and reel
0°C to 70°C
SSOP – DB
TSSOP – PW
PDIP – N
–40°C to 85°C
2
TOP-SIDE MARKING
SN75C1167N
SN75C1167N
SN75C1168N
SN75C1168N
SN75C1167NSR
75C1167
SN75C1168NSR
75C1168
SN75C1167DBR
CA1167
SN75C1168DBR
CA1168
Tube
SN75C1168PW
Tape and reel
SN75C1168PWR
Tube
SN65C1168N
SN65C1168N
SN65C1167NSR
65C1167
CA1168
SOP – NS
Tape and reel
SN65C1168NSR
65C1168
SSOP – DB
Tape and reel
SN65C1167DBR
CB1167
Tube
SN65C1168PW
Tape and reel
SN65C1168PWR
TSSOP – PW
(1)
(2)
Tape and reel
ORDERABLE PART NUMBER
CB1168
Package drawings, thermal data, and symbolization are available at www.ti.com/sc/packaging.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
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Copyright © 1993–2009, Texas Instruments Incorporated
Product Folder Link(s): SN65C1167 SN75C1167 SN65C1168 SN75C1168
SN65C1167
SN75C1167, SN65C1168, SN75C1168
www.ti.com
SLLS159F – MARCH 1993 – REVISED NOVEMBER 2009
FUNCTION TABLES
ABC
Each Driver (1)
INPUT ENABLE
D
DE
OUTPUTS
Y
Z
H
H
H
L
L
H
L
H
X
L
Z
Z
(1)
H = high level, L = low level, X =
irrelevant, Z = high impedance
Each Receiver (1)
(1)
DIFFERENTIAL INPUTS
A−B
ENABLE
RE
OUTPUT
R
VID ≥ 0.2 V
L
H
−0.2 V < VID < 0.2 V
L
?
VID ≤ −0.2 V
L
L
X
H
Z
Open
L
H
H = high level, L = low level, ? = indeterminate, X = irrelevant,
Z = high impedance (off), Open = input disconnected or connected
driver off
LOGIC DIAGRAM (POSITIVE LOGIC)
SN65C1167/SN75C1167
SN65C1168, SN75C1168
12
4
DE
1DE
14
15
4
13
1D
RE
14
15
1D
13
2
3
1
1R
10
9
11
2D
6
5
7
2R
Copyright © 1993–2009, Texas Instruments Incorporated
2
1Y
1Z
1A
3
1
1R
12
2DE
10
9
11
2D
1B
2Y
6
5
7
2R
2Z
1Y
1Z
1A
1B
2Y
2Z
2A
2B
2A
2B
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3
SN65C1167
SN75C1167, SN65C1168, SN75C1168
SLLS159F – MARCH 1993 – REVISED NOVEMBER 2009
www.ti.com
SCHEMATIC OF INPUTS
EQUIVALENT OF DRIVER ENABLE INPUT
EQUIVALENT OF A OR B INPUT
VCC
VCC
17 kΩ
NOM
Input
1.7 kΩ
NOM
Input
288 kΩ
NOM
1.7 kΩ
NOM
VCC (A)
or
GND (B)
GND
GND
SCHEMATIC OF OUTPUTS
TYPICAL OF EACH DRIVER OUTPUT
TYPICAL OF EACH RECEIVER OUTPUT
VCC
VCC
Output
Output
GND
GND
4
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Copyright © 1993–2009, Texas Instruments Incorporated
Product Folder Link(s): SN65C1167 SN75C1167 SN65C1168 SN75C1168
SN65C1167
SN75C1167, SN65C1168, SN75C1168
www.ti.com
SLLS159F – MARCH 1993 – REVISED NOVEMBER 2009
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
–0.5
7
Driver
–0.5
VCC + 0.5
A or B, Receiver
–11
14
Receiver
–14
14
V
Driver
–0.5
7
V
VCC
Supply voltage range (2)
VI
Input voltage range
VID
Differential input voltage range (3)
VO
Output voltage range
IIK or IOK
Clamp current range
Driver
±20
Driver
±150
IO
Output current range
ICC
Supply current
Receiver
±25
GND current
TJ
θJA
Tstg
(1)
(2)
(3)
(4)
(5)
Operating virtual junction temperature
Package thermal impedance (4)
(5)
V
mA
mA
200
mA
mA
150
°C
82
N package
67
NS package
64
PW package
108
–65
V
−200
DB package
Storage temperature range
UNIT
150
°C/W
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages values except differential input voltage are with respect to the network GND.
Differential input voltage is measured at the noninverting terminal with respect to the inverting terminal.
Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS
VCC
Supply voltage
(1)
MIN
NOM
MAX
4.5
5
5.5
UNIT
V
VIC
Common-mode input voltage
Receiver
±7
V
VID
Differential input voltage
Receiver
±7
V
VIH
High-level input voltage
Except A, B
VIL
Low-level input voltage
Except A, B
IOH
High-level output current
IOL
Low-level output current
TA
Operating free-air temperature
(1)
2
V
0.8
−6
Receiver
−20
Driver
Receiver
6
Driver
20
SN75C1167, SN75C1168
0
70
SN65C1167, SN65C1168
–40
85
V
mA
mA
°C
Refer to TIA/EIA-422-B for exact conditions.
Copyright © 1993–2009, Texas Instruments Incorporated
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5
SN65C1167
SN75C1167, SN65C1168, SN75C1168
SLLS159F – MARCH 1993 – REVISED NOVEMBER 2009
www.ti.com
DRIVER SECTION
Electrical Characteristics (1)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VIK
TEST CONDITIONS
MIN
TYP (2)
II = −18 mA
Input clamp voltage
VOH
High-level output voltage
VIH = 2 V,
VIL = 0.8
V,
VOL
Low-level output voltage
VIH = 2 V,
VIL = 0.8
V,
|VOD1|
Differential output voltage
IOH = −20 mA
IOL = 20 mA
IO = 0 mA
Differential output voltage
∆|VOD|
Change in magnitude of differential
output voltage
UNIT
−1.5
V
3.4
V
0.2
2
(1)
|VOD2|
2.4
MAX
2
0.4
V
6
V
3.1
V
±0.4
V
±3
V
±0.4
V
RL = 100 Ω, See Figure 1
VOC
Common-mode output voltage
∆|VOC|
Change in magnitude of common-mode
output voltage
IO(OFF)
Output current with power off
IOZ
High-impedance-state output current
IIH
High-level input current
VI = VCC or VIH
1
IIL
Low-level input current
VI = GND or VIL
−1
µA
IOS
Short-circuit output current (3)
VO = VCC or GND,
−150
mA
ICC
Supply current (total package) (4)
No load,
Enabled
Ci
Input capacitance
(1)
(2)
(3)
(4)
VCC = 0 V
VO = 6 V
100
VO = −0.25 V
µA
−100
VO = 2.5 V
20
µA
−20
VO = 5 V
−30
VI = VCC or GND
4
6
VI = 2.4 or 0.5 V
5
3
µA
mA
6
pF
Refer to TIA/EIA-422-B for exact conditions.
All typical values are at VCC = 5 V, and TA = 25°C.
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
This parameter is measured per input, while the other inputs are at VCC or GND.
Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
tPHL
Propagation delay time, high- to low-level
output
tPLH
Propagation delay time, low- to high-level
output
tsk(p)
Pulse skew
tr
Rise time
tf
Fall time
tPZH
Output enable time to high level
tPZL
Output enable time to low level
tPHZ
Output disable time from low level
tPLZ
Output disable time from high level
(1)
6
TEST CONDITIONS
R1 = R2 = 50 Ω,
C1 = C2 = C3 = 40 pF,
See Figure 2
R3 = 500 Ω,
S1 is open,
MIN
TYP (1)
MAX
7
12
ns
7
12
ns
0.5
4
ns
UNIT
R1 = R2 = 50 Ω,
C1 = C2 = C3 = 40 pF,
SeeFigure 3
R3 = 500 Ω,
S1 is open,
5
10
ns
5
10
ns
R1 = R2 = 50 Ω,
C1 = C2 = C3 = 40 pF,
See Figure 4
R3 = 500 Ω,
S1 is closed,
10
19
ns
10
19
ns
R1 = R2 = 50 Ω,
C1 = C2 = C3 = 40 pF,
See Figure 4
R3 = 500 Ω,
S1 is closed,
7
16
ns
7
16
ns
All typical values are at VCC = 5 V, and TA = 25°C.
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Copyright © 1993–2009, Texas Instruments Incorporated
Product Folder Link(s): SN65C1167 SN75C1167 SN65C1168 SN75C1168
SN65C1167
SN75C1167, SN65C1168, SN75C1168
www.ti.com
SLLS159F – MARCH 1993 – REVISED NOVEMBER 2009
RECEIVER SECTION
Electrical Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage, differential
input
VIT–
Negative-going input threshold voltage, differential
input
Vhys
Input hysteresis (VIT+ – VIT–)
VIK
Input clamp voltage, RE
VOH
High-level output voltage
VID = 200 mV,
IOH = −6 mA
VOL
Low-level output voltage
VID = −200 mV,
IOL = 6 mA
IOZ
High-impedance-state output
current
II
Line input current
II
Enable input current, RE
ri
Input resistance
ICC
(1)
(2)
(3)
MIN
TYP (1)
MAX UNIT
0.2
−0.2 (2)
V
60
SN75C1167
SN75C1167
II = −18 mA
Other input at 0 V
SN75C1167
3.8
4.2
V
0.3
V
±0.5
±5
µA
VI = 10 V
1.5
VI = −10 V
−2.5
No load, Enabled
±1
Other input at 0 V
V
0.1
VI = VCC or GND
VIC = −7 V to 7 V,
Supply current (total package)
mV
−1.5
VO = VCC or GND
V
4
17
mA
µA
kΩ
VI = VCC or GND
4
6
VIH = 2.4 V or 0.5 V (3)
5
9
mA
All typical values are at VCC = 5 V and TA = 25°C.
The algebraic convention, where the less positive (more negative) limit is designated as minimum, is used in this data sheet for
common-mode input voltage and threshold voltage levels only.
Refer to TIA/EIA-422-B for exact conditions.
Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
(1)
TEST CONDITIONS
MIN
TYP (2)
MAX
9
17
27
ns
9
17
27
ns
4
9
ns
UNIT
tPLH
Propagation delay time, low- to high-level output
tPHL
Propagation delay time, high- to low-level output
tTLH
Transition time, low- to high-level output
tTHL
Transition time, high- to low-level output
4
9
ns
tPZH
Output enable time to high level
13
22
ns
tPZL
Output enable time to low level
13
22
ns
tPHZ
Output disable time from high level
13
22
ns
tPLZ
Output disable time from low level
13
22
ns
(1)
(2)
See Figure 5
VIC = 0 V, See Figure 5
RL = 1 kW, See Figure 6
Measured per input while the other inputs are at VCC or GND
All typical values are at VCC = 5 V and TA = 25°C.
Copyright © 1993–2009, Texas Instruments Incorporated
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SN65C1167
SN75C1167, SN65C1168, SN75C1168
SLLS159F – MARCH 1993 – REVISED NOVEMBER 2009
www.ti.com
PARAMETER MEASUREMENT INFORMATION
RL
2
VOD2
RL
2
VOC
Figure 1. Driver Test Circuit, VOD and VOC
A.
C1, C2, and C3 include probe and jig capacitance.
B.
The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, 50% duty cycle, tr = tf
≤ 6 ns.
3V
Input
(see Note B)
t PLH
Y
C2
Input
1.3 V
1.3 V
t PHL
VOH
R1
R3
50%
1.3 V
Y
1.5 V
C1
S1
C3
0V
t sk(p)
R2
50%
1.3 V
VOL
t sk(p)
VOH
Z
50%
1.3 V
Z
See Note A
t PHL
50%
1.3 V
VOL
t PLH
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 2. Driver Test Circuit and Voltage Waveforms
C.
C1, C2, and C3 include probe and jig capacitance.
D.
The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, 50% duty cycle, tr = tf
≤ 6 ns.
C2
Input
C1
R1
0V
R3
VOD
1.5 V
S1
C3
3V
Input
(see Note B)
R2
Differential
Output
90%
90%
10%
10%
tr
See Note A
TEST CIRCUIT
tf
VOLTAGE WAVEFORMS
Figure 3. Driver Test Circuit and Voltage Waveforms
8
E.
C1, C2, and C3 include probe and jig capacitance.
F.
The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, 50% duty cycle, tr = tf
≤ 6 ns.
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Product Folder Link(s): SN65C1167 SN75C1167 SN65C1168 SN75C1168
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SN75C1167, SN65C1168, SN75C1168
www.ti.com
SLLS159F – MARCH 1993 – REVISED NOVEMBER 2009
PARAMETER MEASUREMENT INFORMATION (continued)
3V
Input DE
1.3 V
C2
0V
or
3V
R1
R3
C1
S1
Pulse
Generator
DE
See Note B
50 Ω
0V
t PZL
1.5 V
Output
1.5 V
VOL + 0.3 V
R2
C3
1.5 V
t PLZ
0.8 V
VOL
t PHZ
t PZH
VOH
See Note A
VOL − 0.3 V
Output
2V
1.5 V
VOLTAGE WAVEFORMS
TEST CIRCUIT
Figure 4. Driver Test Circuit and Voltage Waveforms
G.
CL includes probe and jig capacitance.
H.
The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, 50% duty cycle, tr = tf
≤ 6 ns.
CC
S1
t TLH
Output
(see Note B)
A Input
RL
Device
Under
Test
B Input
t THL
10%
90%
50%
50%
90%
10%
t PLH
CL = 50 pF
(see Note A)
VOH
VOL
t PHL
2.5 V
0V
−2.5 V
B Input
A Input = 0 V
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 5. Receiver Test Circuit and Voltage Waveforms
I.
CL includes probe and jig capacitance.
J.
The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, 50% duty cycle, tr = tf
≤ 6 ns.
RE Input
VCC
1.3 V
1.3 V
0V
S1
t PLZ
0.5 V
t PZL
VCC
Output
RE Input
VID = −2.5 V
or 2.5 V
Device
Under
Test
50%
VOL
RL
t PHZ
t PZH
VOH
CL = 50 pF
(see Note A)
50%
Output
GND
0.5 V
t PZL , t PLZ Measurement: S1 to VCC
t PZH, t PHZ Measurement: S1 to GND
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 6. Receiver Test Circuit and Voltage Waveforms
Copyright © 1993–2009, Texas Instruments Incorporated
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9
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
SN65C1167NSR
ACTIVE
SO
NS
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
65C1167
Samples
SN65C1167NSRG4
ACTIVE
SO
NS
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
65C1167
Samples
SN65C1168N
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
-40 to 85
SN65C1168N
Samples
SN65C1168NSR
ACTIVE
SO
NS
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
65C1168
Samples
SN65C1168PW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CB1168
Samples
SN65C1168PWG4
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CB1168
Samples
SN65C1168PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CB1168
Samples
SN75C1167DB
ACTIVE
SSOP
DB
16
80
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
CA1167
Samples
SN75C1167DBR
ACTIVE
SSOP
DB
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
CA1167
Samples
SN75C1167N
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
SN75C1167N
Samples
SN75C1167NSR
ACTIVE
SO
NS
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
75C1167
Samples
SN75C1167NSRG4
ACTIVE
SO
NS
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
75C1167
Samples
SN75C1168DBR
ACTIVE
SSOP
DB
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
CA1168
Samples
SN75C1168N
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
SN75C1168N
Samples
SN75C1168NE4
ACTIVE
PDIP
N
16
25
RoHS & Green
NIPDAU
N / A for Pkg Type
0 to 70
SN75C1168N
Samples
SN75C1168NSR
ACTIVE
SO
NS
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
75C1168
Samples
SN75C1168NSRG4
ACTIVE
SO
NS
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
75C1168
Samples
SN75C1168PW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
CA1168
Samples
SN75C1168PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
CA1168
Samples
SN75C1168PWRG4
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
CA1168
Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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