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SN65C1167E, SN65C1168E
SLLS740B – MARCH 2007 – REVISED MAY 2017
SN65C116xE Dual Differential Drivers and Receivers
With ±15-kV ESD Protection
1 Features
3 Description
•
The SN65C1167E and SN65C1168E consist of dual
drivers and dual receivers with ±15-kV ESD (Human
Body Model [HBM]) and ±8-kV ESD (IEC61000-4-2
Air-Gap Discharge and Contact Discharge) for RS422 bus pins. The devices meet the requirements of
TIA/EIA-422-B and ITU recommendation V.11.
1
•
•
•
•
•
•
•
•
•
Meet or Exceed Standards TIA/EIA-422-B and
ITU Recommendation V.11
Operate From Single 5-V Power Supply
ESD Protection for RS-422 Bus Pins
– ±15-kV Human-Body Model (HBM)
– ±8-kV IEC 61000-4-2, Contact Discharge
– ±8-kV IEC 61000-4-2, Air-Gap Discharge
Low Supply-Current Requirements: 9 mA
Maximum
Low Pulse Skew
Receiver Input Impedance . . . 17 kΩ (Typical)
Receiver Input Sensitivity . . . ±200 mV
Receiver Common-Mode Input Voltage Range of
–7 V to +7 V
Glitch-Free Power-Up/Power-Down Protection
Receiver 3-State Outputs Active-Low Enable
(SN65C1167E Only)
2 Applications
•
•
•
The SN65C1167E combines dual 3-state differential
line drivers and 3-state differential line receivers, both
of which operate from a single 5-V power supply. The
driver and receiver have active-high and active-low
enables, respectively, which can be connected
together externally to function as direction control.
SN65C1168E drivers have individual active-high
enables.
Device Information(1)
PART NUMBER
SN65C116xE
PACKAGE
BODY SIZE (NOM)
SO (16)
10.30 mm × 5.30 mm
TSSOP (16)
5.00 mm × 4.40 mm
VQFN (16)
4.00 mm × 3.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
AC and Servo Motor Drives
Factory Automation and Control
Wireless Infrastructure
Block Diagram
SN65C1167E
DE
RE
SN65C1168E
12
1DE
1D
4
14
1D
15
13
2
1R
3
1
10
2D
9
11
6
2R
5
7
1Y
1Z
1A
1R
2DE
2D
4
15
13
3
2Z
2R
2
1
12
9
10
11
1B
2Y
14
5
6
7
1Y
1Z
1A
1B
2Y
2Z
2A
2B
2A
2B
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN65C1167E, SN65C1168E
SLLS740B – MARCH 2007 – REVISED MAY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
5
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
5
5
6
6
7
7
8
8
Absolute Maximum Ratings ......................................
Driver Output and Receiver Input ESD Ratings........
Recommended Operating Conditions.......................
Thermal Information ..................................................
Driver Section Electrical Characteristics ...................
Receiver Section Electrical Characteristics ..............
Driver Section Switching Characteristics ..................
Receiver Section Switching Characteristics..............
Parameter Measurement Information .................. 9
Detailed Description ............................................ 12
8.1 Overview ................................................................. 12
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 13
9
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Application ................................................. 15
10 Power Supply Recommendations ..................... 15
11 Device and Documentation Support ................. 16
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support ....................................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
16
16
16
16
16
16
16
12 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (April 2007) to Revision B
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section ...................................................................................................................... 1
•
Changed the Rise Time Max value From: 10 ns To: 8 ns in the Driver Section Switching Characteristics table.................. 8
•
Changed the Fall Time Max value From: 10 ns To: 8 ns in the Driver Section Switching Characteristics table ................... 8
•
Added Maximum switching frequency to the Driver Section Switching Characteristics table ................................................ 8
2
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SLLS740B – MARCH 2007 – REVISED MAY 2017
5 Pin Configuration and Functions
NS or PW Package
16 Pin (NS or TSSOP)
Top View
1
16
VCC
1A
2
1A
2
15
ID
1R
3
1R
3
14
1Y
RE
4
16
1B
1
1B
VCC
RGY Package
16 Pin (VQFN)
Top View
Thermal
Pad
15
1D
14
1Y
13
1Z
12
DE
13
1Z
2R
5
2R
5
12
DE
2A
6
11
2Z
2A
6
11
2Z
2B
7
10
2Y
2B
7
10
2Y
GND
8
9
2D
GND
2D
9
4
8
RE
Pin Functions, SN65C1167E
PIN
NAME
I/O
DESCRIPTION
SO
TSSOP
VQFN
1A
2
2
2
I
RS422 differential input (noninverting) to receiver 1
2A
6
6
6
I
RS422 differential input (noninverting) to receiver 2
1B
1
1
1
I
RS422 differential input (inverting) to receiver 1
2B
7
7
7
I
RS422 differential input (inverting) to receiver 2
1D
15
15
15
I
Logic data input to RS422 driver 1
2D
9
9
9
I
Logic data input to RS422 driver 2
DE
12
12
12
I
Driver enable (active high)
GND
8
8
8
—
Device ground pin
1R
3
3
3
O
Logic data output of RS422 receiver 1
2R
5
5
5
O
Logic data output of RS422 receiver 2
RE
4
4
4
I
Receiver enable pin (active low)
VCC
16
16
16
—
Power supply
1Y
14
14
14
O
RS-422 differential (noninverting) driver output 1
2Y
10
10
10
O
RS-422 differential (noninverting) driver output 1
1Z
13
13
13
O
RS-422 differential (inverting) driver output 1
2Z
11
11
11
O
RS-422 differential (inverting) driver output 2
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SLLS740B – MARCH 2007 – REVISED MAY 2017
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NS or PW Package
16 Pin (NS or TSSOP)
Top View
2
15
ID
1R
3
14
1Y
1DE
4
13
1Z
2R
5
12
2DE
2A
6
11
2Z
2B
7
10
2Y
GND
8
9
2D
1A
2
1R
3
1DE
4
16
1A
Thermal
Pad
15
1D
14
1Y
13
1Z
12
2DE
2R
5
2A
6
11
2Z
2B
7
10
2Y
9
VCC
2D
16
8
1
GND
1B
1
1B
VCC
RGY Package
16 Pin (VQFN)
Top View
Pin Functions, SN65C1168E
PIN
NAME
I/O
DESCRIPTION
SO
TSSOP
VQFN
1A
2
2
2
I
RS422 differential input (noninverting) to receiver 1
2A
6
6
6
I
RS422 differential input (noninverting) to receiver 1
1B
1
1
1
I
RS422 differential input (inverting) to receiver 1
2B
7
7
7
I
RS422 differential input (inverting) to receiver 2
1D
15
15
15
I
Logic data input to RS422 driver 1
2D
9
9
9
I
Logic data input to RS422 driver 2
1DE
4
4
4
I
Driver 1 enable (active high)
2DE
12
12
12
I
Driver 2 enable (active high)
GND
8
8
8
—
Device ground
1R
3
3
3
O
Logic data output of RS422 receiver 1
2R
5
5
5
O
Logic data output of RS422 receiver 2
VCC
16
16
16
—
Power supply
1Y
14
14
14
O
RS-422 differential (noninverting) driver output 1
2Y
10
10
10
O
RS-422 differential (noninverting) driver output 2
1Z
13
13
13
O
RS-422 differential (noninverting) driver output 1
2Z
11
11
11
O
RS-422 differential (noninverting) driver output 2
4
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SLLS740B – MARCH 2007 – REVISED MAY 2017
6 Specifications
6.1 Absolute Maximum Ratings
over recommended operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage (2)
VI
Input voltage
VID
Differential input voltage (3)
VO
Output voltage
IIK
Input clamp current
IOK
Output clamp current
IO
Output current
ICC
Supply current
(1)
MIN
MAX
–0.5
7
Driver, DE, RE
–0.5
7
A or B, Receiver
–14
14
Receiver
–14
14
Driver
–0.5
7
Receiver
–0.5
VCC + 0.5
Driver, VI < 0
–20
Driver, VO < 0
–20
Receiver
±20
Driver
θJA
Package thermal impedance (4)
(5)
V
V
V
mA
mA
mA
±25
GND current
Operating virtual junction temperature
V
±150
Receiver
TJ
UNIT
200
mA
–200
mA
150
°C
NS package
64
PW package
108
RGY package
39
°C/W
TA
Operating free-air temperature
–40
85
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
(3)
(4)
(5)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values except differential input voltage are with respect to the network GND.
Differential input voltage is measured at the noninverting terminal, with respect to the inverting terminal.
Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/θJA. Selecting the maximum of 150°C can affect reliability.
The package thermal impedance is calculated in accordance with JESD 51-7.
6.2 Driver Output and Receiver Input ESD Ratings
VALUE UNIT
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±15000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
IEC 61000-4-2, air-gap discharge
±8000
IEC 61000-4-2, contact discharge
±8000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2007–2017, Texas Instruments Incorporated
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6.3 Recommended Operating Conditions
MIN
NOM
MAX
4.5
5
5.5
V
Receiver
±7
V
Differential input voltage
Receiver
±7
V
VI
Input voltage
Except A, B
0
5.5
V
VO
Output voltage
Receiver
0
VCC
V
VIH
High-level input voltage
Except A, B
2
VIL
Low-level input voltage
Except A, B
0.8
Receiver
–6
VCC
Supply voltage
VIC
Common-mode input voltage (1)
VID
IOH
High-level output current
IOL
Low-level output current
TA
Operating free-air temperature
(1)
UNIT
V
Driver
–20
Receiver
6
Driver
20
–40
85
V
mA
mA
°C
Refer to TIA/EIA-422-B for exact conditions.
6.4 Thermal Information
SN65C116xE
THERMAL METRIC
(1)
SO (NS)
PW (TSSOP)
RGY (VQFN)
16 PINS
16 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
74.9
98.9
42.8
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
33.7
32.9
35.3
°C/W
RθJB
Junction-to-board thermal resistance
37.1
44.6
18.5
°C/W
ψJT
Junction-to-top characterization parameter
6.1
1.9
0.5
°C/W
ψJB
Junction-to-board characterization parameter
36.6
44.1
18.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
3.3
°C/W
(1)
6
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SLLS740B – MARCH 2007 – REVISED MAY 2017
6.5 Driver Section Electrical Characteristics
over recommended supply voltage and operating free-air temperature ranges (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIK
Input clamp voltage
II = –18 mA
VOH
High-level output voltage
VIH = 2 V,
VIL = 0.8 V,
IOH = –20 mA
VOL
Low-level output voltage
VIH = 2 V,
VIL = 0.8 V,
IOL = 20 mA
|VOD1|
Differential output voltage 1
IO = 0 mA
MIN
TYP (1)
2.4
3.5
MAX
UNIT
–1.5
V
V
0.2
2
0.4
V
6
V
|VOD2|
Differential output voltage 2
RL = 100 Ω, See Figure 1
(2)
Δ|VOD|
Change in magnitude of
differential output voltage
RL = 100 Ω, See Figure 1
(2)
±0.4
V
VOC
Common-mode output voltage
RL = 100 Ω, See Figure 1
(2)
±3
V
Δ|VOC|
Change in magnitude of
common-mode output voltage
RL = 100 Ω, See Figure 1
(2)
±0.4
V
IO(OFF)
Output current with power off
VCC = 0 V
IOZ
High-impedance-state output current
IIH
High-level input current
VI = VCC or VIH
1
IIL
Low-level input current
VI = GND or VIL
–1
μA
IOS
Short-circuit output current
VO = VCC or GND (3)
–150
mA
ICC
Supply current (total package)
No load,
Enabled
Ci
Input capacitance
(1)
(2)
(3)
(4)
2
3.7
V
VO = 6 V
100
VO = –0.25 V
100
VO = 2.5 V
20
VO = 5 V
–20
–30
VI = VCC or GND
4
6
VI = 2.4 or 0.5 V (4)
5
9
6
μA
μA
μA
mA
pF
All typical values are at VCC = 5 V and TA = 25°C.
Refer to TIA/EIA-422-B for exact conditions.
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
This parameter is measured per input, while the other inputs are at VCC or GND.
6.6 Receiver Section Electrical Characteristics
over recommended ranges of common-mode input voltage, supply voltage, and operating free-air temperature
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage,
differential input
VIT–
Negative-going input threshold voltage,
differential input
Vhys
Input hysteresis (VIT+ – VIT–)
VIK
Input clamp voltage, RE
VOH
High-level output voltage
VID = 200 mV,
IOH = –6 mA
VOL
Low-level output voltage
VID = –200 mV,
IOL = 6 mA
IOZ
High-impedance state
output current
II
Line input current
II
Enable input current, RE
rI
Input resistance
VIC = –7 V to 7 V, Other input at 0 V
ICC
Supply current (total package)
No load,
Enabled
(1)
(2)
(3)
MIN
TYP (1)
MAX
0.2
–0.2 (2)
60
Other input at 0 V
mV
–1.5
SN65C1167E VO = VCC or GND
4.2
V
V
0.1
0.3
V
±0.5
±5
μA
VI = 10 V
1.5
VI = –10 V
–2.5
SN65C1167E VI = VCC or GND
±1
4
V
V
SN65C1167E II = –18 mA
3.8
UNIT
17
mA
μA
kΩ
VI = VCC or GND
4
6
VIH = 2.4 V or 0.5 V (3)
5
9
mA
All typical values are at VCC = 5 V and TA = 25°C.
The algebraic convention, where the less positive (more negative) limit is designated as minimum, is used in this data sheet for
common-mode input voltage and threshold voltage levels only.
Refer to TIA/EIA-422-B for exact conditions.
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6.7 Driver Section Switching Characteristics
over recommended supply voltage and operating free-air temperature ranges (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPHL
Propagation delay time, high- to low-level output
tPLH
Propagation delay time, low- to high-level output
tsk(p)
Pulse skew
tr
Rise time
tf
Fall time
tPZH
Output-enable time to high level
tPZL
Output-enable time to low level
tPHZ
Output-disable time from high level
tPLZ
Output-disable time from low level
fSW
Maximum switching frequency
(1)
R1 = R2 = 50 Ω,
C1 = C2 = C3 = 40 pF,
See Figure 2
MIN
R3 = 500 Ω,
S1 is open,
abc
R1 = R2 = 50 Ω,
C1 = C2 = C3 = 40 pF,
See Figure 3
R3 = 500 Ω,
S1 is open,
R1 = R2 = 50 Ω,
C1 = C2 = C3 = 40 pF,
See Figure 4
R3 = 500 Ω,
S1 is closed,
R1 = R2 = 50 Ω,
C1 = C2 = C3 = 40 pF,
See Figure 4
R3 = 500 Ω,
S1 is closed,
R1 = R2 = 50 Ω,
C1 = C2 = C3 = 40 pF,
See Figure 3
R3 = 500 Ω,
S1 is open,
TYP (1)
MAX
8
16
ns
8
16
ns
1.5
4
ns
5
8
ns
5
8
ns
10
19
ns
10
19
ns
7
16
ns
7
16
ns
UNIT
20
MHz
All typical values are at VCC = 5 V and TA = 25°C.
6.8 Receiver Section Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
MIN TYP (2)
MAX
UNIT
tPLH
Propagation delay time, low- to high-level output
See Figure 5
9
15
27
ns
tPHL
Propagation delay time, high- to low-level output
See Figure 5
9
15
27
ns
tTLH
Transition time, low- to high-level output
4
9
ns
tTHL
Transition time, high- to low-level output
4
9
ns
tPZH
Output-enable time to high level
7
22
ns
tPZL
Output-enable time to low level
7
22
ns
tPHZ
Output-disable time from high level
12
22
ns
tPLZ
Output-disable time from low level
12
22
ns
(1)
(2)
8
VIC = 0 V,
SN65C1167E
RL = 1 kΩ,
CL= 50 pF
See Figure 5
See Figure 6
Measured per input while the other inputs are at VCC or GND
All typical values are at VCC = 5 V and TA = 25°C.
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7 Parameter Measurement Information
RL
2
VOD2
RL
2
VOC
Figure 1. Driver Test Circuit, VOD and VOC
3V
Input
(see Note B)
Input
0V
t PHL
VOH
R1
R3
50%
1.3 V
Y
1.5 V
C1
S1
C3
1.3 V
t PLH
Y
C2
1.3 V
t sk(p)
R2
50%
1.3 V
VOL
t sk(p)
VOH
Z
50%
1.3 V
Z
See Note A
t PHL
TEST CIRCUIT
50%
1.3 V
VOL
t PLH
VOLTAGE WAVEFORMS
A.
C1, C2, and C3 include probe and jig capacitance.
B.
The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, tr = tf
≤ 6 ns.
Figure 2. Driver Test Circuit and Voltage Waveforms
C2
Input
R1
0V
R3
VOD
1.5 V
C1
S1
R2
C3
3V
Input
(see Note B)
Y
Differential
Output
90%
90%
10%
10%
Z
tr
See Note A
tf
VOLTAGE WAVEFORMS
TEST CIRCUIT
A.
C1, C2, and C3 include probe and jig capacitance.
B.
The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, tr = tf
≤ 6 ns.
Figure 3. Driver Test Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
3V
Input DE
Y
C2
0V
or
3V
1.3 V
R1
R3
C1
S1
C3
Pulse
Generator
0V
t PZL
1.5 V
Output
1.5 V
VOL + 0.3 V
0.8 V
R2
VOL
t PHZ
Z
DE
See Note A
50Ω
1.3 V
t PLZ
t PZH
VOH
VOH - 0.3 V
Output
2V
1.5 V
See Note B
TEST CIRCUIT
VOLTAGE WAVEFORMS
A.
C1, C2, and C3 include probe and jig capacitance.
B.
The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, tr = tf
≤ 6 ns.
Figure 4. Driver Test Circuit and Voltage Waveforms
VCC
S1
2.5 V
0V
-2.5 V
B Input
A Input = 0 V
(see Note B)
t PLH
t PHL
RL
A Input
Device
Under
Test
B Input
Output
CL = 50 pF
(see Note A)
TEST CIRCUIT
10%
90%
50%
90%
50%
t TLH
VOH
10%
VOL
t THL
VOLTAGE WAVEFORMS
A.
C1, C2, and C3 include probe and jig capacitance.
B.
The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, tr = tf
≤ 6 ns.
Figure 5. Receiver Test Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
3V
RE Input
(see Note B)
VCC
S1
1.3 V
1.3 V
0V
t PLZ
t PZL
VCC
Output
VOL + 0.5 V
RE Input
VID = -2.5 V
or 2.5 V
RL
Device
Under
Test
t PHZ
50%
VOL
t PZH
VOH
CL = 50 pF
(see Note A)
Output
VOH – 0.5 V
50%
GND
t PZL, t PLZ Measurement: S1 to V CC
t PZH, t PHZ Measurement: S1 to GND
VOLTAGE WAVEFORMS
TEST CIRCUIT
A.
C1, C2, and C3 include probe and jig capacitance.
B.
The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, duty cycle = 50%, tr = tf
≤ 6 ns.
Figure 6. Receiver Test Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SN65C1167E and SN65C1168E consist of dual drivers and dual receivers powered from a single 5-V
supply. These devices meet the requirements of TIA/EIA-422-B and ITU recommendation V.11.
8.2 Functional Block Diagram
SN65C1167E
DE
RE
SN65C1168E
12
1DE
1D
4
14
1D
15
13
2
1R
3
1
10
2D
9
11
6
2R
5
7
1Y
1Z
1A
1R
2DE
2D
4
14
15
13
2
3
1
12
10
9
11
1B
2Y
2R
6
5
7
2Z
1Y
1Z
1A
1B
2Y
2Z
2A
2B
2A
2B
Copyright © 2017, Texas Instruments Incorporated
8.3 Feature Description
8.3.1 Active High Driver Output Enables
Both drivers of SN65C1167E can be configured with the single DE logic input. Both drivers are set at highimpedance when disabled.
SN65C1168E drivers can be configured individually by 1DE and 2DE logic inputs. Both drivers are set at highimpedance when disabled.
8.3.2 Active Low Receiver Enables
Both SN65C1167E receivers can be configured with the single RE logic input. Receiver logic outputs are set at
high-impedance when disabled.
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8.4 Device Functional Modes
Table 1 and Table 2 list the functional modes of SN65C1167E and SN65C1168E.
Table 1. Each Driver
OUTPUTS
INPUT
D
ENABLE
DE
Y
Z
H
H
H
L
L
H
L
H
X
L
Z
Z
Table 2. SN65C1167E, Each Receiver (1)
(1)
DIFFERENTIAL INPUTS
A–B
ENABLE
RE
OUTPUT
R
VID ≥ 0.2 V
L
H
–0.2 V < VID < 0.2 V
L
?
VID ≤ –0.2 V
L
L
X
H
Z
Open
L
H
H = High level, L = Low level, ? = Indeterminate, X = Irrelevant,
Z = High impedance (off)
Table 3. SN65C1168E, Each Receiver (1)
(1)
DIFFERENTIAL INPUTS
A–B
OUTPUT
R
VID ≥ 0.2 V
H
–0.2 V < VID < 0.2 V
?
VID ≤ –0.2 V
L
Open
H
H = High level, L = Low level, ? = Indeterminate
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Figure 7 shows a typical RS-422 application. One transmitter is able to broadcast to multiple receiving nodes
connected together over a shared differential bus. Twisted-pair cabling with a controlled differential impedance is
used, and a termination resistance is placed at the farthest receive end of the cable in order to match the
transmission line impedance and minimize signal reflections.
EQUIVALENT OF DRIVER ENABLE INPUT
VCC
EQUIVALENT OF A OR B INPUT
VCC
17 kΩ
NOM
Input
1.7 kΩ
NOM
Input
288 kΩ
NOM
1.7 kΩ
NOM
VCC (A)
or
GND (B)
GND
GND
Figure 7. Schematic of Inputs
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Application Information (continued)
TYPICAL OF EACH DRIVER OUTPUT
TYPICAL OF EACH RECEIVER OUTPUT
VCC
VCC
Output
Output
GND
GND
Figure 8. Schematic of Outputs
9.2 Typical Application
Figure 9. Typical RS-422 Application
9.2.1 Design Requirements
A
•
•
•
typical RS-422 implementation using SN65C116xE requires the following:
5 V power source.
Connector that ensures the correct polarity for port pins.
Cabling that supports the desired operating rate and transmission distance.
9.2.2 Detailed Design Procedure
Place the device close to bus connector to keep traces (stub) short to prevent adding reflections to the bus line.
If desired, add external fail-safe biasing to ensure ±200 mV on the A-B port when the driver circuit is disabled.
10 Power Supply Recommendations
Use a 5 V power supply for VCC place 0.1-μF bypass capacitors close to the power supply pins to reduce errors
coupling in from noisy or high impedance power supplies.
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 4. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN65C1167E
Click here
Click here
Click here
Click here
Click here
SN65C1168E
Click here
Click here
Click here
Click here
Click here
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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13-Aug-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN65C1167ENS
ACTIVE
SO
NS
16
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
65C1167E
SN65C1167ENSR
ACTIVE
SO
NS
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
65C1167E
SN65C1167EPW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CB1167E
SN65C1167EPWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CB1167E
SN65C1167ERGYR
ACTIVE
VQFN
RGY
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CB1167
SN65C1168ENS
ACTIVE
SO
NS
16
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
65C1168E
SN65C1168ENSG4
ACTIVE
SO
NS
16
50
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
65C1168E
SN65C1168ENSR
ACTIVE
SO
NS
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
65C1168E
SN65C1168EPW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CB1168E
SN65C1168EPWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CB1168E
SN65C1168EPWRG4
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CB1168E
SN65C1168ERGYR
ACTIVE
VQFN
RGY
16
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CB1168
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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