SN65LVDM051PW

SN65LVDM179, SN65LVDM180 SN65LVDM050, SN65LVDM051 www.ti.com .................................................................................................................................................... SLLS324J – DECEMBER 1998 – REVISED JULY 2009 HIGH-SPEED DIFFERENTIAL LINE DRIVERS AND RECEIVERS FEATURES 1 • • • • • • • • • • • Low-Voltage Differential 50-Ω Line Drivers and Receivers Typical Full-Duplex Signaling Rates of 100 Mbps (See Table 1) Bus-Terminal ESD Exceeds 12 kV Operates From a Single 3.3-V Supply Low-Voltage Differential Signaling With Typical Output Voltages of 340 mV With a 50-Ω Load Valid Output With as Little as 50-mV Input Voltage Difference Propagation Delay Times – Driver: 1.7 ns Typical – Receiver: 3.7 ns Typical Power Dissipation at 200 MHz – Driver: 50 mW Typical – Receiver: 60 mW Typical LVTTL Input Levels Are 5-V Tolerant Driver Is High Impedance When Disabled or With VCC < 1.5 V Receiver Has Open-Circuit Failsafe DESCRIPTION The SN65LVDM179, SN65LVDM180, SN65LVDM050, and SN65LVDM051 are differential line drivers and receivers that use low-voltage differential signaling (LVDS) to achieve high signaling rates. These circuits are similar to TIA/EIA-644 standard compliant devices (SN65LVDS) counterparts, except that the output current of the drivers is doubled. This modification provides a minimum differential output voltage magnitude of 247 mV across a 50-Ω load simulating two transmission lines in parallel. This allows having data buses with more than one driver or with two line termination resistors. The receivers detect a voltage difference of 50 mV with up to 1 V of ground potential difference between a transmitter and receiver. The intended application of these devices and signaling techniques is point-to-point half duplex, baseband data transmission over a controlled impedance media of approximately 100 Ω characteristic impedance. SN65LVDM179D (Marked as DM179 or LVM179) SN65LVDM179DGK (Marked as M79) (TOP VIEW) VCC R D GND 1 8 2 7 3 6 4 5 A B Z Y 5 3 D 6 8 2 7 R Y Z A B SN65LVDM180D (Marked as LVDM180) SN65LVDM180PW (Marked as LVDM180) (TOP VIEW) NC R RE DE D GND GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC VCC A B Z Y NC 9 5 D 10 4 DE 12 2 11 R 14 15 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 1D 1Y 1Z DE 2Z 2Y 2D 13 1D 12 DE 10 9 11 2D 3 1R 2 1 4 RE 6 5 2R 7 SN65LVDM051D (Marked as LVDM051) SN65LVDM051PW (Marked as LVDM051) (TOP VIEW) 15 1B 1A 1R 1DE 2R 2A 2B GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 1D 1Y 1Z 2DE 2Z 2Y 2D Z 3 RE SN65LVDM050D (Marked as LVDM050) SN65LVDM050PW (Marked as LVDM050) (TOP VIEW) 1B 1A 1R RE 2R 2A 2B GND Y 1D 14 13 4 1DE 2 3 1R 9 2D 1 10 11 12 2DE 6 5 2R 7 A B 1Y 1Z 2Y 2Z 1A 1B 2A 2B 1Y 1Z 1A 1B 2Y 2Z 2A 2B 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1998–2009, Texas Instruments Incorporated SN65LVDM179, SN65LVDM180 SN65LVDM050, SN65LVDM051 SLLS324J – DECEMBER 1998 – REVISED JULY 2009 .................................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application-specific characteristics. The SN65LVDM179, SN65LVDM180, SN65LVDM050, and SN65LVDM051 are characterized for operation from –40°C to 85°C. Table 1. Maximum Recommended Operating Speeds Part Number All Buffers Active Rx Buffer Only Tx Buffer Only SN65LVDM179 150 Mbps 150 Mbps 500 Mbps SN65LVDM180 150 Mbps 150 Mbps 500 Mbps SN65LVDM050 100 Mbps 100 Mbps 400 Mbps SN65LVDM051 100 Mbps 100 Mbps 400 Mbps AVAILABLE OPTIONS PACKAGE TA –40°C to 85°C SMALL OUTLINE (D) SMALL OUTLINE (DGK) SMALL OUTLINE (PW) SN65LVDM050D — SN65LVDM050PW SN65LVDM051D — SN65LVDM051PW SN65LVDM179D SN65LVDM179DGK — SN65LVDM180D — SN65LVDM180PW FUNCTION TABLES SN65LVDM179 RECEIVER (1) INPUTS OUTPUT (1) VID = VA – VB R VID ≥ 50 mV H 50 MV < VID < 50 mV ? VID ≤ –50 mV L Open H H = high level, L = low level, ? = indeterminate SN65LVDM179 DRIVER INPUT (1) 2 (1) OUTPUTS (1) D Y Z L L H H H L Open L H H = high level, L = low level Submit Documentation Feedback Copyright © 1998–2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVDM179 SN65LVDM180 SN65LVDM050 SN65LVDM051 SN65LVDM179, SN65LVDM180 SN65LVDM050, SN65LVDM051 www.ti.com .................................................................................................................................................... SLLS324J – DECEMBER 1998 – REVISED JULY 2009 SN65LVDM180, SN65LVDM050, and SN65LVDM051 RECEIVER INPUTS (1) (1) OUTPUT (1) VID = VA – VB RE R VID ≥ 50 mV L H 50 MV < VID < 50 mV L ? VID ≤ –50 mV L L Open L H X H Z H = high level, L = low level, Z = high impedance, X = don't care SN65LVDM180, SN65LVDM050, and SN65LVDM051 DRIVER INPUTS (1) (1) OUTPUTS (1) D DE Y Z H L H L H H H L Open H L H X L Z Z H = high level, L = low level, Z = high impedance, X = don't care EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS VCC VCC VCC 300 kΩ 50 Ω 5Ω 10 kΩ D or RE Input Y or Z Output 50 Ω DE Input 7V 7V 7V 300 kΩ VCC VCC 300 kΩ 300 kΩ 5Ω A Input R Output B Input 7V 7V Copyright © 1998–2009, Texas Instruments Incorporated 7V Submit Documentation Feedback Product Folder Link(s): SN65LVDM179 SN65LVDM180 SN65LVDM050 SN65LVDM051 3 SN65LVDM179, SN65LVDM180 SN65LVDM050, SN65LVDM051 SLLS324J – DECEMBER 1998 – REVISED JULY 2009 .................................................................................................................................................... www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT Supply voltage range (2) VCC –0.5 V to 4 V D, R, DE, RE Voltage range –0.5 V to 6 V Y, Z, A, and B Electrostatic discharge –0.5 V to 4 V Y, Z, A, B , and GND (3) CLass 3, A:12 kV, B:600 V All Class 3, A:7 kV, B:500 V Continuous power dissipation See Dissipation Rating Table Storage temperature range (1) (2) (3) –65°C to 150°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. Tested in accordance with MIL-STD-883C Method 3015.7. DISSIPATION RATING TABLE (1) PACKAGE TA≤ 25°C POWER RATING DERATING FACTOR ABOVE TA = 25°C (1) TA = 85°C POWER RATING D(8) 635 mW 5.1 mW/°C 330 mW D(14) 987 mW 7.9 mW/°C 513 mW D(16) 1110 mW 8.9 mW/°C 577 mW DGK 424 mW 3.4 mW/°C 220 mW PW (14) 736 mW 5.9 mW/°C 383 mW PW (16) 839 mW 6.7 mW/°C 437 mW This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. RECOMMENDED OPERATING CONDITIONS MIN NOM MAX VCC Supply voltage 3 3.3 3.6 UNIT V VO Driver output voltage 0 2.4 V VIH High-level input voltage 2 VIL Low-level input voltage |VID| Magnitude of differential input voltage VIC Common-mode input voltage (see Figure 6) V 0.1 ŤV Ť 0.8 V 0.6 V ŤV Ť ID 2 2.4 * ID 2 V VCC-0.8 TA 4 Operating free-air temperature Submit Documentation Feedback —40 85 °C Copyright © 1998–2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVDM179 SN65LVDM180 SN65LVDM050 SN65LVDM051 SN65LVDM179, SN65LVDM180 SN65LVDM050, SN65LVDM051 www.ti.com .................................................................................................................................................... SLLS324J – DECEMBER 1998 – REVISED JULY 2009 DEVICE ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) MIN TYP (1) MAX No receiver load, driver RL = 50 Ω 10 15 Driver and receiver enabled, no receiver load, driver RL = 50 Ω 10 15 PARAMETER SN65LVDM179 SN65LVDM180 ICC Supply current SN65LVDM050 TEST CONDITIONS Driver enabled, receiver disabled, RL = 50 Ω 9 13 Driver disabled, receiver enabled, no load 1.7 5 Disabled 0.5 2 Drivers and receivers enabled, no receiver loads, driver RL = 50 Ω 19 27 Drivers enabled, receivers disabled, RL = 50 Ω 16 24 4 6 Drivers disabled, receivers enabled, no loads SN65LVDM051 (1) Disabled 0.5 1 Drivers enabled, no receiver loads, driver RL = 50 Ω 19 27 4 6 MIN TYP MAX 247 340 454 Drivers disabled, no loads UNIT mA mA mA mA All typical values are at 25°C and with a 3.3 V supply. DRIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS |VOD| Differential output voltage magnitude Δ|VOD| Change in differential output voltage magnitude between logic states VOC(SS) Steady-state common-mode output voltage ΔVOC(SS) Change in steady-state common-mode output voltage between logic states VOC(PP) Peak-to-peak common-mode output voltage DE RL = 50 Ω, See Figure 1 and Figure 2 –50 (1) 1.125 See Figure 3 50 1.2 1.375 –50 50 –20 mV V 50 mV 150 mV –0.5 µA IIH High-level input current IIL Low-level input current IOS Short-circuit output current IOZ High-impedance output current VO = 0 V or 2.4 V, other output at 1.2 V, DE AT 0.8 V –47 47 µA IO(OFF) Power-off output current VCC = 0 V, VO = 0 V or 2.4 V, other output at 1.2 V, DE AT 0.8 V –47 47 µA CIN Input capacitance (1) D DE D VIH = 5 V UNIT 2 –10 VIL = 0.8 V 20 –0.5 2 10 VOY or VOZ = 0 V 7 10 VOD = 0 V 7 10 3 µA mA pF The algebraic convention in which the least positive (most negative) value is designated minimum is used in this datasheet. Copyright © 1998–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65LVDM179 SN65LVDM180 SN65LVDM050 SN65LVDM051 5 SN65LVDM179, SN65LVDM180 SN65LVDM050, SN65LVDM051 SLLS324J – DECEMBER 1998 – REVISED JULY 2009 .................................................................................................................................................... www.ti.com RECEIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VIT+ Positive-going differential input voltage threshold VIT- Negative-going differential input voltage threshold VOH High-level output voltage IOH = -8 mA VOL Low-level output voltage IOL = 8 mA See Figure 5 and Table 2 Input current (A or B inputs) II(OFF) Power-off input current (A or B inputs) VCC = 0 IIH High-level input current (enables) VIH = 5 V IIL Low-level input current (enables) VIL = 0.8 V IOZ High-impedance output current VO = 0 or 5 V CI Input capacitance (1) MAX 50 –50 2.4 –20 VI = 2.4 V UNIT mV V 0.4 VI = 0 II MIN TYP (1) –11 –3 –20 –10 –1.2 V µA 20 µA 10 µA 10 µA 10 µA 5 pF All typical values are at 25°C and with a 3.3-V supply. DRIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT tPLH Propagation delay time, low-to-high-level output 1.7 2.7 ns tPHL Propagation delay time, high-to-low-level output 1.7 2.7 ns tr Differential output signal rise time 0.6 1 ns tf Differential output signal fall time 0.6 1 ns tsk(p) Pulse skew (|tpHL – tpLH|) tsk(o) Channel-to-channel output skew (2) tsk(pp) Part-to-part skew (3) tPZH Propagation delay time, high-impedance-to-high-level output tPZL Propagation delay time, high-impedance-to-low-level output tPHZ Propagation delay time, high-level-to-high-impedance output tPLZ Propagation delay time, low-level-to-high-impedance output (1) (2) (3) 6 RL = 50Ω, CL = 10 pF, See Figure 6 250 ps 100 See Figure 7 ps 1 ns 6 10 ns 6 10 ns 4 10 ns 5 10 ns All typical values are at 25°C and with a 3.3-V supply. tsk(o) is the maximum delay time difference between drivers on the same device. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. Submit Documentation Feedback Copyright © 1998–2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVDM179 SN65LVDM180 SN65LVDM050 SN65LVDM051 SN65LVDM179, SN65LVDM180 SN65LVDM050, SN65LVDM051 www.ti.com .................................................................................................................................................... SLLS324J – DECEMBER 1998 – REVISED JULY 2009 RECEIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP ( 1) MAX UNIT 3.7 4.5 ns 3.7 4.5 ns tPLH Propagation delay time, low-to-high-level output tPHL Propagation delay time, high-to-low-level output tsk(p) Pulse skew (|tpHL - tpLH|) 0.1 ns tsk(o) Channel-to-channel output skew 0.2 ns CL = 10 pF, See Figure 6 (2) tsk(pp) Part-to-part skew tr Output signal rise time tf Output signal fall time tPZH Propagation delay time, high-level-to-high-impedance output tPZL Propagation delay time, low-level-to-low-impedance output tPHZ Propagation delay time, high-impedance-to-high-level output tPLZ Propagation delay time, low-impedance-to-high-level output (1) (2) CL = 10 pF, See Figure 6 See Figure 7 1 ns 0.7 1.5 ns 0.9 1.5 ns 2.5 ns 2.5 ns 7 ns 4 ns All typical values are at 25°C and with a 3.3-V supply. tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. PARAMETER MEASUREMENT INFORMATION DRIVER IOY Driver Enable Y II A IOZ VOD V VOY Z VI OY )V OZ 2 VOC VOZ Figure 1. Driver Voltage and Current Definitions Copyright © 1998–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65LVDM179 SN65LVDM180 SN65LVDM050 SN65LVDM051 7 SN65LVDM179, SN65LVDM180 SN65LVDM050, SN65LVDM051 SLLS324J – DECEMBER 1998 – REVISED JULY 2009 .................................................................................................................................................... www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) 3.75 kΩ Y Input DA 50 Ω VOD + _ Z 0 ≤ Vtest ≤ 2.4 V 3.75 kΩ 2V 1.4 V 0.8 V Input tPHL tPLH 100% 80% VOD(H) Output 0V VOD(L) 20% 0% tf A. tr All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. Figure 2. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal 25 Ω, ±1% (2 Places) Driver Enable 3V Y Input 0V Z VOC VOC(PP) CL = 10 pF (2 Places) VOC(SS) VOC A. All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. The measurement of VOC(PP) is made on test equipment with a -3 dB bandwidth of at least 300 MHz. Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage 8 Submit Documentation Feedback Copyright © 1998–2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVDM179 SN65LVDM180 SN65LVDM050 SN65LVDM051 SN65LVDM179, SN65LVDM180 SN65LVDM050, SN65LVDM051 www.ti.com .................................................................................................................................................... SLLS324J – DECEMBER 1998 – REVISED JULY 2009 PARAMETER MEASUREMENT INFORMATION (continued) 25 Ω, ±1% (2 Places) Y 0.8 V or 2 V Z DE 1.2 V CL = 10 pF (2 Places) VOY 2V 1.4 V 0.8 V DE VOY or VOZ tPZH tPZL ~1.4 V 1.25 V 1.2 V D at 2 V and input to DE 1.2 V 1.15 V ~1 V D at 0.8 V and input to DE tPHZ VOZ or VOY A. VOZ tPLZ All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. Figure 4. Enable and Disable Time Circuit and Definitions Copyright © 1998–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65LVDM179 SN65LVDM180 SN65LVDM050 SN65LVDM051 9 SN65LVDM179, SN65LVDM180 SN65LVDM050, SN65LVDM051 SLLS324J – DECEMBER 1998 – REVISED JULY 2009 .................................................................................................................................................... www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) RECEIVER A V IA )V IB R VID 2 VIA VIC B VO VIB Figure 5. Receiver Voltage Definitions Table 2. Receiver Minimum and Maximum Input Threshold Test Voltages APPLIED VOLTAGES (V) 10 RESULTING DIFFERENTIAL INPUT VOLTAGE (mV) RESULTING COMMON-MODE INPUT VOLTAGE (V) VIA VIB VID VIC 1.225 1.175 50 1.2 1.175 1.225 –50 1.2 2.375 2.325 50 2.35 2.325 2.375 –50 2.35 0.05 0 50 0.05 0 0.05 –50 0.05 1.5 0.9 600 1.2 0.9 1.5 –600 1.2 2.4 1.8 600 2.1 1.8 2.4 –600 2.1 0.6 0 600 0.3 0 0.6 –600 0.3 Submit Documentation Feedback Copyright © 1998–2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVDM179 SN65LVDM180 SN65LVDM050 SN65LVDM051 SN65LVDM179, SN65LVDM180 SN65LVDM050, SN65LVDM051 www.ti.com .................................................................................................................................................... SLLS324J – DECEMBER 1998 – REVISED JULY 2009 VID VIA VIB CL 10 pF VO VIA 1.4 V VIB 1V VID 0.4 V 0V −0.4 V tPHL VO tPLH VOH 2.4 V 1.4 V 0.4 V VOL tf A. tr All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. Figure 6. Timing Test Circuit and Waveforms Copyright © 1998–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65LVDM179 SN65LVDM180 SN65LVDM050 SN65LVDM051 11 SN65LVDM179, SN65LVDM180 SN65LVDM050, SN65LVDM051 SLLS324J – DECEMBER 1998 – REVISED JULY 2009 .................................................................................................................................................... www.ti.com 1.2 V B 500 Ω A Inputs RE CL 10 pF + − VO NOTE A: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T. 2.5 V VTEST A 1V 2V RE 1.4 V 0.8 V tPZL tPZL tPLZ 2.5 V 1.4 V R VOL +0.5 V VOL 0V VTEST A 1.4 V 2V RE 1.4 V 0.8 V tPZH R tPZH VOH −0.5 V tPHZ VOH 1.4 V 0V Figure 7. Enable/Disable Time Test Circuit and Waveforms 12 Submit Documentation Feedback Copyright © 1998–2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVDM179 SN65LVDM180 SN65LVDM050 SN65LVDM051 SN65LVDM179, SN65LVDM180 SN65LVDM050, SN65LVDM051 www.ti.com .................................................................................................................................................... SLLS324J – DECEMBER 1998 – REVISED JULY 2009 TYPICAL CHARACTERISTICS DRIVER LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT DRIVER HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 4 3.5 VCC = 3.3 V TA = 25°C V OH− High-Level Output Voltage − V V OL − Low-Level Output Voltage − V VCC = 3.3 V TA = 25°C 3 2 1 0 3 2.5 2 1.5 1 .5 0 0 4 2 6 8 10 12 0 IOL − Low-Level Output Current − mA Figure 8. −4 −6 −8 IOH − High-Level Output Current − mA Figure 9. RECEIVER HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT RECEIVER LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 4 5 VCC = 3.3 V TA = 25°C VCC = 3.3 V TA = 25°C VOL − Low-Level Output Votlage − V VOH − High-Level Output Voltage − V −2 3 2 1 0 0 −20 −40 −60 IOH − High-Level Output Current − mA Figure 10. Copyright © 1998–2009, Texas Instruments Incorporated −80 4 3 2 1 0 0 10 20 30 40 50 IOL − Low-Level Output Current − mA Figure 11. Submit Documentation Feedback Product Folder Link(s): SN65LVDM179 SN65LVDM180 SN65LVDM050 SN65LVDM051 60 13 SN65LVDM179, SN65LVDM180 SN65LVDM050, SN65LVDM051 SLLS324J – DECEMBER 1998 – REVISED JULY 2009 .................................................................................................................................................... www.ti.com TYPICAL CHARACTERISTICS (continued) 2 VCC = 3.3 V VCC = 3 V VCC = 3.6 V 1.5 −50 −30 −10 50 30 70 TA − Free-Air Temperature − °C 10 DRIVER LOW-TO-HIGH LEVEL PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 2.5 t PLH − Low-To-High Propagation Delay Time − ns t PLH − High-To-Low Propagation Delay Time − ns DRIVER HIGH-TO-LOW LEVEL PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 2.5 90 2 VCC = 3.3 V VCC = 3 V VCC = 3.6 V 1.5 −50 −30 Figure 12. VCC = 3.3 V VCC = 3 V 3.5 VCC = 3.6 V 3 −30 −10 50 30 70 TA − Free−Air Temperature − °C Figure 14. 10 Submit Documentation Feedback 90 t PLH − Low-To-High Level Propagation Delay Time − ns t PLH − High-To-Low Level Propagation Dealy Time − ns 14 4.5 2.5 −50 50 30 70 TA − Free-Air Temperature − °C 10 90 Figure 13. RECEIVER HIGH-TO-LOW LEVEL PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 4 −10 RECEIVER LOW-TO-HIGH LEVEL PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 4.5 VCC = 3 V 4 VCC = 3.3 V 3.5 VCC = 3.6 V 3 2.5 −50 −30 −10 50 10 30 70 TA − Free-Air Temperature − °C 90 Figure 15. Copyright © 1998–2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVDM179 SN65LVDM180 SN65LVDM050 SN65LVDM051 SN65LVDM179, SN65LVDM180 SN65LVDM050, SN65LVDM051 www.ti.com .................................................................................................................................................... SLLS324J – DECEMBER 1998 – REVISED JULY 2009 APPLICATION INFORMATION Equipment • • • Hewlett Packard HP6624A DC power supply Tektronix TDS7404 Real Time Scope Agilent ParBERT E4832A Hewlett Packard HP6624A DC Power Supply Agilent ParBERT (E4832A) Bench Test Board Tektronix TDS7404 Real Time Scope Figure 16. Equipment Setup (a) (b) a. Tx + Rx running at 150 Mbps; Channel 1: R, Channel 2: Y-Z b. Rx only running at 150 Mbps; Channel 1: R c. Tx only running at 500 Mbps; Channel 1: Y-Z (c) Figure 17. Typical Eye Patterns SN65LVDM179: (T = 25°C; VCC = 3.6 V; PRBS = 223-1) Copyright © 1998–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65LVDM179 SN65LVDM180 SN65LVDM050 SN65LVDM051 15 SN65LVDM179, SN65LVDM180 SN65LVDM050, SN65LVDM051 SLLS324J – DECEMBER 1998 – REVISED JULY 2009 .................................................................................................................................................... www.ti.com (a) (b) a. Tx + Rx running at 150 Mbps; Channel 1: R, Channel 2: Y-Z b. Rx only running at 150 Mbps; Channel 1: R c. Tx only running at 500 Mbps; Channel 1: Y-Z (c) Figure 18. Typical Eye Patterns SN65LVDM180: (T = 25°C; VCC = 3.6 V; PRBS = 223-1) (a) (b) (c) a. All buffers running at 100 Mbps; Channel 1: R, Channel 2: 2R, Channel 3: 1Y-1Z, Channel 4: 2Y-2Z, b. Rx buffers only running at 100 Mbps; Channel 1: R, Channel 2: 2R c. Tx buffers only running at 400 Mbps; Channel 3: 1Y-1Z, Channel 4: 2Y-2Z, Figure 19. Typical Eye Patterns SN65LVDM050: (T = 25°C; VCC = 3.6 V; PRBS = 223-1) (a) (b) (c) a. All buffers running at 100 Mbps; Channel 1: R, Channel 2: 2R, Channel 3: 1Y-1Z, Channel 4: 2Y-2Z, b. Rx buffers only running at 100 Mbps; Channel 1: R, Channel 2: 2R c. Tx buffers only running at 400 Mbps; Channel 3: 1Y-1Z, Channel 4: 2Y-2Z, Figure 20. Typical Eye Patterns SN65LVDM051: (T = 25°C; VCC = 3.6 V; PRBS = 223-1) 16 Submit Documentation Feedback Copyright © 1998–2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVDM179 SN65LVDM180 SN65LVDM050 SN65LVDM051 SN65LVDM179, SN65LVDM180 SN65LVDM050, SN65LVDM051 www.ti.com .................................................................................................................................................... SLLS324J – DECEMBER 1998 – REVISED JULY 2009 The devices are generally used as building blocks for high-speed point-to-point data transmission. Ground differences are less than 1 V with a low common-mode output and balanced interface for low noise emissions. Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/receivers maintain ECL speeds without the power and dual supply requirements. Transmission Distance - m 1000 30% Jitter 100 5% Jitter 10 1 24 AWG UTP 96 Ω (PVC Dielectric) 0.1 100k 1M 10M 100M Data Rate - Hz Figure 21. Data Transmission Distance Versus Rate FAIL SAFE One of the most common problems with differential signaling applications is how the system responds when no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that its output logic state can be indeterminate when the differential input voltage is between –50 mV and 50 mV and within its recommended input common-mode voltage range. TI's LVDS receiver is different; however, in the way it handles the open-input circuit situation. Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver pulls each line of the signal pair to near VCC through 300-kΩ resistors as shown in Figure 22. The fail-safe feature uses an AND gate with input voltage thresholds at about 2.3 V to VCC – 0.4 V to detect this condition and force the output to a high-level, regardless of the differential input voltage. VCC 300 kΩ 300 kΩ A Rt = 100 Ω (Typ) Y B VIT ≈ 2.3 V Figure 22. Open-Circuit Fail Safe of the LVDS Receiver It is only under these conditions that the output of the receiver is valid with less than a 50-mV differential input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that could defeat the pullup currents from the receiver and the fail-safe feature. Copyright © 1998–2009, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN65LVDM179 SN65LVDM180 SN65LVDM050 SN65LVDM051 17 SN65LVDM179, SN65LVDM180 SN65LVDM050, SN65LVDM051 SLLS324J – DECEMBER 1998 – REVISED JULY 2009 .................................................................................................................................................... www.ti.com REVISION HISTORY Changes from Revision I (January 2009) to Revision J ................................................................................................. Page • • 18 Changed value from 40 to -40 ............................................................................................................................................... 4 Deleted value 85 from NOM value and moved to max.......................................................................................................... 4 Submit Documentation Feedback Copyright © 1998–2009, Texas Instruments Incorporated Product Folder Link(s): SN65LVDM179 SN65LVDM180 SN65LVDM050 SN65LVDM051 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN65LVDM050D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDM050 Samples SN65LVDM050DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDM050 Samples SN65LVDM050PW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDM050 Samples SN65LVDM050PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDM050 Samples SN65LVDM050PWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDM050 Samples SN65LVDM051D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDM051 Samples SN65LVDM051DG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDM051 Samples SN65LVDM051DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDM051 Samples SN65LVDM051PW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDM051 Samples SN65LVDM051PWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDM051 Samples SN65LVDM179D ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 DM179 Samples SN65LVDM179DG4 ACTIVE SOIC D 8 75 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 DM179 Samples SN65LVDM179DGK ACTIVE VSSOP DGK 8 80 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 M79 Samples SN65LVDM179DGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 M79 Samples SN65LVDM179DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 DM179 Samples SN65LVDM179DRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 DM179 Samples SN65LVDM180D ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDM180 Samples SN65LVDM180DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDM180 Samples SN65LVDM180PW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDM180 Samples SN65LVDM180PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDM180 Samples Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of