SN65LVDS048AD

SN65LVDS048A www.ti.com SLLS451B – SEPTEMBER 2000 – REVISED SEPTEMBER 2002 LVDS QUAD DIFFERENTIAL LINE RECEIVER FEATURES • • • • • • • • • • • • • • >400 Mbps (200 MHz) Signaling Rates Flow-Through Pinout Simplifies PCB Layout 50 ps Channel-to-Channel Skew (Typ) 200 ps Differential Skew (Typ) Propagation Delay Times 2.7 ns (Typ) 3.3-V Power Supply Design High Impedance LVDS Inputs on Power Down Low-Power Dissipation (40 mW at 3.3 V Static) Accepts Small Swing (350 mV) Differential Signal Levels Supports Open, Short, and Terminated Input Fail-Safe Industrial Operating Temperature Range (–40°C to 85°C) Conforms to TIA/EIA-644 LVDS Standard Available in SOIC and TSSOP Packages Pin-Compatible With DS90LV048A From National SN65LVDS048AD (Marked as LVDS048A) SN65LVDS048APW (Marked as DL048A) (TOP VIEW) RIN1– RIN1+ RIN2+ RIN2– RIN3– RIN3+ RIN4+ RIN4– 1 16 EN 2 15 3 14 4 13 5 12 ROUT1 ROUT2 VCC GND ROUT3 ROUT4 6 11 7 10 8 9 EN functional diagram EN EN RIN1+ RIN1– RIN2+ RIN2– R1 ROUT1 R2 ROUT2 R3 ROUT3 R4 ROUT4 RIN3+ RIN3– RIN4+ RIN4– DESCRIPTION The SN65LVDS048A is a quad differential line receiver that implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the quad differential receivers will provide a valid logical output state with a ±100-mV differential input voltage within the input common-mode voltage range. The input common-mode voltage range allows 1 V of ground potential difference between two LVDS nodes The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics. The SN65LVDS048A is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2000–2002, Texas Instruments Incorporated SN65LVDS048A www.ti.com SLLS451B – SEPTEMBER 2000 – REVISED SEPTEMBER 2002 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. TRUTH TABLE (1) DIFFERENTIAL INPUT ENABLES RIN+– RIN– OUTPUT EN EN H L or OPEN VID ≥ 100 mV H VID ≤ –100 mV Open/short or terminated X (1) ROUT L H All other conditions Z H = high level, L = low level, X = irrelevant, Z = high impedance (off) EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS VCC VCC 50 Ω 300 kΩ 300 kΩ VCC 5Ω EN,EN Output 7V Input Input 7V 7V 300 kΩ 7V ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) (2) UNIT VCC Supply voltage range –0.3 V to 4 V VI(RIN+, RIN-) Input voltage range –0.3 V to 4 V Enable input voltage (EN, EN ) VO(ROUT) –0.3 V to (VCC +0.3 V) Output voltage Bus-pin (RIN+, RIN–) electrostatic –0.3 V to (VCC +0.3 V) discharge (3) Continuous power dissipation Storage temperature range –65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) (2) (3) 2 > 10 kV See Dissipation Rating Table 260°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. Tested in accordance with MIL-STD-883C Method 3015.7. Submit Documentation Feedback SN65LVDS048A www.ti.com SLLS451B – SEPTEMBER 2000 – REVISED SEPTEMBER 2002 DISSIPATION RATING TABLE (1) PACKAGE TA ≤ 25°C POWER RATING OPERATING FACTOR (1) ABOVE TA = 25°C TA = 85°C POWER RATING D 950 mW 7.6 mW/°C 494 mW PW 774 mW 6.2 mW/°C 402 mW This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. RECOMMENDED OPERATING CONDITIONS VCC MIN NOM MAX 3 3.3 3.6 V 3 V Supply voltage Receiver input voltage GND |V |V VIC Common-mode input voltage TA Operating free-air temperature UNIT | ID 2 | ID 2 2.4
V VCC– 0.8 –40 25 85 °C MIN TYP (2) MAX UNIT ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) (1) PARAMETER VIT+ Differential input high threshold voltage VIT– Differential input low threshold voltage V(CMR) Common mode voltage range IIN Input current TEST CONDITIONS VCM = 1.2 V, 0.05 V, 2.35 V (3) 100 –100 mV VID = 200 mV pk to pk (4) 0.1 2.3 V VIN = 2.8 V –20 ±1 20 µA –20 ±1 20 µA 20 µA VIN = 0 V VIN = 3.6 V, VCC = 3.6 V or 0 V –20 ±1 IOH = -0.4 mA, VID = 200 mV VCC = 0 V 2.7 3.2 V IOH = -0.4 mA, input terminated 2.7 3.2 V IOH = -0.4 mA, input shorted 2.7 VOH Output high voltage VOL Output low voltage IOL = 2 mA, VID = -200 mV 0.05 0.25 V IOS Output short circuit current Enabled, VOUT = 0 V (5) –65 –100 mA IO(Z) Output 3-state current Disabled, VOUT = 0 V or VCC –1 1 µA VIH Input high voltage VIL Input low voltage II Input current (enables) VIN = 0 V or VCC, Other input = VCC or GND VIK Input clamp voltage ICL = –18 mA ICC No load supply current, receivers enabled EN = VCC, Inputs open ICC(Z) No load supply current, receivers disabled EN = GND, Inputs open (1) (2) (3) (4) (5) 3.2 V 2.0 VCC V GND 0.8 V –10 10 µA –1.5 8 15 mA 0.6 1.5 mA –0.8 V Current into device pin is defined as positive. Current out of the device is defined as negative. All voltages are referenced to ground, unless otherwise specified. All typical values are at 25°C and with a 3.3-V supply. VCC is always higher than RIN+ and RIN- voltage, RIN- and RIN+ have a voltage range of -0.2 V to VCC-VID/2. To be compliant with ac specifications the common voltage range is 0.1 V to 2.3 V. The VCMR range is reduced for larger VID, Example: If VID = 400 mV, the VCMR is 0.2 V to 2.2 V. The fail-safe condition with inputs shorted is not supported over the common-mode range of 0 V to 2.4 V, but is supported only with inputs shorted and no external common-mode voltage applied. A VID up to VCC-0 V may be applied to the RIN+ and RIN- inputs with the common-mode voltage set to VCC/2. Propagation delay and differential pulse skew decrease when VID is increased from 200 mV to 400 mV. Skew specifications apply for 200 mV < VID < 800 mV over the common-mode range. Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time. Do not exceed maximum junction temperature specification. Submit Documentation Feedback 3 SN65LVDS048A www.ti.com SLLS451B – SEPTEMBER 2000 – REVISED SEPTEMBER 2002 SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) (1) PARAMETER TEST CONDITIONS MIN TYP (2) MAX UNIT tPHL Differential propagation delay, high-to-low 1.9 2.7 3.7 ns tPLH Differential propagation delay, low-to-high 1.9 2.9 3.7 ns 200 450 ps 50 500 ps 1 ns ) (3) tSK(p) Differential pulse skew (tPHLD - tPLHD tSK(o) Differential channel-to-channel skew; same device (4) tSK(pp) Differential part-to-part skew (5) tSK(lim) Differential part-to-part skew (6) 1.5 ns tr Rise time 0.5 1 ns tf Fall time 0.5 1 ns tPHZ Disable time high to Z 8 9 ns tPLZ Disable time low to Z 6 8 ns tPZH Enable time Z to high 8 10 ns tPZL Enable time Z to low 7 8 ns f(MAX) (1) (2) (3) (4) (5) (6) (7) 4 Maximum operating frequency (7) CL = 15 pF VID = 200 mV (see Figure 1 and Figure 2) RL = 2 K Ω CL = 15 pF (see Figure 3 and Figure 4) All channels switching 200 250 MHz Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50 Ω, tr and tf (0%–100%) ≤ 3 ns for RIN. All typical values are at 25°C and with a 3.3-V supply. tSK(p)|tPLH – tPHL| is the magnitude difference in differential propagation delay time between the positive going edge andthe negative going edge of the same channel. tSK(o) is the differential channel-to-channel skew of any event on the same device. tSK(pp) is the differential part-to-part skew, and is defined as the difference between the minimum and the maximum specified differential propagation delays. This specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range. tsk(lim) part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. tsk(lim) is defined as |Min - Max| differential propagation delay. f(MAX) generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% to 55%,VOD > 250 mV, all channels switching Submit Documentation Feedback SN65LVDS048A www.ti.com SLLS451B – SEPTEMBER 2000 – REVISED SEPTEMBER 2002 PARAMETER MEASUREMENT INFORMATION RIN+ Generator RIN– R ROUT CL 50 Ω 50 Ω Receiver Enabled Figure 1. Receiver Propagation Delay and Transition Time Test Circuit RIN– 1.3 V OV Differential VID = 200 mV 1.2 V RIN+ 1.1 V tPLH ROUT tPHL 1.5 V 20% tr 80% 80% VOH 1.5 V 20% VOL tf Figure 2. Receiver Propagation Delay and Transition Time Waveforms Submit Documentation Feedback 5 SN65LVDS048A www.ti.com SLLS451B – SEPTEMBER 2000 – REVISED SEPTEMBER 2002 PARAMETER MEASUREMENT INFORMATION (continued) VCC RIN+ Generator RIN– EN 50 Ω S1 RL Device Under Test EN ROUT CL 1/4 65LVDS048A CL Includes Load and Test Jig Capacitance. S1 = VCC for tPZL and tPLZ Measurements. S1 = GND for tPZH and tPHZ Measurements. Figure 3. Receiver 3-State Delay Test Circuit 1.5 V EN When EN = GND or Open 1.5 V 3V 0V 3V EN When EN = VCC 0V tPLZ tPZL VCC Output When VID = –100 mV Output When VID = 100 mV 50% 0.5 V tPHZ VOL tPZH VOH 0.5 V 50% GND Figure 4. Receiver 3-State Delay Waveforms 6 Submit Documentation Feedback SN65LVDS048A www.ti.com SLLS451B – SEPTEMBER 2000 – REVISED SEPTEMBER 2002 TYPICAL CHARACTERISTICS OUTPUT HIGH VOLTAGE vs POWER SUPPLY VOLTAGE OUTPUT LOW VOLTAGE vs POWER SUPPLY VOLTAGE 3.6 57 TA = 25°C VID = 200 mV VOL − Output Low Voltage − mV VOH − Output High Voltage − V TA = 25°C VID = 200 mV 3.4 3.2 3 2.8 3 3.3 56 55 54 53 52 3.6 3 VCC − Power Supply Voltage − V Figure 5. Figure 6. OUTPUT SHORT CIRCUIT CURRENT vs POWER SUPPLY VOLTAGE DIFFERENTIAL TRANSITION VOLTAGE vs POWER SUPPLY VOLTAGE −76 − Differential Transition Voltage − mV TA = 25°C VO = 0 V −72 −68 −64 −60 3 3.3 VCC − Power Supply Voltage − V 3.6 VIT+ VIT− I OS − Output Short Circuit Current − mA 3.6 50 −80 −56 3.3 VCC − Power Supply Voltage − V TA = 25°C 40 30 20 10 0 3 Figure 7. 3.3 VCC − Power Supply Voltage − V 3.6 Figure 8. Submit Documentation Feedback 7 SN65LVDS048A www.ti.com SLLS451B – SEPTEMBER 2000 – REVISED SEPTEMBER 2002 TYPICAL CHARACTERISTICS (continued) DIFFERENTIAL PROPAGATION DELAY vs COMMON-MODE VOLTAGE 4 t PLH, t PHL − Differential Propagation Delay − ns t PLH, t PHL − Differential Propagation Delay − ns DIFFERENTIAL PROPAGATION DELAY vs DIFFERENTIAL INPUT VOLTAGE tPLH 3 tPHL 2 TA = 25°C f = 20 MHz VCM = 1.2 V CI = 15 pF VCC = 3.3 V 1 0 0 500 1000 1500 2000 2500 Differential Input Voltage − mV 4 tPLH 3 tPHL 2 TA = 25°C f = 20 MHz VCM = 1.2 V CI = 15 pF VCC = 3.3 V 1 0 −0.5 3000 0 0.5 1 1.5 Common-Mode Voltage − V Figure 9. Figure 10. DATA TRANSFER RATE vs FREE-AIR TEMPERATURE 800 Data Transfer Rate − Mxfr/s 750 700 650 600 215 −1 prbs NRZ VCC = 3.3 V VID = 0.4 V VIC = 1.2 V CL = 5.5 pF 40% Open Eye 4 Receivers Switching Input Jitter < 45 ps 550 500 450 400 −40 −20 0 20 40 60 TA − Free-Air Temperature − °C Figure 11. 8 Submit Documentation Feedback 80 2 2.5 SN65LVDS048A www.ti.com SLLS451B – SEPTEMBER 2000 – REVISED SEPTEMBER 2002 APPLICATION INFORMATION FAIL SAFE One of the most common problems with differential signaling applications is how the system responds when no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that its output logic state can be indeterminate when the differential input voltage is between –100 mV and 100 mV and within its recommended input common-mode voltage range. TI's LVDS receiver is different in how it handles the open-input circuit situation, however. Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver will pull each line of the signal pair to near VCC through 300-kΩ resistors as shown in Figure 10. The fail-safe feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the output to a high-level regardless of the differential input voltage. VCC 300 kΩ 300 kΩ A Rt = 100 Ω (Typ) Y B VIT ≈ 2.3 V Figure 12. Open-Circuit Fail Safe of the LVDS Receiver It is only under these conditions that the output of the receiver will be valid with less than a 100-mV differential input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that could defeat the pullup currents from the receiver and the fail-safe feature. Submit Documentation Feedback 9 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN65LVDS048AD ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS048A Samples SN65LVDS048ADG4 ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS048A Samples SN65LVDS048ADR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 LVDS048A Samples SN65LVDS048APW ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 DL048A Samples SN65LVDS048APWG4 ACTIVE TSSOP PW 16 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 DL048A Samples SN65LVDS048APWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 DL048A Samples SN65LVDS048APWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 DL048A Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of