SN65LVDS048
LVDS QUAD DIFFERENTIAL LINE RECEIVER
SLLS415A – JUNE 2000 – REVISED SEPTEMBER 2000
D
D
D
D
D
D
D
D
D
D
D
D
D
D
>400 Mbps (200 MHz) Signaling Rates
Flow-Through Pinout Simplifies PCB
Layout
50 ps Channel-to-Channel Skew (Typ)
200 ps Differential Skew (Typ)
Propagation Delay Times 2.7 ns (Typ)
3.3 V Power Supply Design
High-Impedance LVDS Inputs on Power
Down
Low-Power Dissipation (40 mW at 3.3 V
Static)
Accepts Small Swing (350 mV) Differential
Signal Levels
Supports Open, Short, and Terminated
Input Fail-Safe
Industrial Operating Temperature Range
(–40°C to 85°C)
Conforms to TIA/EIA-644 LVDS Standard
Available in SOIC and TSSOP Packages
Pin-Compatible With DS90LV048A From
National
NOT RECOMMENDED FOR NEW DESIGNS
For Replacement Use SN65LVDS048A
D OR PW PACKAGE
(TOP VIEW)
RIN1–
RIN1+
RIN2+
RIN2–
RIN3–
RIN3+
RIN4+
RIN4–
1
16
EN
2
15
3
14
4
13
5
12
ROUT1
ROUT2
VCC
GND
ROUT3
ROUT4
6
11
7
10
8
9
EN
functional diagram
EN
EN
RIN1+
RIN1–
RIN2+
RIN2–
description
The SN65LVDS048 is a quad differential line receiver
that implements the electrical characteristics of
low-voltage differential signaling (LVDS). This signaling
technique lowers the output voltage levels of 5-V
differential standard levels (such as EIA/TIA-422B) to
reduce the power, increase the switching speeds, and
allow operation with a 3.3-V supply rail. Any of the quad
differential receivers will provide a valid logical output
state with a ±100-mV differential input voltage within the
input common-mode voltage range. The input
common-mode voltage range allows 1 V of ground
potential difference between two LVDS nodes.
RIN3+
RIN3–
RIN4+
RIN4–
R1
ROUT1
R2
ROUT2
R3
ROUT3
R4
ROUT4
The intended application of this device and signaling technique is for point-to-point baseband data transmission
over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board
traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation
characteristics of the media, the noise coupling to the environment, and other system characteristics.
The SN65LVDS048 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN65LVDS048
LVDS QUAD DIFFERENTIAL LINE RECEIVER
SLLS415A – JUNE 2000 – REVISED SEPTEMBER 2000
TRUTH TABLE
ENABLES
DIFFERENTIAL INPUT
RIN+ – RIN–
VID ≥ 100 mV
EN
EN
VID ≤ –100 mV
Open/short or terminated
H
L or OPEN
OUTPUT
ROUT
H
L
H
X
All other conditions
Z
H = high level, L = low level, X = irrelevant, Z = high impedance (off)
equivalent input and output schematic diagrams
VCC
VCC
VCC
50 Ω
300 kΩ
300 kΩ
5Ω
EN,EN
Output
7V
Input
Input
7V
7V
300 kΩ
7V
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V
Input voltage range, VI(RIN+, RIN–) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4 V
Enable input voltage (EN, EN ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (VCC +0.3 V)
Output voltage, VO(ROUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to (VCC +0.3 V)
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
OPERATING FACTOR‡
ABOVE TA = 25°C
TA = 85°C
POWER RATING
D
950 mW
7.6 mW/°C
494 mW
PW
774 mW
6.2 mW/°C
402 mW
‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with
no air flow.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65LVDS048
LVDS QUAD DIFFERENTIAL LINE RECEIVER
SLLS415A – JUNE 2000 – REVISED SEPTEMBER 2000
recommended operating conditions
MIN
NOM
MAX
3
3.3
3.6
V
3
V
* |V2ID|
V
VCC – 0.8
85
°C
Supply voltage, VCC
Receiver input voltage
GND
|V
ID
2
Common–mode input voltage, VIC
Operating free-air temperature, TA
|
2.4
–40
25
UNIT
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Note 2)
PARAMETER
TEST CONDITIONS
VIT+
VIT–
Differential input high threshold voltage
V(CMR)
Common mode voltage range
IIN
VOH
Differential input low threshold voltage
VCM = 1.2 V,, 0.05 V,, 2.35 V
(see Note 3)
VID = 200 mV pk to pk (see Note 4)
VIN = 2.8 V
VCC = 3.6
3 6 V or 0 V
VIN = 0 V
Input current
Output high voltage
TYP†
MAX
100
–100
0.1
UNIT
mV
2.3
V
–20
±1
20
µA
–20
±1
20
µA
VIN = 3.6 V
VCC = 0 V
IOH = –0.4 mA, VID = 200 mV
–20
±1
20
µA
2.7
3.2
V
IOH = –0.4 mA, input terminated
IOH = –0.4 mA, input shorted
2.7
3.2
V
2.7
3.2
V
VOL
IOS
Output low voltage
Output short circuit current
IOL = 2 mA, VID = –200 mV
Enabled, VOUT = 0 V (see Note 5)
IO(Z)
VIH
Output 3-state current
Disabled, VOUT = 0 V or VCC
VIL
Input low voltage
II
Input current (enables)
VIK
ICC
Input clamp voltage
Input high voltage
VIN = 0 V or VCC,
Other input = VCC or GND
No load supply current, receivers enabled
MIN
ICL = –18 mA
EN = VCC,
0.05
0.25
V
–65
–100
mA
–1
1
µA
2.0
VCC
0.8
V
GND
–10
10
µA
15
mA
–1.5
Inputs open
–0.8
8
V
V
ICC(Z)
No load supply current, receivers disabled
EN = GND,
Inputs open
0.6
1.5
mA
† All typical values are at 25°C and with a 3.3-V supply.
NOTES: 2. Current into device pin is defined as positive. Current out of the device is defined as negative. All voltages are referenced to ground,
unless otherwise specified.
3. VCC is always higher than RIN+ and RIN– voltage, RIN– and RIN+ have a voltage range of –0.2 V to VCC–VID/2. To be compliant with
ac specifications the common voltage range is 0.1 V to 2.3 V.
4. The VCMR range is reduced for larger VID, Example: If VID = 400 mV, the VCMR is 0.2 V to 2.2 V. The fail-safe condition with inputs
shorted is not supported over the common-mode range of 0 V to 2.4 V, but is supported only with inputs shorted and no external
common-mode voltage applied. A VID up to VCC–0 V may be applied to the RIN+ and RIN– inputs with the common-mode voltage
set to VCC/2. Propagation delay and differential pulse skew decrease when VID is increased from 200 mV to 400 mV. Skew
specifications apply for 200 mV < VID < 800 mV over the common-mode range.
5. Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be
shorted at a time. Do not exceed maximum junction temperature specification.
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3
SN65LVDS048
LVDS QUAD DIFFERENTIAL LINE RECEIVER
SLLS415A – JUNE 2000 – REVISED SEPTEMBER 2000
switching characteristics over recommended operating conditions (unless otherwise noted) (see
Notes 6)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
2.7
3.7
ns
tPHL
tPLH
Differential propagation delay, high-to-low
1.9
Differential propagation delay, low-to-high
1.9
tSK(p)
tSK(o)
Differential pulse skew (tPHLD – tPLHD) (see Note 7)
tSK(pp)
tSK(lim)
Differential part-to-part skew (see Note 9)
tr
tf
Rise time
Fall time
tPHZ
Disable time high to Z
tPLZ
tPZH
Disable time low to Z
tPZL
Enable time Z to low
Differential channel-to-channel skew; same device (see Note 8)
CL = 15 pF
VID = 200 mV
(see Figure 1 and 2 )
2.9
3.7
ns
200
450
ps
50
500
ps
1
ns
1.5
ns
0.5
1
ns
0.5
1
ns
8
9
ns
6
8
ns
8
10
ns
7
8
ns
Differential part-to-part skew (see Note10)
RL = 2 K Ω
CL = 15 pF
F
(
g
(see
Figure
3 and 4 )
Enable time Z to high
UNIT
f(MAX)
Maximum operating frequency (see Note 11)
All channels switching
200
250
MHz
† All typical values are at 25°C and with a 3.3-V supply.
NOTES: 6. Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50 Ω, tr and tf (0% – 100%) ≤ 3 ns for RIN.
7. tSK(p)|tPLH – tPHL| is the magnitude difference in differential propagation delay time between the positive going edge and
the negative going edge of the same channel.
8. tSK(o) is the differential channel-to-channel skew of any event on the same device.
9. tSK(pp) is the differential part-to-part skew, and is defined as the difference between the minimum and the maximum specified
differential propagation delays. This specification applies to devices at the same VCC and within 5°C of each other within the
operating temperature range.
10. tsk(lim) part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to
devices over recommended operating temperature and voltage ranges, and across process distribution. tsk(lim) is defined as |Min
– Max| differential propagation delay.
11. f(MAX) generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% to 55%,
VOD > 250 mV, all channels switching
4
POST OFFICE BOX 655303
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SN65LVDS048
LVDS QUAD DIFFERENTIAL LINE RECEIVER
SLLS415A – JUNE 2000 – REVISED SEPTEMBER 2000
PARAMETER MEASUREMENT INFORMATION
RIN+
Generator
RIN–
50 Ω
R
ROUT
CL
50 Ω
Receiver Enabled
Figure 1. Receiver Propagation Delay and Transition Time Test Circuit
RIN–
1.3 V
OV Differential
VID = 200 mV
1.2 V
RIN+
1.1 V
tPLH
ROUT
tPHL
1.5 V
20%
80%
tr
80%
VOH
1.5 V
20%
VOL
tf
Figure 2. Receiver Propagation Delay and Transition Time Waveforms
POST OFFICE BOX 655303
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5
SN65LVDS048
LVDS QUAD DIFFERENTIAL LINE RECEIVER
SLLS415A – JUNE 2000 – REVISED SEPTEMBER 2000
PARAMETER MEASUREMENT INFORMATION
VCC
RIN+
EN
Generator
50 Ω
RIN–
S1
RL
Device
Under
Test
EN
ROUT
CL
1/4 65LVDS048
CL Includes Load and Test Jig Capacitance.
S1 = VCC for tPZL and tPLZ Measurements.
S1 = GND for tPZH and tPHZ Measurements.
Figure 3. Receiver 3-State Delay Test Circuit
1.5 V
EN When EN = GND or Open
1.5 V
3V
0V
3V
EN When EN = VCC
0V
tPLZ
tPZL
VCC
Output When
VID = –100 mV
Output When
VID = 100 mV
50%
0.5 V
tPHZ
VOL
tPZH
VOH
0.5 V
50%
GND
Figure 4. Receiver 3-State Delay Waveforms
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65LVDS048
LVDS QUAD DIFFERENTIAL LINE RECEIVER
SLLS415A – JUNE 2000 – REVISED SEPTEMBER 2000
TYPICAL CHARACTERISTICS
OUTPUT HIGH VOLTAGE
vs
POWER SUPPLY VOLTAGE
OUTPUT LOW VOLTAGE
vs
POWER SUPPLY VOLTAGE
3.6
57
TA = 25°C
VID = 200 mV
VOL – Output Low Voltage – mV
VOH – Output High Voltage – V
TA = 25°C
VID = 200 mV
3.4
3.2
3
2.8
3
3.3
56
55
54
53
52
3.6
3
3.3
VCC – Power Supply Voltage – V
Figure 5
Figure 6
OUTPUT SHORT CIRCUIT CURRENT
vs
POWER SUPPLY VOLTAGE
–72
–68
–64
–60
–56
3
3.3
VCC – Power Supply Voltage – V
3.6
– Differential Transition Voltage – mV
I OS – Output Short Circuit Current – mA
TA = 25°C
VO = 0 V
50
VIT+ VIT–
DIFFERENTIAL TRANSITION VOLTAGE
vs
POWER SUPPLY VOLTAGE
–80
–76
3.6
VCC – Power Supply Voltage – V
10
TA = 25°C
40
30
20
0
3
Figure 7
3.3
VCC – Power Supply Voltage – V
3.6
Figure 8
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7
SN65LVDS048
LVDS QUAD DIFFERENTIAL LINE RECEIVER
SLLS415A – JUNE 2000 – REVISED SEPTEMBER 2000
TYPICAL CHARACTERISTICS
DIFFERENTIAL PROPAGATION DELAY
vs
COMMON-MODE VOLTAGE
4
t PLH, t PHL – Differential Propagation Delay – ns
t PLH, t PHL – Differential Propagation Delay – ns
DIFFERENTIAL PROPAGATION DELAY
vs
DIFFERENTIAL INPUT VOLTAGE
tPLH
3
tPHL
2
TA = 25°C,
f = 20 MHz,
VCM = 1.2 V,
CI = 15 pF,
VCC = 3.3 V
1
0
0
500
1000
1500
2000
2500
Differential Input Voltage – mV
3000
4
tPHL
2
TA = 25°C,
f = 20 MHz,
VCM = 1.2 V,
CI = 15 pF,
VCC = 3.3 V
1
0
–0.5
Figure 9
8
tPLH
3
0
0.5
1
1.5
Common-Mode Voltage – V
Figure 10
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2
2.5
SN65LVDS048
LVDS QUAD DIFFERENTIAL LINE RECEIVER
SLLS415A – JUNE 2000 – REVISED SEPTEMBER 2000
APPLICATION INFORMATION
fail safe
One of the most common problems with differential signaling applications is how the system responds when
no differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in
that its output logic state can be indeterminate when the differential input voltage is between –100 mV and 100
mV and within its recommended input common-mode voltage range. TI’s LVDS receiver is different in how it
handles the open-input circuit situation, however.
Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be
when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver
will pull each line of the signal pair to near VCC through 300-kΩ resistors as shown in Figure 10. The fail-safe
feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the
output to a high-level regardless of the differential input voltage.
VCC
300 kΩ
300 kΩ
A
Rt = 100 Ω (Typ)
Y
B
VIT ≈ 2.3 V
Figure 11. Open-Circuit Fail Safe of the LVDS Receiver
It is only under these conditions that the output of the receiver will be valid with less than a 100 mV differential
input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as
long as it is connected as shown in the figure. Other termination circuits may allow a dc current to ground that
could defeat the pullup currents from the receiver and the fail-safe feature.
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9
SN65LVDS048
LVDS QUAD DIFFERENTIAL LINE RECEIVER
SLLS415A – JUNE 2000 – REVISED SEPTEMBER 2000
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
14
0.010 (0,25) M
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°– 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
PINS **
0.004 (0,10)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
4040047 / D 10/96
NOTES: A.
B.
C.
D.
10
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012
POST OFFICE BOX 655303
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SN65LVDS048
LVDS QUAD DIFFERENTIAL LINE RECEIVER
SLLS415A – JUNE 2000 – REVISED SEPTEMBER 2000
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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11
PACKAGE OPTION ADDENDUM
www.ti.com
3-Aug-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
SN65LVDS048D
OBSOLETE
SOIC
D
16
TBD
Call TI
Call TI
SN65LVDS048DR
OBSOLETE
SOIC
D
16
TBD
Call TI
Call TI
SN65LVDS048PW
OBSOLETE
TSSOP
PW
16
TBD
Call TI
Call TI
SN65LVDS048PWR
OBSOLETE
TSSOP
PW
16
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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www.ti.com/telephony
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www.ti.com/video
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www.ti.com/wireless
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