SN74ABT853PWR

SN54ABT853, SN74ABT853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS198G − FEBRUARY 1991 − REVISED OCTOBER 2010 D D D D D D description The ’ABT853 8-bit to 9-bit parity transceivers are designed for communication between data buses. When data is transmitted from the A bus to the B bus, a parity bit is generated. When data is transmitted from the B bus to the A bus with its corresponding parity bit, the open-collector parity-error (ERR) output indicates whether or not an error in the B data has occurred. The output-enable (OEA and OEB) inputs can be used to disable the device so that the buses are effectively isolated. The ’ABT853 transceivers provide true data at their outputs. 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC B1 B2 B3 B4 B5 B6 B7 B8 PARITY OEB LE SN54ABT853 . . . FK PACKAGE (TOP VIEW) A3 A4 A5 NC A6 A7 A8 4 5 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 B3 B4 B5 NC B6 B7 B8 CLR GND NC LE OEB PARITY D OEA A1 A2 A3 A4 A5 A6 A7 A8 ERR CLR GND A2 A1 OEA NC V CC B1 B2 D Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JESD 17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C High-Drive Outputs (−32-mA IOH, 64-mA IOL) High-Impedance State During Power Up and Power Down Parity-Error Flag With Parity Generator/Checker Latch for Storage of Parity-Error Flag Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (NT) and Ceramic (JT) DIPs SN54ABT853 . . . JT OR W PACKAGE SN74ABT853 . . . DB, DW, NT, OR PW PACKAGE (TOP VIEW) ERR D State-of-the-Art EPIC-ΙΙB ™ BiCMOS Design NC − No internal connection A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with the ERR flag. The parity-error output can be passed, sampled, stored, or cleared from the latch using the latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic capability. When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-ΙΙB is a trademark of Texas Instruments Incorporated. Copyright © 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ABT853, SN74ABT853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS198G − FEBRUARY 1991 − REVISED OCTOBER 2010 description (continued) The SN54ABT853 is characterized for operation over the full military temperature range of −55°C to 125°C. The SN74ABT853 is characterized for operation from −40°C to 85°C. FUNCTION TABLE INPUTS OUTPUTS AND I/Os Ai Σ OF H Bi† Σ OF H A B NA NA A B NA NA FUNCTION OEA CLR LE L H X X H L X L NA H L H H NA X X NA NA NC Store error flag X X L H X X X NA NA H Clear error flag register H L H L Odd Even H H X L H X X L L Odd X L H Even X Odd Even L NA H H L A data to B bus and generate parity B data to A bus and check parity NC X Z Z H Z Isolation§ (parity (p y check)) H L Odd X PARITY ERR‡ OEB NA Even NA H A NA L A data to B bus and generate inverted parity NA = not applicable, NC = no change, X = don’t care Summation of high-level inputs includes PARITY along with Bi inputs. ‡ Output states shown assume ERR was previously high. § In this mode, ERR (when clocked) shows inverted parity of the A bus. † logic symbol¶ LE CLR OEA OEB A1 A2 A3 A4 A5 A6 A7 A8 13 11 1 14 2 3 Φ LE 10 ERR CLR OEA OEB PARITY 1 1 23 22 4 21 5 20 6 A Bus 19 B Bus 7 18 8 17 9 8 8 ¶ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages. 2 15 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 16 ERR PARITY B1 B2 B3 B4 B5 B6 B7 B8 SN54ABT853, SN74ABT853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS198G − FEBRUARY 1991 − REVISED OCTOBER 2010 logic diagram (positive logic) A1−A8 2−9 8x 8 23−16 8 B1−B8 EN 8x 8 EN OEB OEA 14 15 1 8 PARITY 8 MUX 1 1 2k 9 1 P 1 G1 LE CLR 10 13 ERR 11 Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages. ERROR-FLAG FUNCTION TABLE INPUTS CLR LE L L H L L H † H H INTERNAL TO DEVICE OUTPUT PRESTATE POINT P ERRN−1† L H X OUTPUT ERR L H L X L X L L H H H X X H L L H H X FUNCTION Pass Sample Clear Store The state of ERR before changes at CLR, LE, or point P POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ABT853, SN74ABT853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS198G − FEBRUARY 1991 − REVISED OCTOBER 2010 error-flag waveforms H OEB L H OEA L Even Bi + PARITY Odd H LE L H CLR L H ERR L Pass Store Sample Clear absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT853 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT853 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ABT853, SN74ABT853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS198G − FEBRUARY 1991 − REVISED OCTOBER 2010 recommended operating conditions (see Note 3) SN54ABT853 SN74ABT853 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage VI Input voltage VOH High-level output voltage ERR IOH High-level output current Except ERR IOL Low-level output current Δt/Δv Input transition rise or fall rate Δt/ΔVCC Power-up ramp rate 200 TA Operating free-air temperature −55 2 2 0.8 0 Outputs enabled UNIT V V 0.8 V VCC V 5.5 5.5 V −24 −32 mA 48 64 mA VCC 0 10 10 200 125 −40 ns/V μs/V 85 °C NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54ABT853, SN74ABT853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS198G − FEBRUARY 1991 − REVISED OCTOBER 2010 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH All outputs except ERR VOL TA = 25°C TEST CONDITIONS MIN II SN54ABT853 MAX MIN SN74ABT853 MIN II = −18 mA VCC = 4.5 V, IOH = −3 mA 2.5 2.5 2.5 VCC = 5 V, IOH = −3 mA 3 3 3 IOH = −24 mA 2 2 IOH = − 32 mA 2* VCC = 4 4.5 5V VCC = 4 4.5 5V −1.2 MAX VCC = 4.5 V, −1.2 −1.2 Control inputs A or B ports VCC = 4.5 V, VCC = 5 5.5 5V V, V V 0.55 IOL = 64 mA 0.55* 0.55 0.55 100 ERR UNIT VOH = 5.5 V VI = VCC or GND V mV 50 50 50 ±1 ±1 ±1 ±100 ±100 ±100 μA μA A IOZPU‡ VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OEA or OEB = X ±50 ±50 ±50 μA IOZPD‡ VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OEA or OEB = X ±50 ±50 ±50 μA IOZH§ VCC = 5.5 V, For control input affecting output under test VIH = 2.0 V or VIL = 0.8 V, VO = 2.7 V 10 10 10 μA IOZL§ VCC = 5.5 V, For control input affecting output under test VIH = 2.0 V or VIL = 0.8 V, VO = 0.5 V −10 −10 −10 μA Ioff VCC = 0, VI or VO ≤ 4.5 V ±100 μA ICEX VCC = 5.5 V, VO = 5.5 V Outputs high 50 μA IO¶ VCC = 5.5 V, VO = 2.5 V −200# mA VCC = 5.5 V, IO = 0, VI = VCC or GND Outputs high 250 μA VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND ICC A or B ports inp ts Data inputs ΔICC|| ±100 50 −50 −100 −200# 1 250 50 −50 −200# 450 −50 Outputs low 24 38 38 38 mA Outputs disabled 0.5 250 450 250 μA Outputs enabled 1.5 1.5 1.5 mA Outputs disabled 50 50 50 μA 1.5 1.5 1.5 mA Control inputs VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND Ci Control inputs VI = 2.5 V or 0.5 V 4.5 pF Cio A or B ports VO = 2.5 V or 0.5 V 10.5 pF * On products compliant to MIL-PRF-38535, this parameter does not apply. † All typical values are at V CC = 5 V. ‡ This parameter is characterized, but not production tested. § The parameters I OZH and IOZL include the input leakage current. ¶ Not more than one output should be tested at a time, and the duration of the test should not exceed one second. # This data sheet limit can vary among suppliers. || This is the increase in supply current for each input that is at the specified TTL voltage level rather than V CC or GND. 6 MAX 2 IOL = 24 mA Vhys IOH TYP† POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ABT853, SN74ABT853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS198G − FEBRUARY 1991 − REVISED OCTOBER 2010 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) VCC = 5 V, TA = 25°C MIN † tw Pulse duration tsu Setup time th Hold time LE high or low MAX SN54ABT853 MIN MAX SN74ABT853 MIN 3.5 3.5 3.5 4 4 4 9.4† 10.2 9.4† CLR before LE↓ 2 2 2 B or PARITY after LE↓ 0 0 0 CLR after LE↓ 3 3 3 CLR low B or PARITY before LE↓ UNIT MAX ns ns ns This data sheet limit can vary among suppliers. switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ † FROM (INPUT) TO (OUTPUT) A or B B or A A PARITY OEA or OEB PARITY CLR ERR LE ERR B or PARITY ERR OEA or o OEB A or B or PARITY OEA or OEB A or B or PARITY VCC = 5 V, TA = 25°C MIN TYP SN54ABT853 SN74ABT853 MAX MIN MAX MIN 1.2 4.8 1.2 6.4 1.2 5.3 1 4.8† 1 5.4 1 5.3† 2.1 9.5 2.1 13.3 2.1 11.2 2.5 9.7 2.5 11 2.5 11 1.8 8.5 1.8 13.6 1.8 10.5 2.3 8.6 2.3 11.7 2.3 10 1 5.5 1 6.3 1 6.2 1.8 5.1 1.8 6.1 1.8 6 1† 5.8 1† 6.7 1 6.6 2 UNIT MAX 10.1 2 11.8 2 11.7 2.2† 11.5 2.2† 12.9 2.2† 12.8 1 5.8† 1 8.8 1 6.7† 1.5† 5.8 1.5† 9.8 1.5† 6.7 1.8† 7.3 1.8† 9.5 1.8† 7.9 2.1† 7.2 2.1† 8.2 2.1† 8.1 ns ns ns ns ns ns ns ns This data sheet limit can vary among suppliers. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54ABT853, SN74ABT853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS198G − FEBRUARY 1991 − REVISED OCTOBER 2010 PARAMETER MEASUREMENT INFORMATION 7V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open LOAD CIRCUIT 3V Timing Input 1.5 V 0V tw tsu 3V 1.5 V Input 1.5 V 0V 3V Data Input 1.5 V VOLTAGE WAVEFORMS PULSE DURATION 1.5 V 1.5 V 0V tPHL tPLH 1.5 V Output 1.5 V VOH VOL VOH Output 1.5 V 0V 1.5 V VOL 3V Output Control 1.5 V 1.5 V 0V tPZL tPLZ Output Waveform 1 S1 at 7 V (see Note B) tPLH tPHL 1.5 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V Input th Output Waveform 2 S1 at Open (see Note B) 1.5 V tPZH VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 3.5 V VOL + 0.3 V tPHZ 1.5 V VOH − 0.3 V VOL VOH ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 5-Sep-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp ACTIVE LCCC FK 28 1 TBD Call TI Call TI 5962-9674601QKA ACTIVE CFP W 24 1 TBD Call TI Call TI 1 TBD Call TI Call TI TBD Call TI Call TI 5962-9674601QLA ACTIVE CDIP JT 24 SN74ABT853DBLE OBSOLETE SSOP DB 24 SN74ABT853DW ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT853DWE4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT853DWG4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT853DWR ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT853DWRE4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT853DWRG4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74ABT853NT ACTIVE PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74ABT853NTE4 ACTIVE PDIP NT 24 15 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN74ABT853PWLE OBSOLETE TSSOP PW 24 SNJ54ABT853FK ACTIVE LCCC FK 28 1 TBD SNJ54ABT853JT ACTIVE CDIP JT 24 1 TBD A42 N / A for Pkg Type SNJ54ABT853W ACTIVE CFP W 24 1 TBD A42 N / A for Pkg Type Call TI Samples (Requires Login) 5962-9674601Q3A TBD (3) Call TI POST-PLATE N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 5-Sep-2011 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54ABT853, SN74ABT853 : • Catalog: SN74ABT853 • Military: SN54ABT853 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Military - QML certified for Military and Defense Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74ABT853DWR Package Package Pins Type Drawing SOIC DW 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 10.75 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.7 2.7 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74ABT853DWR SOIC DW 24 2000 367.0 367.0 45.0 Pack Materials-Page 2 PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 5962-9674601Q3A ACTIVE LCCC FK 28 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 59629674601Q3A SNJ54ABT 853FK SN74ABT853DW ACTIVE SOIC DW 24 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ABT853 Samples SN74ABT853DWR ACTIVE SOIC DW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 ABT853 Samples SNJ54ABT853FK ACTIVE LCCC FK 28 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 59629674601Q3A SNJ54ABT 853FK (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of