SN74AC74D


  
    
   
 SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003 D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 10 ns at 5 V SN54AC74 . . . J OR W PACKAGE SN74AC74 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW) 1CLR 1D 1CLK 1PRE 1Q 1Q GND description/ordering information The ’AC74 devices are dual positive-edgetriggered D-type flip-flops. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at D can be changed without affecting the levels at the outputs. 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE 2Q 2Q 1D 1CLR NC VCC 2CLR SN54AC74 . . . FK PACKAGE (TOP VIEW) 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2D NC 2CLK NC 2PRE 1Q GND NC 2Q 2Q 1CLK NC 1PRE NC 1Q NC − No internal connection ORDERING INFORMATION PDIP − N SN74AC74N Tube SN74AC74D Tape and reel SN74AC74DR SOP − NS Tape and reel SN74AC74NSR AC74 SSOP − DB Tape and reel SN74AC74DBR AC74 Tube SN74AC74PW Tape and reel SN74AC74PWR CDIP − J Tube SNJ54AC74J SNJ54AC74J CFP − W Tube SNJ54AC74W SNJ54AC74W LCCC − FK Tube SNJ54AC74FK SNJ54AC74FK TSSOP − PW −55°C 125°C −55 C to 125 C TOP-SIDE MARKING Tube SOIC − D −40°C 85°C −40 C to 85 C ORDERABLE PART NUMBER PACKAGE† TA SN74AC74N AC74 AC74 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2003, Texas Instruments Incorporated     ! " #$%! "  &$'(#! )!%* )$#!" # ! "&%##!" &% !+% !%"  %," "!$%!" "!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)% !%"!/  (( &%!%"*  &)$#!" #&(! ! 0121 (( &%!%" % !%"!%) $(%"" !+%-"% !%)*  (( !+% &)$#!" &)$#! &#%""/ )%" ! %#%""(. #($)% !%"!/  (( &%!%"* POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 

  
    
   
 SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003 FUNCTION TABLE OUTPUTS INPUTS PRE CLR CLK D Q L H X X H L H L X X H H† L Q L L X X L H† H H ↑ H H H H ↑ L L H H H L X Q0 Q0 † This configuration is unstable; that is, it does not persist when either PRE or CLR returns to its inactive (high) level. logic diagram, each flip-flop (positive logic) PRE CLK C C C Q TG C C C C D TG TG TG C C C Q CLR 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

  
    
   
 SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) VCC VIH Supply voltage VCC = 3 V VCC = 4.5 V High-level input voltage VCC = 5.5 V VCC = 3 V VIL VI VO IOH IOL ∆t/∆v SN54AC74 SN74AC74 MIN MAX MIN MAX 2 6 2 6 2.1 2.1 3.15 3.15 3.85 3.85 VCC = 4.5 V VCC = 5.5 V Low-level input voltage Input voltage 0 Output voltage 0 High-level output current Low-level output current 0.9 1.35 1.35 1.65 1.65 0 0 VCC VCC VCC = 3 V VCC = 4.5 V −12 −12 −24 −24 VCC = 5.5 V VCC = 3 V −24 −24 12 12 VCC = 4.5 V VCC = 5.5 V 24 24 24 24 8 8 Input transition rise or fall rate V V 0.9 VCC VCC UNIT V V V mA mA ns/V TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 

  
    
   
 SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = −50 µA IOH = −12 mA VOH IOH = −24 mA TA = 25°C TYP MAX 3V 2.9 4.49 2.9 2.9 4.5 V 4.4 5.49 4.4 4.4 5.5 V 5.4 5.49 5.4 5.4 3V 2.56 2.4 2.46 4.5 V 3.86 3.7 3.76 5.5 V 4.86 4.7 4.76 MAX V 3V 0.002 0.1 0.1 0.1 IOL = 50 µA 4.5 V 0.001 0.1 0.1 0.1 5.5 V 0.001 0.1 0.1 0.1 3.85 3V 0.36 0.5 0.44 4.5 V 0.36 0.5 0.44 5.5 V 0.36 0.5 0.44 5.5 V VI = VCC or GND, VI = VCC or GND 1.65 5.5 V IO = 0 V 1.65 5.5 V VI = VCC or GND UNIT 3.85 Data pins ICC Ci MIN MAX 5.5 V IOL = 50 mA† IOL = 75 mA† Control pins SN74AC74 MIN 5.5 V IOL = 24 mA II SN54AC74 IOH = −50 mA† IOH = −75 mA† IOL = 12 mA VOL MIN 5.5 V ±0.1 ±1 ±1 ±0.1 ±1 ±1 2 40 20 5V 3 † Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms. A µA µA pF timing requirements over recommended operating free-air temperature range, VCC = 3.3 V " 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX fclock 4 Clock frequency tw Pulse duration tsu Setup time, data before CLK↑ th Hold time, data after CLK↑ SN54AC74 SN74AC74 MIN MIN 100 MAX 70 95 PRE or CLR low 5.5 8 7 CLK 5.5 8 7 Data 4 5 4.5 PRE or CLR inactive 0 0.5 0 0.5 0.5 0.5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT MHz ns ns ns 

  
    
   
 SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003 timing requirements over recommended operating free-air temperature range, VCC = 5 V"0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX fclock Clock frequency SN54AC74 SN74AC74 MIN MIN 140 tw Pulse duration tsu Setup time, data before CLK↑ th Hold time, data after CLK↑ MAX 95 MAX 125 PRE or CLR low 4.5 5.5 5 CLK 4.5 5.5 5 Data 3 4 3 PRE or CLR inactive 0 0.5 0 0.5 0.5 0.5 UNIT MHz ns ns ns switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V " 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL FROM (INPUT) TO (OUTPUT) PRE or CLR Q or Q CLK Q or Q TA = 25°C MIN TYP MAX SN54AC74 SN74AC74 MIN MAX MIN 70 MAX 100 125 3.5 8 12 1 13 2.5 95 13 4 10.5 12 1 14 3.5 13.5 4.5 8 13.5 1 17.5 4 16 3.5 8 14 1 13.5 3.5 14.5 UNIT MHz ns ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V " 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL FROM (INPUT) TO (OUTPUT) PRE or CLR Q or Q CLK Q or Q MIN TA = 25°C TYP MAX SN54AC74 SN74AC74 MIN MIN MAX 95 MAX 140 160 125 2.5 6 9 1 9.5 2 10 3 8 9.5 1 10.5 2.5 10.5 3.5 6 10 1 12 3 10.5 2.5 6 10 1 10 2.5 10.5 UNIT MHz ns ns operating characteristics, VCC = 3.3 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance CL = 50 pF, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 1 MHz TYP 45 UNIT pF 5 

  
    
   
 SCAS521F − AUGUST 1995 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 500 Ω From Output Under Test CL = 50 pF (see Note A) Open TEST S1 tPLH/tPHL Open 500 Ω tw LOAD CIRCUIT VCC VCC 50% VCC Input 0V VOLTAGE WAVEFORMS tPHL tPLH 50% VCC VOH 50% VCC VOL VCC 50% VCC Timing Input 0V tPLH tPHL Out-of-Phase Output 50% VCC 50% VCC 0V In-Phase Output 50% VCC Input 50% VCC VOH 50% VCC VOL th tsu Data Input VCC 50% VCC 50% VCC 0V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr v 2.5 ns, tf v 2.5 ns. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 26-Jul-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) 5962-88520012A ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 596288520012A SNJ54AC 74FK 5962-8852001CA ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8852001CA SNJ54AC74J Samples 5962-8852001DA ACTIVE CFP W 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8852001DA SNJ54AC74W Samples 5962-8852001VDA ACTIVE CFP W 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8852001VD A SNV54AC74W SN74AC74D ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC74 Samples SN74AC74DBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC74 Samples SN74AC74DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC74 Samples SN74AC74N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74AC74N Samples SN74AC74NE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74AC74N Samples SN74AC74NSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC74 Samples SN74AC74PW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC74 Samples SN74AC74PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC74 Samples SN74AC74PWRE4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC74 Samples SN74AC74PWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 AC74 Samples SNJ54AC74FK ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 596288520012A SNJ54AC 74FK SNJ54AC74J ACTIVE CDIP J 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8852001CA SNJ54AC74J Addendum-Page 1 Samples Samples Samples Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 26-Jul-2022 Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) (3) Device Marking Samples (4/5) (6) SNJ54AC74W ACTIVE CFP W 14 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 5962-8852001DA SNJ54AC74W (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of