SN54AHC245, SN74AHC245
SCLS230K – OCTOBER 1995 – REVISED DECEMBER 2022
SNx4AHC245 Octal Bus Transceivers With 3-State Outputs
1 Features
3 Description
•
•
The SNx4AHC245 octal bus transceivers are
designed for asynchronous two-way communication
between data buses. This part operates from 4.5 V to
5.5 V.
•
Operating range 2 V to 5.5 V VCC
Latch-up performance exceeds 250 mA
per JESD 17
On products compliant to MIL-PRF-38535,
all parameters are tested unless otherwise noted.
On all other products, production processing does
not necessarily include testing of all parameters.
2 Applications
•
•
•
•
•
•
Package Information(1)
PART NUMBER
SN54AHC245
Servers
PCs and notebooks
Network switches
Wearable health and fitness devices
Telecom infrastructures
Electronic points of sale
SN74AHC245
PACKAGE
BODY SIZE (NOM)
J (CDIP, 20)
24.20 mm × 6.92 mm
W (CFP, 20)
13.09 mm × 6.92 mm
FK (LCCC, 20)
8.89 mm × 8.89 mm
DB (SSOP, 20)
7.20 mm × 5.30 mm
DGV (TVSOP, 20)
5.00 mm × 4.40 mm
DW (SOIC, 20)
12.80 mm × 7.50 mm
N (PDIP, 20)
24.33 mm × 6.35 mm
PW (TSSOP, 20)
6.50 mm × 4.40 mm
DGS (VSSOP, 20)
(2)
5.10 mm × 3.00 mm
RKS (VQFN, 20)(2) 4.50 mm × 2.50 mm
(1)
(2)
For all available packages, see the orderable addendum at
the end of the data sheet.
Preview package
1
DIR
19
OE
A1
2
18
B1
To Seven Other Channels
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
SN54AHC245, SN74AHC245
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SCLS230K – OCTOBER 1995 – REVISED DECEMBER 2022
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 Handling Ratings.........................................................5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics, VCC = 3.3 V ± 0.3 V...........6
6.7 Switching Characteristics, VCC = 5 V ± 0.5 V..............7
6.8 Noise Characteristics.................................................. 7
6.9 Operating Characteristics........................................... 8
6.10 Typical Characteristics.............................................. 8
7 Parameter Measurement Information............................ 9
8 Detailed Description......................................................10
8.1 Overview................................................................... 10
8.2 Functional Block Diagram......................................... 10
8.3 Feature Description...................................................10
8.4 Device Functional Modes..........................................10
9 Application and Implementation.................................. 11
9.1 Application Information..............................................11
9.2 Typical Application.................................................... 11
10 Power Supply Recommendations..............................12
11 Layout........................................................................... 12
11.1 Layout Guidelines................................................... 12
11.2 Layout Example...................................................... 12
12 Device and Documentation Support..........................13
12.1 Receiving Notification of Documentation Updates..13
12.2 Support Resources................................................. 13
12.3 Trademarks............................................................. 13
12.4 Electrostatic Discharge Caution..............................13
12.5 Glossary..................................................................13
13 Mechanical, Packaging, and Orderable
Information.................................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision J (July 2014) to Revision K (December 2022)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Added the DGS and RKS package to the data sheet.........................................................................................1
Changes from Revision I (July 2003) to Revision J (July 2014)
Page
• Updated document to new TI data sheet format.................................................................................................1
• Removed Ordering Information table..................................................................................................................1
• Added Military Disclaimer to Features list...........................................................................................................1
• Added Applications. ........................................................................................................................................... 1
• Added Device Information table..........................................................................................................................1
• Added Handling Ratings table. .......................................................................................................................... 5
• Changed MAX ambient temperature to 125°C in Recommended Operating Conditions................................... 5
• Added Typical Characteristics............................................................................................................................ 8
• Added Application and Implementation section................................................................................................ 11
• Added Power Supply Recommendations and Layout sections........................................................................ 12
2
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SCLS230K – OCTOBER 1995 – REVISED DECEMBER 2022
5 Pin Configuration and Functions
DIR
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
OE
B1
B2
B3
B4
B5
B6
B7
B8
1
VCC
20
A1
2
19 OE
A2
3
18 B1
A3
4
17 B2
A4
5
16 B3
PAD
A5
6
15 B4
A6
7
14 B5
A7
8
13 B6
A8
9
12 B7
10
B8
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
B1
B2
B3
B4
B5
A8
GND
B8
B7
B6
A3
A4
A5
A6
A7
11
Figure 5-2. SN74AHC245 RKS Package, VQFN 20Pin (Top View)
A2
A1
DIR
VCC
Figure 5-1. SN54AHC245 J or W, SN74AHC245 DB,
DGV, DW, N, PW or DGS Package, CDIP, CFP,
SSOP, TVSOP, SOIC, PDIP, TSSOP, or VSSOP 20Pin (Top View)
GND
OE
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
Figure 5-3. SN54AHC245 FK Package, LCCC 20-Pin (Top View)
Table 5-1. Pin Functions
PIN
NAME
NO.
TYPE(1)
DESCRIPTION
DIR
1
I/O
Direction Pin
A1
2
I/O
A1 Input/Output
A2
3
I/O
Y4 Input/Output
A3
4
I/O
A2 Input/Output
A4
5
I/O
Y3 Input/Output
A5
6
I/O
A3 Input/Output
A6
7
I/O
Y2 Input/Output
A7
8
I/O
A4 Input/Output
A8
9
I/O
Y1 Input/Output
GND
10
—
Ground Pin
B8
11
I/O
A1 Input/Output
B7
12
I/O
Y4 Input/Output
B6
13
I/O
A2 Input/Output
B5
14
I/O
Y3 Input/Output
B4
15
I/O
A3 Input/Output
B
16
I/O
Y2 Input/Output
B2
17
I/O
A4 Input/Output
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Table 5-1. Pin Functions (continued)
PIN
NAME
TYPE(1)
DESCRIPTION
B2
18
I/O
Y1 Input/Output
B1
19
I/O
Output Enable
VCC
20
—
Power Pin
—
Thermal Pad(2)
Thermal pad
(1)
(2)
4
NO.
I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power
RKS package only.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage range
range(1)
Control inputs
MIN
MAX
–0.5
7
UNIT
V
–0.5
7
V
–0.5
VCC + 0.5
V
VI
Input voltage
VO
I/O, Output voltage range
IIK
Input clamp current
VI < 0
–20
mA
IOK
I/O, Output clamp current
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
±75
mA
Control inputs
Continuous current through VCC or GND
(1)
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 Handling Ratings
Tstg
Storage temperature range
V(ESD)
(1)
(2)
Electrostatic discharge
MIN
MAX
UNIT
°C
–65
150
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins(1)
0
1500
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins(2)
0
2000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
SN54AHC245
VCC
Supply voltage
VIH
High-level input voltage
MIN
MAX
MIN
MAX
2
5.5
2
5.5
VCC = 2 V
1.5
1.5
VCC = 3 V
2.1
2.1
VCC = 5.5 V
3.85
VCC = 2 V
VIL
Low-level input voltage
SN74AHC245
VCC = 5.5 V
V
V
3.85
0.5
VCC = 3 V
UNIT
0.5
0.9
0.9
1.65
1.65
V
VI
Input voltage
OE or DIR
0
5.5
0
5.5
V
VO
Output voltage
A or B
0
VCC
0
VCC
V
µA
IOH
High-level output current
VCC = 2 V
IOL
Low-level output current
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
–50
–50
VCC = 3.3 V ± 0.3 V
–4
–4
VCC = 5 V ± 0.5 V
–8
–8
VCC = 2 V
50
50
VCC = 3.3 V ± 0.3 V
4
4
VCC = 5 V ± 0.5 V
8
8
100
100
20
20
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
–55
125
–40
125
mA
µA
mA
ns/V
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
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6.4 Thermal Information
DB
THERMAL METRIC(1)
DGV
DW
N
NS
PW
RGY
RKS
DGS
UNIT
20 PINS
RθJA
Junction-to-ambient thermal
resistance
96.0
116.1
79.8
51.5
77.1
102.8
35.1
67.7
118.4
RθJC(top)
Junction-to-case (top) thermal
resistance
57.7
31.3
45.8
38.2
43.6
36.8
43.3
72.4
57.7
RθJB
Junction-to-board thermal resistance
51.2
57.6
47.4
32.4
44.6
53.8
12.9
40.4
73.1
ψJT
Junction-to-top characterization
parameter
19.4
1.0
18.5
24.6
17.2
2.5
0.9
10.3
5.7
ψJB
Junction-to-board characterization
parameter
50.8
56.9
47.0
32.3
44.2
53.3
12.9
40.4
72.7
RθJC(bot)
Junction-to-case (bottom) thermal
resistance
n/a
n/a
n/a
n/a
n/a
n/a
7.9
24.1
n/a
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SN74AHC245
MIN
2
1.9
1.9
2.9
2.9
4.5 V
4.4
4.5
4.4
4.4
IOH = –4 mA
3V
2.58
2.48
2.48
IOH = –8 mA
4.5 V
3.94
3.8
MAX
UNIT
V
3.8
2V
0.1
0.1
0.1
3V
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
IOL = 4 mA
3V
0.36
0.5
0.44
IOL = 8 mA
4.5 V
0.36
0.5
0.44
5.5 V
±0.1
±1
±1
0 V to 5.5 V
±0.1
±1(1)
±1
5.5 V
±0.25
±2.5
±2.5
µA
4
40
40
µA
10
pF
V I = VCC or GND
VI = VCC or GND,
IO = 0
5.5 V
Ci
OE or DIR
VI = VCC or GND
5V
2.5
Cio
A or B inputs
VI = VCC or GND
5V
4
(1)
(2)
MAX
3
VO = VCC or GND,
VI ( OE) = VIL or VIH
ICC
MIN
1.9
VOL
IOZ (2)
SN54AHC245
MAX
2.9
IOL = 50 µA
OE or DIR
TYP
3V
VOH
II
MIN
2V
IOH = –50 µA
A or B inputs
TA = 25°C
VCC
10
V
µA
pF
On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
The parameter IOZ includes the input leakage current.
6.6 Switching Characteristics, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
6
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A or B
B or A
CL = 15 pF
OE
A or B
CL = 15 pF
OE
A or B
CL = 15 pF
TA = 25°C
MIN
SN54AHC245
SN74AHC245
TYP
MAX
MIN
MAX
MIN
MAX
5.8(1)
8.4(1)
1(1)
10(1)
1
10
5.8(1)
8.4(1)
1(1)
10(1)
1
10
8.5(1)
13.2(1)
1(1)
15.5(1)
1
15.5
8.5(1)
13.2(1)
1(1)
15.5(1)
1
15.5
8.9(1)
12.5(1)
1(1)
15.5(1)
1
15.5
8.9(1)
12.5(1)
1(1)
15.5(1)
1
15.5
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UNIT
ns
ns
ns
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6.6 Switching Characteristics, VCC = 3.3 V ± 0.3 V (continued)
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A or B
B or A
CL = 50 pF
OE
A or B
CL = 50 pF
OE
A or B
CL = 50 pF
tsk(o)
(1)
(2)
TA = 25°C
MIN
SN54AHC245
SN74AHC245
TYP
MAX
MIN
MAX
MIN
MAX
8.3
11.9
1
13.5
1
13.5
8.3
11.9
1
13.5
1
13.5
11
16.7
1
19
1
19
11
16.7
1
19
1
19
11.5
15.8
1
18
1
18
11.5
15.8
1
18
1
18
1.5(2)
CL = 50 pF
UNIT
ns
ns
ns
1.5
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
On products compliant to MIL-PRF-38535, this parameter does not apply.
6.7 Switching Characteristics, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A or B
B or A
CL = 15 pF
OE
A or B
CL = 15 pF
OE
A or B
CL = 15 pF
A or B
B or A
CL = 50 pF
OE
A or B
CL = 50 pF
OE
A or B
CL = 50 pF
tsk(o)
(1)
(2)
TA = 25°C
MIN
SN54AHC245
SN74AHC245
TYP
MAX
MIN
MAX
MIN
MAX
4(1)
5.5(1)
1(1)
6.5(1)
1
6.5
4(1)
5.5(1)
1(1)
6.5(1)
1
6.5
5.8(1)
8.5(1)
1(1)
10(1)
1
10
5.8(1)
8.5(1)
1(1)
10(1)
1
10
5.6(1)
7.8(1)
1(1)
9.2(1)
1
9.2
5.6(1)
7.8(1)
1(1)
9.2(1)
1
9.2
5.5
7.5
1
8.5
1
8.5
5.5
7.5
1
8.5
1
8.5
7.3
10.6
1
12
1
12
7.3
10.6
1
12
1
12
7
9.7
1
11
1
11
7
9.7
1
11
1
11
CL = 50 pF
1(2)
UNIT
ns
ns
ns
ns
ns
ns
1
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
On products compliant to MIL-PRF-38535, this parameter does not apply.
6.8 Noise Characteristics
VCC = 5 V, CL = 50 pF, TA = 25°C (1)
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
0.9
V
VOL(V)
Quiet output, minimum dynamic VOL
–0.9
V
VOH(V)
Quiet output, minimum dynamic VOH
4.3
V
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
(1)
3.5
V
1.5
V
Characteristics are for surface-mount packages only.
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6.9 Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load
TYP
f = 1 MHz
14
UNIT
pF
6.10 Typical Characteristics
10
14
TPD in ns
12
8
6
TPD (ns)
TPD (ns)
10
4
8
6
4
2
2
TPD in ns
0
-100
0
-50
0
50
Temperature (qC)
100
0
1
D001
Figure 6-1. TPD vs Temperature at 3.3 V
8
150
2
3
VCC (V)
4
5
6
D002
Figure 6-2. TPD vs VCC at 25°C
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7 Parameter Measurement Information
RL = 1 kΩ
From Output
Under Test
Test
Point
From Output
Under Test
S1
VCC
Open
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
tw
tsu
VCC
Input
50% VCC
50% VCC
0V
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
50% VCC
Input
50% VCC
0V
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
Output
Waveform 1
S1 at VCC
(see Note B)
50% VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
50% VCC
0V
tPLZ
tPZL
≈VCC
50% VCC
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
tPZH
tPLH
VOH
50% VCC
VOL
VCC
Output
Control
50% VCC
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 7-1. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
These octal bus transceivers are designed for asynchronous two-way communication between data buses. The
control-function implementation minimizes external timing requirements. The SNx4AHC245 devices allow data
transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses
are effectively isolated. To ensure the high-impedance state during power up or power down, OE should be tied
to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability
of the driver.
8.2 Functional Block Diagram
1
DIR
19
OE
A1
2
18
B1
To Seven Other Channels
8.3 Feature Description
•
•
•
VCC is optimized at 5 V
Allows down voltage translation from 5 V to 3.3 V
– Inputs accept voltage levels up to 5.5 V
Slow edge rates minimize output ringing
8.4 Device Functional Modes
Table 8-1. Function Table
(Each Transceiver)
INPUTS
10
OPERATION
OE
DIR
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
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Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN54AHC245 SN74AHC245
SN54AHC245, SN74AHC245
www.ti.com
SCLS230K – OCTOBER 1995 – REVISED DECEMBER 2022
9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The SNx4AHC245A is a low-drive CMOS device that can be used for a multitude of bus interface type
applications where output ringing is a concern. The low drive and slow edge rates will minimize overshoot
and undershoot on the outputs. The inputs can accept voltages to 5.5 V at any valid VCC making it ideal for down
translation.
9.2 Typical Application
Regulated 5 V
Regulated 5 V or 3.3 V
OE
VCC
OE
DIR
A1
DIR
B1
µC
5 V LEDs, Relays,
or other system boards
A8
VCC
B8
3.3 V µC
5 V LEDs, Relays,
or other system
or other system boards
A1
B1
µC
A8
B8
boards
GND
GND
5 V LEDs, Relays,
or other system
boards
Figure 9-1. Typical Application Schematic
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. Outputs can be combined to
produce higher drive but the high drive will also create faster edges into light loads, so routing and load
conditions should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions
• Rise time and fall time specs: See (Δt/ΔV) in the Section 6.3 table.
• Specified high and low levels: See (VIH and VIL) in the Section 6.3 table.
• Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions
• Load currents should not exceed 25 mA per output and 75 mA total for the part.
• Outputs should not be pulled above VCC.
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Product Folder Links: SN54AHC245 SN74AHC245
11
SN54AHC245, SN74AHC245
www.ti.com
SCLS230K – OCTOBER 1995 – REVISED DECEMBER 2022
9.2.3 Application Curves
AC245
HC245
AHC245
Figure 9-2. Switching Characteristics Comparison
10 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the Section 6.3
table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended; if there are multiple VCC pins, then 0.01 μF or 0.022 μF is recommended for
each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF
and a 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple-bit logic devices, inputs should never float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not
be left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Figure 11-1 specifies the rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally they will be tied to
GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs,
unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the output section of the
part when asserted. This will not disable the input section of the IOs, so they cannot float when disabled.
11.2 Layout Example
Vcc
Unused Input
Input
Output
Unused Input
Output
Input
Figure 11-1. Layout Diagram
12
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Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN54AHC245 SN74AHC245
SN54AHC245, SN74AHC245
www.ti.com
SCLS230K – OCTOBER 1995 – REVISED DECEMBER 2022
12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN54AHC245 SN74AHC245
13
PACKAGE OPTION ADDENDUM
www.ti.com
9-Dec-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-9681801Q2A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629681801Q2A
SNJ54AHC
245FK
5962-9681801QRA
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9681801QR
A
SNJ54AHC245J
5962-9681801QSA
ACTIVE
CFP
W
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9681801QS
A
SNJ54AHC245W
5962-9681801VSA
ACTIVE
CFP
W
20
25
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9681801VS
A
SNV54AHC245W
PSN74AHC245RKSR
ACTIVE
VQFN
RKS
20
3000
TBD
Call TI
Call TI
-40 to 125
SN74AHC245DBR
ACTIVE
SSOP
DB
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA245
Samples
SN74AHC245DGVR
ACTIVE
TVSOP
DGV
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA245
Samples
SN74AHC245DW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC245
Samples
SN74AHC245DWR
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC245
Samples
SN74AHC245DWRE4
ACTIVE
SOIC
DW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC245
Samples
SN74AHC245N
ACTIVE
PDIP
N
20
20
RoHS &
Non-Green
NIPDAU
N / A for Pkg Type
-40 to 125
SN74AHC245N
Samples
SN74AHC245NSR
ACTIVE
SO
NS
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC245
Samples
SN74AHC245PW
ACTIVE
TSSOP
PW
20
70
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA245
Samples
SN74AHC245PWR
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
HA245
Samples
SN74AHC245PWRE4
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA245
Samples
SN74AHC245PWRG4
ACTIVE
TSSOP
PW
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA245
Samples
Addendum-Page 1
Samples
Samples
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
9-Dec-2022
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
Samples
(4/5)
(6)
SNJ54AHC245FK
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629681801Q2A
SNJ54AHC
245FK
SNJ54AHC245J
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9681801QR
A
SNJ54AHC245J
SNJ54AHC245W
ACTIVE
CFP
W
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9681801QS
A
SNJ54AHC245W
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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