SN74AHC595NSR


   
 

 
  

SCLS373I − MAY 1997 − REVISED JUNE 2004 QB QC QD QE QF QG QH GND description/ordering information The ’AHC595 devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage registers. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output for cascading. When the output-enable (OE) input is high, all outputs, except QH′, are in the high-impedance state. 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER OE RCLK SRCLK SRCLR QH′ QC QB SN54AHC595 . . . FK PACKAGE (TOP VIEW) 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 QH Both the shift-register clock (SRCLK) and storage-register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register. 4 SER OE NC RCLK SRCLK SRCLR QD QE NC QF QG NC VCC QA D SN54AHC595 . . . J OR W PACKAGE SN74AHC595 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW) Operating Range 2-V to 5.5-V VCC 8-Bit Serial-In, Parallel-Out Shift Shift Register Has Direct Clear Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) GND NC Q H′ D D D D NC − No internal connection ORDERING INFORMATION PDIP − N SN74AHC595N Tube SN74AHC595D Tape and reel SN74AHC595DR SOP − NS Tape and reel SN74AHC595NSR AHC595 SSOP − DB Tape and reel SN74AHC595DBR HA595 Tube SN74AHC595PW Tape and reel SN74AHC595PWR CDIP − J Tube SNJ54AHC959J SNJ54AHC595J CFP − W Tube SNJ54AHC595W SNJ54AHC595W LCCC − FK Tube SNJ54AHC595FK SNJ54AHC595FK TSSOP − PW −55°C 125°C −55 C to 125 C TOP-SIDE MARKING Tube SOIC − D −40°C 85°C −40 C to 85 C ORDERABLE PART NUMBER PACKAGE† TA SN74AHC595N AHC595 HA595 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright  2004, Texas Instruments Incorporated 


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SCLS373I − MAY 1997 − REVISED JUNE 2004 FUNCTION TABLE INPUTS 2 SER SRCLK X X X X X X L SRCLR FUNCTION RCLK OE X X H X X L Outputs QA−QH are disabled. Outputs QA−QH are enabled. L X X Shift register is cleared. ↑ H X X First stage of the shift register goes low. Other stages store the data of previous stage, respectively. H ↑ H X X First stage of the shift register goes high. Other stages store the data of previous stage, respectively. X X X ↑ X Shift-register data is stored into the storage register. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

   
 

 
  

SCLS373I − MAY 1997 − REVISED JUNE 2004 logic diagram (positive logic) OE RCLK SRCLR SRCLK SER 13 12 10 11 14 1D Q C1 R 3D C3 Q 15 2D Q C2 R 3D C3 Q 1 2D Q C2 R 3D C3 Q 2 2D Q C2 R 3D C3 Q 3 2D Q C2 R 3D C3 Q 4 2D Q C2 R 3D C3 Q 5 2D Q C2 R 3D C3 Q 6 2D Q C2 R 3D C3 Q 7 9 QA QB QC QD QE QF QG QH QH′ Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 

   
 

 
  

SCLS373I − MAY 1997 − REVISED JUNE 2004 timing diagram SRCLK SER RCLK SRCLR OE ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ QA QB QC QD QE QF QG QH QH′ ÎÎÎÎ ÎÎÎÎ NOTE: 4 implies that the output is in 3-State mode. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

   
 

 
  

SCLS373I − MAY 1997 − REVISED JUNE 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±75 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54AHC595 VCC VIH Supply voltage VCC = 2 V VCC = 3 V High-level input voltage VCC = 5.5 V VCC = 2 V VIL VI VO IOH ∆t/∆v MAX 2 5.5 1.5 Input voltage Output voltage VCC = 2 V VCC = 3.3 V ± 0.3 V High-level output current VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V VCC = 3.3 V ± 0.3 V Low-level output current Input transition rise or fall rate VCC = 5 V ± 0.5 V MIN MAX 2 5.5 UNIT V 1.5 2.1 2.1 3.85 3.85 0.5 VCC = 3 V VCC = 5.5 V Low-level input voltage VCC = 5 V ± 0.5 V VCC = 2 V IOL MIN SN74AHC595 V 0.5 0.9 0.9 1.65 1.65 V 0 5.5 0 5.5 V 0 VCC −50 0 VCC −50 mA −4 −4 −8 −8 50 50 4 4 8 8 100 100 20 20 V mA mA mA ns/V TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.  2 &(!)$'!& "!&"%)& *)!#" & % (!)$'3% !) %1& *'% !( %3%,!*$%&- ')'"%)" '' '& !%) *%"("'!& ')% %1& 1!',- %.' &)#$%& )%%)3% % )1 ! "'&1% !) "!&&#% %% *)!#" /!# &!"%- POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 

   
 

 
  

SCLS373I − MAY 1997 − REVISED JUNE 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) VCC MIN TA = 25°C TYP MAX 2V 1.9 2 1.9 1.9 3V 2.9 3 2.9 2.9 4.5 V 4.4 4.5 4.4 4.4 IOH = −4 mA 3V 2.58 2.48 2.48 IOH = −8 mA 4.5 V 3.94 PARAMETER TEST CONDITIONS IOH = −50 mA VOH IOL = 50 mA VOL IOZ ICC Ci MAX 3.8 SN74AHC595 MIN MAX UNIT V 3.8 2V 0.1 0.1 0.1 3V 0.1 0.1 0.1 0.1 0.1 0.1 3V 0.36 0.5 0.44 V 4.5 V 0.36 0.5 0.44 0 V to 5.5 V ±0.1 ±1* ±1 mA QA−QH 5.5 V ±0.25 ±2.5 ±2.5 mA IO = 0 5.5 V 4 40 40 mA 10 pF IOL = 8 mA VI = 5.5 V or GND VI = VCC or GND, VO = VCC or GND, OE = VIH or VIL VI = VCC or GND, MIN 4.5 V IOL = 4 mA II SN54AHC595 VI = VCC or GND VO = VCC or GND 5V 3 10 Co 5V 5.5 * On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V. pF timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX tw Pulse duration MAX MIN 5 5 5 RCLK high or low 5 5 5 5 5 5 3.5 3.5 3.5 SRCLK↑ before RCLK↑† 8 8.5 8.5 SRCLR low before RCLK↑ 8 9 9 SRCLR high (inactive) before SRCLK↑ 3 3 3 SER before SRCLK↑ Setup time MIN SN74AHC595 SRCLK high or low SRCLR low tsu SN54AHC595 MAX UNIT ns ns th Hold time SER after SRCLK↑ 1.5 1.5 1.5 ns † This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register.  2 &(!)$'!& "!&"%)& *)!#" & % (!)$'3% !) %1& *'% !( %3%,!*$%&- ')'"%)" '' '& !%) *%"("'!& ')% %1& 1!',- %.' &)#$%& )%%)3% % )1 ! "'&1% !) "!&&#% %% *)!#" /!# &!"%- 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 

   
 

 
  

SCLS373I − MAY 1997 − REVISED JUNE 2004 timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX tw tsu Pulse duration Setup time SN54AHC595 MIN MAX SN74AHC595 MIN SRCLK high or low 5 5 5 RCLK high or low 5 5 5 SRCLR low 5 5 5 SER before SRCLK↑ 3 3 3 SRCLK↑ before RCLK↑† 5 5 5 SRCLR low before RCLK↑ 5 5 5 2.5 2.5 2.5 SRCLR high (inactive) before SRCLK↑ MAX UNIT ns ns th Hold time SER after SRCLK↑ 2 2 2 ns † This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register. switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax TA = 25°C TYP MAX SN54AHC595 SN74AHC595 LOAD CAPACITANCE MIN CL = 15 pF 80* 120* 70* 70 CL = 50 pF 55 105 50 50 tPLH tPHL RCLK QA−QH CL = 15 pF tPLH tPHL SRCLK QH′ H CL = 15 pF tPHL SRCLR QH′ tPZH tPZL OE tPLH tPHL MIN MAX MIN MAX UNIT MHz 6* 11.9* 1* 13.5* 1 13.5 6* 11.9* 1* 13.5* 1 13.5 6.6* 13* 1* 15* 1 15 6.6* 13* 1* 15* 1 15 CL = 15 pF 6.2* 12.8* 1* 13.7* 1 13.7 6* 11.5* 1* 13.5* 1 13.5 QA−QH CL = 15 pF 7.8* 11.5* 1* 13.5* 1 13.5 7.9 15.4 1 17 1 17 RCLK QA−QH CL = 50 pF 7.9 15.4 1 17 1 17 tPLH tPHL 9.2 16.5 1 18.5 1 18.5 SRCLK QH′ H CL = 50 pF 9.2 16.5 1 18.5 1 18.5 tPHL SRCLR QH′ CL = 50 pF 9 16.3 1 17.2 1 17.2 tPZH tPZL 7.8 15 1 17 1 17 OE QA−QH CL = 50 pF 9.6 15 1 17 1 17 tPHZ tPLZ OE QA−QH CL = 50 pF 8.1 15.7 1 16.2 1 16.2 9.3 15.7 1 16.2 1 16.2 ns ns ns ns ns ns ns ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested.  2 &(!)$'!& "!&"%)& *)!#" & % (!)$'3% !) %1& *'% !( %3%,!*$%&- ')'"%)" '' '& !%) *%"("'!& ')% %1& 1!',- %.' &)#$%& )%%)3% % )1 ! "'&1% !) "!&&#% %% *)!#" /!# &!"%- POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 

   
 

 
  

SCLS373I − MAY 1997 − REVISED JUNE 2004 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) TA = 25°C TYP MAX SN54AHC595 SN74AHC595 LOAD CAPACITANCE MIN CL = 15 pF 135* 170* 115* 115 CL = 50 pF 95 140 85 85 fmax tPLH tPHL RCLK QA−QH CL = 15 pF tPLH tPHL SRCLK QH′ H CL = 15 pF tPHL SRCLR QH′ CL = 15 pF tPZH tPZL OE QA−QH CL = 15 pF tPLH tPHL RCLK QA−QH CL = 50 pF tPLH tPHL SRCLK QH′ H CL = 50 pF tPHL SRCLR QH′ CL = 50 pF tPZH tPZL OE QA−QH CL = 50 pF tPHZ tPLZ OE QA−QH CL = 50 pF MIN MAX MIN MAX UNIT MHz 4.3* 7.4* 1* 8.5* 1 8.5 4.3* 7.4* 1* 8.5* 1 8.5 4.5* 8.2* 1* 9.4* 1 9.4 4.5* 8.2* 1* 9.4* 1 9.4 4.5* 8* 1* 9.1* 1 9.1 4.3* 8.6* 1* 10* 1 10 5.4* 8.6* 1* 10* 1 10 5.6 9.4 1 10.5 1 10.5 5.6 9.4 1 10.5 1 10.5 6.4 10.2 1 11.4 1 11.4 6.4 10.2 1 11.4 1 11.4 6.4 10 1 11.1 1 11.1 5.7 10.6 1 12 1 12 6.8 10.6 1 12 1 12 3.5 10.3 1 11 1 11 3.4 10.3 1 11 1 11 ns ns ns ns ns ns ns ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load,  2 &(!)$'!& "!&"%)& *)!#" & % (!)$'3% !) %1& *'% !( %3%,!*$%&- ')'"%)" '' '& !%) *%"("'!& ')% %1& 1!',- %.' &)#$%& )%%)3% % )1 ! "'&1% !) "!&&#% %% *)!#" /!# &!"%- 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 1 MHz TYP UNIT 25.2 pF 

   
 

 
  

SCLS373I − MAY 1997 − REVISED JUNE 2004 PARAMETER MEASUREMENT INFORMATION From Output Under Test RL = 1 kΩ From Output Under Test Test Point S1 VCC Open TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input tw tsu VCC Input 50% VCC 50% VCC 0V th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC 50% VCC Input 50% VCC 0V tPLH In-Phase Output tPHL 50% VCC tPHL Out-of-Phase Output VOH 50% VCC VOL Output Waveform 1 S1 at VCC (see Note B) 50% VCC VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 50% VCC 50% VCC 0V tPZL tPLZ ≈VCC 50% VCC tPZH tPLH VOH 50% VCC VOL VCC Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 50% VCC VOH − 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time, with one input transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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