SN74BCT374
SCBS019D – SEPTEMBER 1988 – REVISED SN74BCT374
FEBRUARY 2021
SCBS019D – SEPTEMBER 1988 – REVISED FEBRUARY 2021
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SNx4BCT374 Octal Edge-Triggered D-Type Latches With 3-State Outputs
1 Features
3 Description
•
•
The SNx4BCT374 devices contain eight channels of
D-type flip-flops with a shared clock (CLK) and output
enable (OE) pin.
•
•
•
Operating Voltage Range of 4.5 V to 5.5 V
BiCMOS Design Significantly Reduces ICCZ Over
TTL Designs
Full Parallel Access for Loading
Buffered Control Inputs
3-State Outputs Drive Bus Lines or Buffer Memory
Address Registers
Device Information (1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SN74BCT374N
PDIP (20)
25.40 mm × 6.35 mm
SN74BCT374DW
SOIC (20)
12.80 mm × 7.50 mm
2 Applications
SN74BCT374NS
SOP (20)
12.60 mm × 5.30 mm
•
•
•
•
SN74BCT374DB
SSOP (20)
7.20 mm × 5.30 mm
SN54BCT374J
CDIP (20)
26.92 mm × 6.92 mm
SN54BCT374W
CFP (20)
13.72 mm × 6.92 mm
SN54BCT374FK
LCCC (20)
8.89 mm × 8.89 mm
Buffer Registers
I/O Ports
Bus Drivers
Working Registers
(1)
For all available packages, see the orderable addendum at
the end of the data sheet.
Shared Control Logic
OE
CLK
xD
D
Q
xQ
One of Eight D-Type Flip-Flops
Functional Block Diagram
An©IMPORTANT
NOTICEIncorporated
at the end of this data sheet addresses availability, warranty, changes, use in
safety-critical
applications,
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2021 Texas Instruments
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intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings (1) ................................... 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions (1) ................... 4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Timing Requirements.................................................. 6
6.7 Switching Characteristics............................................6
6.8 Typical Characteristics................................................ 6
7 Parameter Measurement Information............................ 7
8 Detailed Description........................................................8
8.1 Overview..................................................................... 8
8.2 Functional Block Diagram........................................... 8
8.3 Feature Description.....................................................8
8.4 Device Functional Modes............................................9
9 Application and Implementation.................................. 10
9.1 Application Information............................................. 10
9.2 Typical Application.................................................... 10
10 Power Supply Recommendations..............................12
11 Layout........................................................................... 12
11.1 Layout Guidelines................................................... 12
11.2 Layout Example...................................................... 12
12 Device and Documentation Support..........................13
12.1 Documentation Support.......................................... 13
12.2 Receiving Notification of Documentation Updates..13
12.3 Support Resources................................................. 13
12.4 Trademarks............................................................. 13
12.5 Electrostatic Discharge Caution..............................13
12.6 Glossary..................................................................13
13 Mechanical, Packaging, and Orderable
Information.................................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (March 2003) to Revision D (February 2021)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Added new applications to the Applications section........................................................................................... 1
• Removed Ordering Information and Function tables from the Description section............................................ 1
• Added the Device Information table to the Description section.......................................................................... 1
• Moved package thermal impedance, ΘJA for the DW, N, and NS packages to Section 6.4 ..............................4
• Added ESD Ratings section............................................................................................................................... 4
• Added Thermal Information section....................................................................................................................5
• Changed IOS(min) value From: –100 mA To: –50 mA ........................................................................................5
• Added Timing Requirements, Switching Characteristics, and Typical Characteristics sections......................... 6
• Added Detailed Description section....................................................................................................................8
• Added Application and Implementation section................................................................................................10
• Added Power Supply Recommendations and Layout sections........................................................................ 12
Changes from Revision B (April 1994) to Revision C (March 2003)
Page
• Added Ordering Information table to the Description section............................................................................. 1
• Added package thermal impedance, ΘJA for the DW, N, and NS packages...................................................... 4
Changes from Revision A (November 1993) to Revision B (April 1994)
Page
• First public release of production data sheet...................................................................................................... 1
2
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5 Pin Configuration and Functions
8Q
1D
3
18
8D
2D
2Q
4
17
2D
4
8D
5
16
7D
7Q
2Q
5
17
7D
3Q
6
15
6Q
3Q
6
16
7Q
7
8
9
10
14
13
12
11
6D
5D
5Q
CLK
3D
7
15
6Q
4D
8
14
9 10 11 12 13
6D
Figure 5-1. DB, DW, N, NS, J, or W Package
20-Pin SSOP, SOIC, PDIP, SO, CDIP, or CFP
Top View
5D
8Q
20 19
18
5Q
1
CLK
2
4Q
3
GND
3D
4D
4Q
GND
VCC
VCC
19
OE
20
2
1Q
1
1Q
1D
OE
Figure 5-2. FK Package
20-Pin LCCC
Transparent Top View
Table 5-1. Pin Functions
PIN
NAME
NO.
I/O(1)
DESCRIPTION
OE
1
I
Output enable, active low
1Q
2
O
Channel 1 output
1D
3
I
Channel 1 input
2D
4
I
Channel 2 input
2Q
5
O
Channel 2 output
3Q
6
O
Channel 3 output
3D
7
I
Channel 3 input
4D
8
I
Channel 4 input
4Q
9
O
Channel 4 output
GND
10
G
Ground
CLK
11
I
Clock, rising edge triggered
5Q
12
O
Channel 5 output
5D
13
I
Channel 5 input
6D
14
I
Channel 6 input
6Q
15
O
Channel 6 output
7Q
16
O
Channel 7 output
7D
17
I
Channel 7 input
8D
18
I
Channel 8 input
8Q
19
O
Channel 8 output
VCC
20
P
Positive supply
(1)
I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.
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6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
Supply voltage range
–0.5
7
range(2)
UNIT
V
VI
Input voltage
–0.5
7
V
VO
Voltage range applied to any output in the disabled or power-off state
–0.5
5.5
V
VO
Voltage range applied to any output in the high state
–0.5
VCC
V
IIK
Input clamp current
–30
mA
IOL
Current into any output in the low state
Tstg
Storage temperature range(3)
(1)
(2)
(3)
SN54BCT374
96
SN74BCT374
128
–65
mA
150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The negative input voltage rating may be exceeded if the input clamp current rating is observed.
Long-term high-temperature storage and extended use at maximum recommended operating conditions or both may result in a
reduction of overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging.
6.2 ESD Ratings
VALUE
V (ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-0011
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C1012
V
±1000
6.3 Recommended Operating Conditions (1)
Operating free-air temperature (TA)
–55°C to 125°C(2)
MIN
VCC Supply voltage
VIH High-level input voltage
NOM
4.5
5
0°C to 70°C(3)
MAX
5.5
2
MIN
NOM
4.5
UNIT
MAX
5
5.5
V
0.8
V
2
V
VIL
Low-level input voltage
0.8
IIK
Input clamp current
–18
–18
mA
–2
–15
mA
64
mA
70
°C
IOH
IOL
Low-level output current
TA
Operating free-air temperature
(1)
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs.
Applies to SN54BCT374 devices only
Applies to SN74BCT374 devices only
(2)
(3)
4
48
–55
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6.4 Thermal Information
SN74BCT374
DB
(SSOP)
THERMAL METRIC(1)
DW
(SOIC)
N (PDIP) NS (SO)
UNIT
20 PINS 20 PINS 20 PINS 20 PINS
R θJA
Junction-to-ambient thermal resistance
84.4
73.4
59.7
71.2
°C/W
R θJB
Junction-to-board thermal resistance
40.1
41.9
40.6
36.2
°C/W
ψ JT
Junction-to-top characterization parameter
6.2
14.6
24.9
7.6
°C/W
ψ JB
Junction-to-board characterization parameter
39.5
41.4
40.3
35.9
°C/W
36.8
38.8
50.0
34.3
°C/W
R θJC(top) Junction-to-case (top) thermal resistance
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
Operating free-air temperature (TA)
PARAMETER
VIK
TEST CONDITIONS
–55°C to 125°C(3)
MIN
TYP(1)
2.4
3.3
2
3.2
VCC = 4.5 V, II = –18 mA
VCC = 4.5 V
IOH = –12 mA
VCC = 4.5 V
IOL = 48 mA
0.38
UNIT
MAX
–1.2
2.4
3.3
2
3.1
V
V
IOH = –15 mA
VOL
TYP(1)
MAX MIN
–1.2
IOH = –3 mA
VOH
0°C to 70°C(4)
0.55
IOL = 64 mA
0.42
0.55
V
II
VCC = 5.5 V, VI = 5.5 V
0.4
0.4
mA
IIH
VCC = 5.5 V, VI = 2.7 V
20
20
μA
IIL
VCC = 5.5 V, VI = 0.5 V
IOS (2)
VCC = 5.5 V, VO = 0 V
–0.6
–50
–225
–50
–0.6
mA
–225
mA
μA
IOZH
VCC = 5.5 V, VO = 2.7 V
50
50
IOZL
VCC = 5.5 V, VO = 0.5 V
–50
–50
μA
ICCL
VCC = 5.5 V
37
60
37
60
mA
ICCH
VCC = 5.5 V
2
5
2
5
mA
ICCZ
VCC = 5.5 V
5
8
5
8
mA
Ci
VCC = 5 V, VI = 2.5 V or 0.5 V
6
6
pF
Co
VCC = 5 V, VO = 2.5 V or 0.5 V
10
10
pF
(1)
(2)
(3)
(4)
All typical values are at VCC = 5 V, TA = 25°C.
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
Applies to SN54BCT374 devices only
Applies to SN74BCT374 devices only
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6.6 Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted)
Operating free-air temperature (TA)
25°C(1)
PARAMETER
MIN
fclock
Clock frequency
tw
Pulse duration
–55°C to 125°C(2)
MAX
MIN
MAX
70
CLK high
0°C to 70°C(3)
MIN
UNIT
MAX
70
70
MHz
7
8
7
ns
tsu
Setup time before CLK ↑
Data high or low
6.5
6.5
6.5
ns
th
Hold time after CLK ↑
Data high or low
0
0
0
ns
(1)
(2)
(3)
VCC = 5 V, TA = 25°C, applies to all SN54BCT374 and SN74BCT374 devices
Applies to SN54BCT374 devices only
Applies to SN74BCT374 devices only
6.7 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
FROM
(INPUT)
Operating free-air temperature (TA)
TO
(OUTPUT)
25°C(1)
MIN
TYP
–55°C to 125°C(2) (3)
MAX
MIN
0°C to 70°C(2) (4)
MAX
fmax
70
2
7.2
9.1
2
11.6 2
10.6
2
7.1
8.8
2
10.6 2
10
1
8.3
10.1
1
12.7 1
12.3
1
8.6
10.6
1
13 1
12.7
1
4.7
6.3
1
7.1 1
6.8
1
4.8
6.3
1
7.5 1
6.8
tPZH
tPZL
tPHZ
tPLZ
(1)
(2)
(3)
(4)
CLK
Q
OE
Q
OE
Q
UNIT
MAX
tPLH
tPHL
70
MIN
70
MHz
ns
ns
ns
VCC = 5 V, CL = 50 pF, R1 = 500 Ω, R2 = 500 Ω, TA = 25°C, applies to all SN54BCT374 and SN74BCT374 devices
VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 Ω, R2 = 500 Ω
Applies to SN54BCT374 devices only
Applies to SN74BCT374 devices only
6.8 Typical Characteristics
TA = 25°C
Figure 6-1. Typical output voltage versus output current for BCT family drivers
6
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7 Parameter Measurement Information
All parameters and waveforms are not applicable to all devices.
7 V (tPZL, tPZL, O.C.)
S1(B)
Test
Point
From Output
Under Test
Open
(all others)
CL(A)
R1
R1
Test
Point
From Output
Under Test
CL(A)
A. CL includes probe and jig capacitance.
R2
Figure 7-2. Load circuit for
push-pull outputs
RL = R1 = R2
A. CL includes probe and jig capacitance.
B. When measuring propagation delay times of 3-state outputs,
switch S1 is open.
Figure 7-1. Load circuit for
3-state and open-collector outputs
3V
(A)
Timing Input
1.5 V
0V
1.5 V
0V
tw
3V
Data Input
1.5 V
High-Level
Pulse(A)
th
tsu
(A)
3V
1.5 V
3V
Low-Level
Pulse
1.5 V
1.5 V
1.5 V
0V
0V
A. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 10 MHz, tr = tf ≤ 2.5 ns, duty cycle = 50%.
A. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 10 MHz, tr = tf ≤ 2.5 ns, duty cycle = 50%.
Figure 7-4. Voltage waveforms
Pulse duration
Figure 7-3. Voltage waveforms
Setup and hold times
3V
1.5 V
1.5 V
Input(B)
1.5 V
1.5 V
0V
0V
tPLZ
VOH
1.5 V
In-Phase
Output(A)
tPZL
tPHL
tPLH
Waveform 1
1.5 V
3.5 V
(A)(B)
1.5 V
VOL
tPHL
Out-of-Phase
Output(A)
3V
Output Control
(low-level enable)
tPLH
tPHZ
tPZH
VOL
0.3 V
VOH
1.5 V
VOH
1.5 V
VOL
Waveform 2(A)(B)
1.5 V
0.3 V
0V
A. The outputs are measured one at a time with one transition per
A. The outputs are measured one at a time with one transition per
measurement.
measurement.
B. All input pulses are supplied by generators having the following B. Waveform 1 is for an output with internal conditions such that
characteristics: PRR ≤ 10 MHz, tr = tf ≤ 2.5 ns, duty cycle = 50%.
the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that
Figure 7-5. Voltage waveforms
the output is high except when disabled by the output control.
Propagation delay times
Figure 7-6. Voltage waveforms
Enable and disable times, 3-state outputs
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8 Detailed Description
8.1 Overview
These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively lowimpedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers.
The eight flip-flops of the SNx4BCT374 devices are edge-triggered D-type flip-flops. On the positive transition of
the clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without
need for interface or pullup components. The output-enable (OE) input does not affect internal operations of the
flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
8.2 Functional Block Diagram
Shared Control Logic
OE
CLK
xD
D
Q
xQ
One of Eight D-Type Flip-Flops
8.3 Feature Description
8.3.1 Bipolar Push-Pull Outputs
This device includes bipolar push-pull outputs. The drive capability of this device may create fast edges into light
loads, so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this
device are capable of driving larger currents than the device can sustain without being damaged. It is important
for the output power of the device to be limited to avoid damage due to overcurrent. The electrical and thermal
limits defined in the Absolute Maximum Ratings must be followed at all times.
Unused bipolar push-pull outputs should be left disconnected.
8.3.2 Standard CMOS Inputs
This device includes standard CMOS inputs. Standard CMOS inputs are high impedance and are typically
modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics. The worst case
resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the
maximum input leakage current, given in the Electrical Characteristics, using Ohm's law (R = V ÷ I).
Standard CMOS inputs require that input signals transition between valid logic states quickly, as defined by the
input transition time or rate in the Recommended Operating Conditions table. Failing to meet this specification
will result in excessive power consumption and could cause oscillations. More details can be found in
Implications of Slow or Floating CMOS Inputs.
Do not leave standard CMOS inputs floating at any time during operation. Unused inputs must be terminated at
VCC or GND. If a system will not be actively driving an input at all times, a pull-up or pull-down resistor can be
added to provide a valid input voltage during these times. The resistor value will depend on multiple factors,
however a 10-kΩ resistor is recommended and will typically meet all requirements.
8
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8.3.3 Clamp Diode Structure
The inputs and outputs to this device have negative clamping diodes only as depicted in Figure 8-1.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to
the device. The input and output voltage ratings may be exceeded if the input and output clampcurrent ratings are observed.
Device
VCC
Logic
Input
-IIK
Output
-IOK
GND
Figure 8-1. Electrical Placement of Clamping Diodes for Each Input and Output
8.4 Device Functional Modes
The Function Table below lists the functional modes of the SNx4BCT374.
Table 8-1. Function Table
INPUTS(1)
(1)
(2)
OUTPUT(2)
OE
CLK
D
Q
L
↑
H
H
L
↑
L
L
L
H or L
X
Q0
H
X
X
Z
L = Low input, H = High input, ↑ = Low to high transition, X = Do not care.
L = Low output, H = High output, Q0 = Previous state, Z = High impedance.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The SNx4BCT374 contains multiple D-type flip-flops that are operated by the same clock. By connecting multiple
channels together in series, a shift register can be formed. This produces a delay of a specific number of clock
cycles for incoming data. The application schematic shown below gives an example of using three channels of
the SNx4BCT374 to produce a delay of three clock cycles.
9.2 Typical Application
9.2.1 Application
VCC
VCC
0.1…F
Data
Source
Data
Destination
Clock
Source
1D
1Q
2D
2Q
3D
3Q
4Q
5Q
6Q
7Q
8Q
OE
4D
5D
6D
7D
CLK 8D
GND
Figure 9-1. Typical application block diagram
9.2.2 Design Requirements
9.2.2.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics.
The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all
outputs of the SNx4BCT374 plus the maximum static supply current, ICC, listed in Electrical Characteristics and
any transient current required for switching. The logic device can only source as much current as is provided by
the positive supply source.
The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the
SNx4BCT374 plus the maximum supply current, ICC, listed in Electrical Characteristics, and any transient current
required for switching. The logic device can only sink as much current as can be sunk into its ground connection.
The SNx4BCT374 can drive a load with a total capacitance less than or equal to 50 pF while still meeting all of
the datasheet specifications. Larger capacitive loads can be applied, however it is not recommended to exceed
50 pF.
10
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SCBS019D – SEPTEMBER 1988 – REVISED FEBRUARY 2021
The SNx4BCT374 can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage and
current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the high state, the
output voltage in the equation is defined as the difference between the measured output voltage and the supply
voltage at the VCC pin.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
9.2.2.2 Output Considerations
The positive supply voltage is used to produce the output high voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. The ground
voltage is used to produce the output low voltage. Sinking current into the output will increase the output voltage
as specified by the VOL specification in the Electrical Characteristics.
Push-pull bipolar outputs should never be connected directly together. This can cause excessive current and
damage to the device.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to Feature Description section for additional information regarding the outputs for this device.
9.2.2.3 Input Considerations
Input signals must cross VIL(max) to be considered a logic low, and VIH(min) to be considered a logic high. Do not
exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. These can be directly connected if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of high, and a pull-down resistor is used
for a default state of low. The resistor size is limited by drive current of the controller, leakage current into the
SNx4BCT374, as specified in the Electrical Characteristics, and the desired input transition rate. A 10-kΩ
resistor value is often used due to these factors.
The SNx4BCT374 has CMOS inputs and thus requires fast input transitions to operate correctly. Slow input
transitions can cause oscillations, additional power consumption, and reduction in device reliability.
Refer to the Feature Description section for additional information regarding the inputs for this device.
9.2.3 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
SNx4BCT374 and electrically close to both the VCC and GND pins. An example layout is shown in the Layout
section.
2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit, however it will ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the SNx4BCT374
to the receiving device(s).
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in megaohms; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation.
5. This device includes D-type flip-flop circuits. The output of these circuits is unknown at system startup. Data
must be clocked into each D-type flip-flop to initialize it into a known state.
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11
SN74BCT374
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SCBS019D – SEPTEMBER 1988 – REVISED FEBRUARY 2021
9.2.4 Application Curves
VCC
CLK
1D
1Q
2Q
3Q
Figure 9-2. Application timing diagram
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in
given example layout image.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
11.2 Layout Example
GND VCC
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
Unused input
tied to GND
Avoid 90°
corners for
signal lines
Bypass capacitor
placed close to the
device
0.1 F
OE
1
20
VCC
1Q
2
19
8Q Unused output
1D
3
Unused input
tied to VCC 18
2D
2Q
4
17
5
16
7D
7Q
3Q
6
15
6Q
7
8
9
10
14
13
12
11
6D
5D
5Q
CLK
3D
4D
4Q
GND
left floating
8D
Figure 11-1. Example layout for the SN74BCT374.
12
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Product Folder Links: SN74BCT374
SN74BCT374
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SCBS019D – SEPTEMBER 1988 – REVISED FEBRUARY 2021
12 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
•
•
•
•
Texas Instruments, Designing With Logic application report
Texas Instruments, Input and Output Characteristics of Digital Integrated Circuits application report
Texas Instruments, Implications of Slow or Floating CMOS Inputs application report
Texas Instruments, Understanding and Interpreting Standard-Logic Data Sheets application report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: SN74BCT374
13
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
5962-9051601M2A
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629051601M2A
SNJ54BCT
374FK
5962-9051601MRA
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9051601MR
A
SNJ54BCT374J
5962-9051601MSA
ACTIVE
CFP
W
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9051601MS
A
SNJ54BCT374W
SN74BCT374DW
ACTIVE
SOIC
DW
20
25
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
BCT374
Samples
SN74BCT374N
ACTIVE
PDIP
N
20
20
RoHS &
Non-Green
NIPDAU
N / A for Pkg Type
0 to 70
SN74BCT374N
Samples
SN74BCT374NSR
ACTIVE
SO
NS
20
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
0 to 70
BCT374
Samples
SNJ54BCT374FK
ACTIVE
LCCC
FK
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
59629051601M2A
SNJ54BCT
374FK
SNJ54BCT374J
ACTIVE
CDIP
J
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9051601MR
A
SNJ54BCT374J
SNJ54BCT374W
ACTIVE
CFP
W
20
1
Non-RoHS
& Green
SNPB
N / A for Pkg Type
-55 to 125
5962-9051601MS
A
SNJ54BCT374W
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
Samples
Samples
Samples
Samples
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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