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SN74CB3Q3125
SCDS143C – OCTOBER 2003 – REVISED JUNE 2015
SN74CB3Q3125 Quadruple FET Bus Switch
2.5-V/3.3-V Low-Voltage, High-Bandwidth Bus Switch
1 Features
•
•
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
(1)
2 Applications
(1)
High-Bandwidth Data Path (up to 500 MHz )
5-V Tolerant I/Os With Device Powered Up
or Powered Down
Low and Flat ON-State Resistance (ron)
Characteristics Over Operating Range
(ron = 3 Ω Typ)
Rail-to-Rail Switching on Data I/O Ports
– 0-V to 5-V Switching With 3.3-V VCC
– 0-V to 3.3-V Switching With 2.5-V VCC
Bidirectional Data Flow With Near-Zero
Propagation Delay
Low Input and Output Capacitance Minimizes
Loading and Signal Distortion
(Cio(OFF) = 4 pF Typ)
Fast Switching Frequency (fOE = 20 MHz Max)
Data and Control Inputs Provide Undershoot
Clamp Diodes
Low Power Consumption
(ICC = 0.3 mA Typ)
VCC Operating Range From 2.3 V to 3.6 V
Data I/Os Support 0-V to 5-V Signaling Levels
(0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
Control Inputs Can Be Driven by TTL,
5-V, or 3.3-V CMOS Outputs
Ioff Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
Supports Both Digital and Analog Applications:
USB Interface, Differential Signal Interface, Bus
Isolation, Low-Distortion Signal Gating
•
•
•
•
•
IP Phones: Wired and Wireless
Optical Modules
Optical Networking: Video Over Fiber and EPON
Private Branch Exchange (PBX)
WiMAX and Wireless Infrastructure Equipment
3 Description
The SN74CB3Q3125 device is a high-bandwidth FET
bus switch that uses a charge pump to elevate the
gate voltage of the pass transistor, thus providing a
low and flat ON-state resistance (ron). The low and
flat ON-state resistance allows for minimal
propagation delay and supports rail-to-rail switching
on the data input/output (I/O) ports. The
SN74CB3Q3125 device also features low data I/O
capacitance to minimize capacitive loading and signal
distortion on the data bus.
Device Information(1)
PART NUMBER
SN74CB3Q3125
PACKAGE
BODY SIZE (NOM)
VQFN (14)
3.50 mm × 3.50 mm
SSOP (16)
4.90 mm × 3.90 mm
TSSOP (16)
5.00 mm × 4.40 mm
TVSOP (16)
4.40 mm × 3.60 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
2
1A
3
2A
1
2B
SW
4
1OE
2OE
9
3A
12
8
SW
3B
4A
11
SW
4B
13
10
3OE
6
5
1B
SW
4OE
Pin numbers shown are for the DGV, PW,
and RGY packages.
For additional information regarding the performance
characteristics of the CB3Q family, refer to the TI application
report, CBT-C, CB3T, and CB3Q Signal-Switch Families
(SCDA008).
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74CB3Q3125
SCDS143C – OCTOBER 2003 – REVISED JUNE 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
4
5
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics ..........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 7
Detailed Description .............................................. 8
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8
8.3 Feature Description................................................... 9
8.4 Device Functional Modes.......................................... 9
9
Application and Implementation ........................ 10
9.1 Application Information............................................ 10
9.2 Typical Application ................................................. 10
10 Power Supply Recommendations ..................... 11
11 Layout................................................................... 12
11.1 Layout Guidelines ................................................. 12
11.2 Layout Example .................................................... 12
12 Device and Documentation Support ................. 13
12.1
12.2
12.3
12.4
12.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
13
13
13
13
13
13 Mechanical, Packaging, and Orderable
Information ........................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (March 2005) to Revision C
Page
•
Added Pin Functions table, ESD Ratings table, Thermal Information table, Detailed Description section, Application
and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
2
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SCDS143C – OCTOBER 2003 – REVISED JUNE 2015
5 Pin Configuration and Functions
13
3
12
4
11
5
10
6
9
7
8
VCC
4OE
4A
4B
3OE
3A
3B
1
1A
1B
2OE
2A
2B
VCC
14
2
14
13 4OE
2
12 4A
3
4B
10 3OE
9 3A
11
4
5
6
7
8
3B
1
GND
1OE
1A
1B
2OE
2A
2B
GND
RGY Package
14-Pin VQFN
Top View
1OE
DGV, PW Packages
14-Pin TVSOP, TSSOP
Top View
DBQ Package
16-Pin SSOP
Top View
NC
1OE
1A
1B
2OE
2A
2B
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
4OE
4A
4B
3OE
3A
3B
NC
NC - No internal connection
Pin Functions
PIN
I/O
DESCRIPTION
DGV, PW,
RGY
DBQ
1OE
1
2
I
1A
2
3
I/O
Channel 1A I/O 1A
1B
3
4
I/O
Channel 1B I/O 1B
2OE
4
5
I
2A
5
6
I/O
Channel 2A I/O 2A
2B
6
7
I/O
Channel 2B I/O 2B
GND
7
8
—
Ground
3B
8
10
I/O
Channel 3B I/O 3B
3A
9
11
I/O
Channel 3A I/O 3B
3OE
10
12
I
4B
11
13
I/O
Channel 4B I/O 4B
4A
12
14
I/O
Channel 4A I/O 4B
4OE
13
15
I
NC
—
1, 9
—
No Connect
VCC
14
16
—
Power
NAME
Output Enable (Active Low)
Output Enable (Active Low)
Output Enable (Active Low)
Output Enable (Active Low)
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
–0.5
4.6
V
VIN
Control input voltage
(2) (3)
–0.5
7
V
VI/O
Switch I/O voltage (2) (3) (4)
–0.5
7
V
II/K
Control input clamp current
VIN < 0
–50
mA
II/OK
I/O port clamp current
VI/O < 0
–50
mA
IIO
ON-state switch current (5)
±64
mA
Continuous current through VCC or GND
±100
mA
VCC
Supply voltage
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
(4)
(5)
150
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to ground, unless otherwise specified.
The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
VI and VO are used to denote specific conditions for VI/O.
II and IO are used to denote specific conditions for II/O.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
+2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
+1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
VIH
High-level control input voltage
VIL
Low-level control input voltage
VI/O
Data input and output voltage
TA
Operating free-air temperature
(1)
MIN
MAX
UNIT
2.3
3.6
VCC = 2.3 V to 2.7 V
1.7
5.5
V
VCC = 2.7 V to 3.6 V
2
5.5
VCC = 2.3 V to 2.7 V
0
0.7
VCC = 2.7 V to 3.6 V
0
0.8
0
5.5
V
–40
85
°C
V
V
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
6.4 Thermal Information
SN74CB3Q3257
THERMAL METRIC (1)
RθJA
(1)
4
Junction-to-ambient thermal resistance
DBQ
(SSOP)
DGV (TVSOP)
PW (TSSOP)
RGY (VQFN)
16 PINS
14 PINS
14 PINS
14 PINS
90
127
113
47
UNIT
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (1)
PARAMETER
VIK
TEST CONDITIONS
MIN
VCC = 3.6 V,
II = –18 mA
VCC = 3.6 V,
VIN = 0 to 5.5 V
IOZ (3)
VCC = 3.6 V,
VO = 0 to 5.5 V,
VI = 0,
Switch OFF,
VIN = VCC or GND
Ioff
VCC = 0,
VO = 0 to 5.5 V,
VI = 0
VCC = 3.6 V,
II/O = 0,
Switch ON or OFF,
VIN = VCC or GND
Other inputs at VCC or GND
IIN
Control inputs
ICC
ΔICC (4)
Control inputs
VCC = 3.6 V,
One input at 3 V,
ICCD (5)
Per control
input
VCC = 3.6 V,
A and B ports open,
Cin
Control inputs
VCC = 3.3 V,
VIN = 5.5 V, 3.3 V, or 0
Cio(OFF)
VCC = 3.3 V,
Switch OFF,
VIN = VCC or GND,
Cio(ON)
VCC = 3.3 V,
ron (6)
VCC = 3 V
(1)
(2)
(3)
(4)
(5)
(6)
UNIT
–1.8
V
±1
µA
±1
µA
1
µA
1
mA
0.3
30
µA
0.04
0.2
mA/
MHz
2.5
3.5
pF
VI/O = 5.5 V, 3.3 V, or 0
4
5
pF
Switch ON,
VIN = VCC or GND,
VI/O = 5.5 V, 3.3 V, or 0
8
10
pF
VI = 0,
IO = 30 mA
4
8
VI = 1.7 V,
IO = –15 mA
4
9
VI = 0,
IO = 30 mA
4
6
VI = 2.4 V,
IO = –15 mA
4
8
Control input switching at 50% duty cycle
VCC = 2.3 V,
TYP at VCC = 2.5 V
TYP (2) MAX
Ω
VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins.
All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
For I/O ports, the parameter IOZ includes the input leakage current.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
This parameter specifies the dynamic power-supply current associated with the operating frequency of a single control input (see
Figure 2).
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is
determined by the lower of the voltages of the two (A or B) terminals.
6.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
VCC = 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
f OE (1)
OE
A or B
10
20
MHz
tpd (2)
A or B
B or A
0.12
0.2
ns
ten
OE
A or B
1.5
6.7
1.5
6.6
ns
tdis
OE
A or B
1
4.6
1
5.3
ns
PARAMETER
(1)
(2)
MIN
MAX
MIN
MAX
UNIT
Maximum switching frequency for control input (VO > VCC, VI = 5 V, RL ≥ 1 MΩ, CL = 0)
The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
capacitance, when driven by an ideal voltage source (zero output impedance).
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6.7 Typical Characteristics
At TA = 25°C and VCC = 3.3 V, unless otherwise noted.
12
16
10
12
Supply Current (mA)
On-State Resistance (:)
14
10
8
6
4
6
4
2
2
One OE Switching
0
0
0
0.5
1
1.5
2
2.5
3
3.5
Input Voltage (V)
4
4.5
5
0
2
4
D001
IO = –15 mA
6
8
10
12
14
16
OE Switching Frequency (MHz)
18
20
D002
A and B Ports Open
Figure 1. Typical On-State Resistance vs Input Voltage
6
8
Figure 2. Typical Supply Current vs OE Switching
Frequency
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7 Parameter Measurement Information
VCC
Input Generator
VIN
50 Ω
50 Ω
VG1
TEST CIRCUIT
DUT
2 × VCC
Input Generator
S1
RL
VO
VI
50 Ω
50 Ω
VG2
RL
CL
(see Note A)
TEST
VCC
S1
RL
VI
CL
t pd(s)
2.5 V ± 0.2 V
3.3 V ± 0.3 V
Open
Open
500 Ω
500 Ω
VCC or GND
VCC or GND
30 pF
50 pF
t PLZ/t PZL
2.5 V ± 0.2 V
3.3 V ± 0.3 V
2 × VCC
2 × VCC
500 Ω
500 Ω
GND
GND
30 pF
50 pF
0.15 V
0.3 V
t PHZ/t PZH
2.5 V ± 0.2 V
3.3 V ± 0.3 V
GND
GND
500 Ω
500 Ω
VCC
VCC
30 pF
50 pF
0.15 V
0.3 V
V∆
VCC
Output
Control
(VIN)
VCC/2
VCC
VCC/2
VCC/2
0V
t PLH
VCC/2
VCC
VCC/2
VCC/2
VOL
t PHZ
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELA Y TIMES (t pd(s) )
VOL + V∆
VOL
t PZH
VOH
Output
t PLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
t PHL
VCC/2
0V
t PZL
Output
Control
(VIN)
Open
GND
VOH
VCC/2
VOH − V∆
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
A.
CL includes probe and jig capacitance.
B.
Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output
control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the
output control.
C.
All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2.5 ns,
tf ≤2.5 ns.
D.
The outputs are measured one at a time, with one transition per measurement.
E.
tPLZ and tPHZ are the same as tdis.
F.
tPZL and tPZH are the same as ten.
G.
tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ONstate resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output
impedance).
H.
All parameters and waveforms are not applicable to all devices.
Figure 3. Test Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SN74CB3Q3125 device is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate
voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state
resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O)
ports. The SN74CB3Q3125 device also features low data I/O capacitance to minimize capacitive loading and
signal distortion on the data bus. Specifically designed to support high-bandwidth applications, the
SN74CB3Q3125 device provides an optimized interface solution ideally suited for broadband communications,
networking, and data-intensive computing systems.
The SN74CB3Q3125 device is organized as four 1-bit bus switches with separate output-enable (1OE, 2OE,
3OE, 4OE) inputs. It can be used as four 1-bit bus switches or as one 4-bit bus switch. When OE is low, the
associated 1-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow
between ports. When OE is high, the associated 1-bit bus switch is OFF, and a high-impedance state exists
between the A and B ports.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging
current backflow through the device when it is powered down. The device has isolation during power off.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
B
A
VCC
Charge
Pump
EN(1)
Figure 4. Simplified Schematic, Each FET Switch (SW)
8.2 Functional Block Diagram
2
1A
3
2A
1
2B
SW
4
1OE
2OE
9
3A
12
8
SW
3B
4A
3OE
11
SW
4B
13
10
8
6
5
1B
SW
4OE
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8.3 Feature Description
The SN74CB3Q3125 device has a high-bandwidth data path (up to 500 MHz) and has 5-V tolerant I/Os with the
device powered up or powered down. It also has low and flat ON-state resistance (ron) characteristics over
operating range (ron = 4-Ω Typ).
The SN74CB3Q3125 device has rail-to-rail switching on data I/O ports for 0-V to 5-V switching with
3.3-V VCCand 0-V to 3.3-V switching with 2.5-V VCC as well as bidirectional data flow with near-zero propagation
delay and low input/output capacitance that minimizes loading and signal distortion (Cio(OFF) = 3.5-pF Typ).
The SN74CB3Q3125 device also provides a fast switching frequency (fOE = 20-MHz Max) with data and control
inputs that provide undershoot clamp diodes as well as low power consumption (ICC = 0.6-mA Typ).
The VCC operating range is from 2.3 V to 3.6 V and the data I/Os support 0-V to 5-V signal levels of
(0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V).
The control inputs can be driven by TTL or 5-V or 3.3-V CMOS outputs, and Ioff supports partial-power-down
mode operation.
8.4 Device Functional Modes
Table 1 lists the functional modes for the SN74CB3Q3125 device.
Table 1. Function Table
INPUT
OE
INPUT/OUTPUT
A
FUNCTION
L
B
A port = B port
H
Z
Disconnect
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74CB3Q3125 device can be used to control up to four channels simultaneously.
9.2 Typical Application
The application shown in Figure 5 is a 4-bit bus being controlled. The OE pins are used to control the chip from
the bus controller. This is a very generic example and can apply to many situations. If an application requires
less than 4 bits, be sure to tie the A side to either high or low on unused channels.
Vcc
Vcc
1OE
1A
2OE
2A
Bus
Controller
4
3OE
3A
4OE
1
2
ron
3
1B
6
2B
4
5
ron
4
10
9
ron
8
Device
3B
13
4A 12
GND
0.1 PF
14
ron
11 4B
8
Pin numbers for DGV, PW, RGY packages
only
Figure 5. Typical Application of the SN74CB3Q3257
9.2.1 Design Requirements
The 0.1-µF capacitor must be placed as close as possible to the SN74CB3Q3257 device.
10
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Typical Application (continued)
9.2.2 Detailed Design Procedure
1. Recommended input conditions:
– For specified high and low levels, see VIH and VIL in Recommended Operating Conditions
– Inputs and outputs are overvoltage tolerant, which slows them to go as high as 5.5 V at any valid VCC
2. Recommended output conditions:
– Load currents must not exceed ±64 mA per channel
3. Frequency selection criterion:
– Added trace resistance or capacitance can reduce maximum frequency capability; use layout practices as
directed in Layout
9.2.3 Application Curve
5
Voltage (V)
4
3
2
1
Vin
Vout
0
0
200
400
600
800
Time (ps)
1000
1200
C001
Figure 6. Propagation Delay (tpd) Simulation Result at VCC = 3.3 V
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating listed in the
Absolute Maximum Ratings table.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF bypass capacitor is recommended. If multiple pins are labeled VCC, then a 0.01-μF or 0.022-μF
capacitor is recommended for each VCC because the VCC pins are tied together internally. For devices with dualsupply pins operating at different voltages, for example VCC and VDD, a 0.1-µF bypass capacitor is recommended
for each supply pin. To reject different frequencies of noise, use multiple bypass capacitors in parallel. Capacitors
with values of 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor must be installed as close to
the power terminal as possible for best results.
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Product Folder Links: SN74CB3Q3125
11
SN74CB3Q3125
SCDS143C – OCTOBER 2003 – REVISED JUNE 2015
www.ti.com
11 Layout
11.1 Layout Guidelines
Reflections and matching are closely related to the loop antenna theory but are different enough to be discussed
separately from the theory. When a PCB trace turns a corner at a 90° angle, a reflection can occur. A reflection
occurs primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to
1.414 times the width. This increase upsets the transmission-line characteristics, especially the distributed
capacitance and self-inductance of the trace, which results in the reflection. Not all PCB traces can be straight;
therefore, some traces must turn corners. Figure 7 shows progressively better techniques of rounding corners.
Only the last example (BEST) maintains constant trace width and minimizes reflections.
11.2 Layout Example
BETTER
BEST
2W
WORST
1W min.
W
Figure 7. Trace Example
12
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Copyright © 2003–2015, Texas Instruments Incorporated
Product Folder Links: SN74CB3Q3125
SN74CB3Q3125
www.ti.com
SCDS143C – OCTOBER 2003 – REVISED JUNE 2015
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Implications of Slow or Floating CMOS Inputs, SCBA004
• Selecting the Right Texas Instruments Signal Switch, SZZA030
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Product Folder Links: SN74CB3Q3125
13
PACKAGE OPTION ADDENDUM
www.ti.com
14-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
74CB3Q3125DBQRE4
ACTIVE
SSOP
DBQ
16
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BU125
Samples
SN74CB3Q3125DBQR
ACTIVE
SSOP
DBQ
16
2500
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BU125
Samples
SN74CB3Q3125DGVR
ACTIVE
TVSOP
DGV
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
BU125
Samples
SN74CB3Q3125PW
ACTIVE
TSSOP
PW
14
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
BU125
Samples
SN74CB3Q3125PWR
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
BU125
Samples
SN74CB3Q3125PWRE4
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
BU125
Samples
SN74CB3Q3125RGYR
ACTIVE
VQFN
RGY
14
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BU125
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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