SN74CBT16212CDLR

     

  

    
  SCDS146A − OCTOBER 2003 − REVISED JANUARY 2004 D Member of the Texas Instruments D D D D D D D D D D D D D DGG, DGV, OR DL PACKAGE (TOP VIEW) Widebus Family Undershoot Protection for Off-Isolation on A and B Ports Up To −2 V Bidirectional Data Flow, With Near-Zero Propagation Delay Low ON-State Resistance (ron) Characteristics (ron = 3 Ω Typical) Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 8 pF Typical) Data and Control Inputs Provide Undershoot Clamp Diodes Low Power Consumption (ICC = 5 µA Max) VCC Operating Range From 4 V to 5.5 V Data I/Os Support 0 to 5-V Signaling Levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V) Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Outputs Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 22 − 2000-V Human-Body Model (A114-B, Class II) − 1000-V Charged-Device Model (C101) Supports Both Digital and Analog Applications: PCI Interface, Memory Interleaving, Bus Isolation, Low-Distortion Signal Gating S0 1A1 1A2 2A1 2A2 3A1 3A2 GND 4A1 4A2 5A1 5A2 6A1 6A2 7A1 7A2 VCC 8A1 GND 8A2 9A1 9A2 10A1 10A2 11A1 11A2 12A1 12A2 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 S1 S2 1B1 1B2 2B1 2B2 3B1 GND 3B2 4B1 4B2 5B1 5B2 6B1 6B2 7B1 7B2 8B1 GND 8B2 9B1 9B2 10B1 10B2 11B1 11B2 12B1 12B2 description/ordering information ORDERING INFORMATION PACKAGE† TA SSOP − DL −40°C −40 C to 85 85°C C TSSOP − DGG ORDERABLE PART NUMBER Tube SN74CBT16212CDL Tape and reel SN74CBT16212CDLR Tube SN74CBT16212CDGG Tape and reel SN74CBT16212CDGGR TOP-SIDE MARKING CBT16212C CBT16212C TVSOP − DGV Tape and reel SN74CBT16212CDGVR CY212C † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. Copyright  2004, Texas Instruments Incorporated   !"#$ % &'!!($ #%  )'*+&#$ ,#$(!,'&$% &!" $ %)(&&#$% )(! $.( $(!"%  (/#% %$!'"($% %$#,#!, 0#!!#$1- !,'&$ )!&(%%2 ,(% $ (&(%%#!+1 &+',( $(%$2  #++ )#!#"($(!%- POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 
     

  

    
  SCDS146A − OCTOBER 2003 − REVISED JANUARY 2004 description/ordering information (continued) The SN74CBT16212C is a high-speed TTL-compatible FET bus-exchange switch with low ON-state resistance (ron), allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the SN74CBT16212C provides protection for undershoot up to −2 V by sensing an undershoot event and ensuring that the switch remains in the proper OFF state. The SN74CBT16212C operates as a 24-bit bus switch, or as a 12-bit bus-exchange that provides data exchanging between four signal ports. The select (S0, S1, S2) inputs control the data path of the bus-exchange switch. When the bus-exchange switch is ON, the A port is connected to the B port, allowing bidirectional data flow between ports. When the bus-exchange switch is disabled, a high-impedance state exists between the A and B ports. This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, each select input should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. FUNCTION TABLE (each 12-bit bus-exchange) INPUTS 2 INPUTS/OUTPUTS S0 FUNCTION S2 S1 A1 A2 L L L L L Z Z Disconnect H B1 Z A1 port = B1 port L H L B2 Z A1 port = B2 port L H H Z B1 A2 port = B1 port H L L Z B2 A2 port = B2 port H L H Z Z Disconnect H H L B1 B2 A1 port = B1 port A2 port = B2 port H H H B2 B1 A1 port = B2 port A2 port = B1 port POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
     

  

    
  SCDS146A − OCTOBER 2003 − REVISED JANUARY 2004 logic diagram (positive logic) 2 1A1 54 1B1 SW SW SW 3 53 SW 1A2 12A1 27 1B2 30 SW 12B1 SW SW 28 29 SW 12A2 12B2 1 S0 56 S1 55 S2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 
     

  

    
  SCDS146A − OCTOBER 2003 − REVISED JANUARY 2004 simplified schematic, each FET switch (SW) A B Undershoot Protection Circuit EN† † EN is the internal enable signal applied to the switch. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Control input voltage range, VIN (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Switch I/O voltage range, VI/O (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Control input clamp current, IIK (VIN < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA I/O port clamp current, II/OK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA ON-state switch current, II/O (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±128 mA Continuous current through VCC or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 5): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to ground unless otherwise specified. 2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. VI and VO are used to denote specific conditions for VI/O. 4. II and IO are used to denote specific conditions for II/O. 5. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 6) MIN MAX VCC VIH Supply voltage 4 5.5 UNIT V High-level control input voltage 2 5.5 V VIL VI/O Low-level control input voltage 0 0.8 V Data input/output voltage 0 5.5 V TA Operating free-air temperature −40 85 °C NOTE 6: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
     

  

    
  SCDS146A − OCTOBER 2003 − REVISED JANUARY 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK Control inputs VCC = 4.5 V, VIKU Data inputs VCC = 5 V, IIN Control inputs VCC = 5.5 V, IOZ‡ VCC = 5.5 V, Ioff VCC = 0, ICC VCC = 5.5 V, IIN = −18 mA 0 mA > II ≥ −50 mA, VIN = VCC or GND, VIN = VCC or GND VO = 0 to 5.5 V, VI = 0, MIN TYP† Switch OFF Switch OFF, VIN = VCC or GND MAX UNIT −1.8 V −2 V ±1 µA ±10 µA VO = 0 to 5.5 V, II/O = 0, VIN = VCC or GND, VI = 0 10 µA Switch ON or OFF 7.5 µA VCC = 5.5 V, VIN = 3 V or 0 One input at 3.4 V, Other inputs at VCC or GND 2.5 mA Cio(OFF) VI/O = 3 V or 0, Switch OFF, Cio(ON) VI/O = 3 V or 0, VCC = 4 V, TYP at VCC = 4 V ∆ICC§ Cin Control inputs Control inputs ron¶ VCC = 4.5 V 3.5 pF VIN = VCC or GND 8 pF Switch ON, VIN = VCC or GND 19 pF VI = 2.4 V, IO = −15 mA 8 12 IO = 64 mA IO = 30 mA 3 6 VI = 0 3 6 Ω VI = 2.4 V, IO = −15 mA 5 10 VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins. † All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C. ‡ For I/O ports, the parameter IOZ includes the input leakage current. § This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND. ¶ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) VCC = 4 V VCC = 5 V ± 0.5 V MIN MIN FROM (INPUT) TO (OUTPUT) A or B B or A S A 7 1.5 ten S B 7.2 tdis S B 7.7 PARAMETER tpd# tpd(s) MAX 0.24 UNIT MAX 0.15 ns 6.4 ns 1.5 7 ns 1.5 7.5 ns # The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 
     

  

    
  SCDS146A − OCTOBER 2003 − REVISED JANUARY 2004 undershoot characteristics (see Figures 1 and 2) PARAMETER TEST CONDITIONS VOUTU VCC = 5.5 V, Switch OFF, † All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C. VCC Input Generator Ax VS DUT 2 VOH−0.3 VIN = VCC or GND Input 90 % (Open Socket) 10 % Bx 100 kΩ MAX UNIT V Figure 1. Device Test Setup POST OFFICE BOX 655303 90 % 2 ns 5.5 V 2 ns 10 % −2 V 20 ns 10 pF Output (VOUTU) 6 TYP† 11 V 100 kΩ 50 Ω MIN VOH VOH − 0.3 Figure 2. Transient Input Voltage (VI) and Output Voltage (VOUTU) Waveforms (Switch OFF) • DALLAS, TEXAS 75265 
     

  

    
  SCDS146A − OCTOBER 2003 − REVISED JANUARY 2004 PARAMETER MEASUREMENT INFORMATION VCC Input Generator VIN 50 Ω 50 Ω VG1 TEST CIRCUIT DUT 7V Input Generator VI S1 RL VO GND 50 Ω 50 Ω VG2 CL (see Note A) RL TEST VCC S1 RL VI CL tpd(s) 5 V ± 0.5 V 4V Open Open 500 Ω 500 Ω VCC or GND VCC or GND 50 pF 50 pF tPLZ/tPZL 5 V ± 0.5 V 4V 7V 7V 500 Ω 500 Ω GND GND 50 pF 50 pF 0.3 V 0.3 V tPHZ/tPZH 5 V ± 0.5 V 4V Open Open 500 Ω 500 Ω VCC VCC 50 pF 50 pF 0.3 V 0.3 V Output Control (VIN) V∆ 3V 1.5 V 3V 1.5 V 1.5 V 0V tPLH VOH Output 1.5 V Output Waveform 1 S1 at 7 V (see Note B) tPLZ 3.5 V 1.5 V tPZH tPHL 1.5 V VOL 1.5 V 0V tPZL Output Control (VIN) Open Output Waveform 2 S1 at Open (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (tpd(s)) VOL + V∆ VOL tPHZ 1.5 V VOH − V∆ VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). H. All parameters and waveforms are not applicable to all devices. Figure 3. Test Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74CBT16212CDGGR ACTIVE TSSOP DGG 56 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CBT16212C SN74CBT16212CDGVR ACTIVE TVSOP DGV 56 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CY212C SN74CBT16212CDL ACTIVE SSOP DL 56 20 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CBT16212C SN74CBT16212CDLR ACTIVE SSOP DL 56 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CBT16212C (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of