SN74CBT16211CDLR

    

  

    
  SCDS116C − JANUARY 2003 − REVISED OCTOBER 2003 D Member of the Texas Instruments D D D D D D D D D D D D D DGG, DGV, OR DL PACKAGE (TOP VIEW) Widebus Family Undershoot Protection for Off-Isolation on A and B Ports Up To −2 V Bidirectional Data Flow, With Near-Zero Propagation Delay Low ON-State Resistance (ron) Characteristics (ron = 3 Ω Typical) Low Input/Output Capacitance Minimizes Loading and Signal Distortion (Cio(OFF) = 5.5 pF Typical) Data and Control Inputs Provide Undershoot Clamp Diodes Low Power Consumption (ICC = 3 µA Max) VCC Operating Range From 4 V to 5.5 V Data I/Os Support 0 to 5-V Signaling Levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V) Control Inputs Can Be Driven by TTL or 5-V/3.3-V CMOS Outputs Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Performance Tested Per JESD 22 − 2000-V Human-Body Model (A114-B, Class II) − 1000-V Charged-Device Model (C101) Supports Both Digital and Analog Applications: PCI Interface, Memory Interleaving, Bus Isolation, Low-Distortion Signal Gating NC 1A1 1A2 1A3 1A4 1A5 1A6 GND 1A7 1A8 1A9 1A10 1A11 1A12 2A1 2A2 VCC 2A3 GND 2A4 2A5 2A6 2A7 2A8 2A9 2A10 2A11 2A12 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 1OE 2OE 1B1 1B2 1B3 1B4 1B5 GND 1B6 1B7 1B8 1B9 1B10 1B11 1B12 2B1 2B2 2B3 GND 2B4 2B5 2B6 2B7 2B8 2B9 2B10 2B11 2B12 NC − No internal connection description/ordering information ORDERING INFORMATION SSOP − DL −40°C −40 C to 85 85°C C ORDERABLE PART NUMBER PACKAGE† TA TSSOP − DGG TOP-SIDE MARKING Tube SN74CBT16211CDL Tape and reel SN74CBT16211CDLR Tube SN74CBT16211CDGG Tape and reel SN74CBT16211CDGGR CBT16211C CBT16211C TVSOP − DGV Tape and reel SN74CBT16211CDGVR CY211C † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. Copyright  2003, Texas Instruments Incorporated   !" # $%&" !#  '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "&#  &-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0  !)) '!!&"&#+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 
    

  

    
  SCDS116C − JANUARY 2003 − REVISED OCTOBER 2003 description/ordering information (continued) The SN74CBT16211C is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. Active Undershoot-Protection Circuitry on the A and B ports of the SN74CBT16211C provides protection for undershoot up to −2 V by sensing an undershoot event and ensuring that the switch remains in the proper OFF state. The SN74CBT16211C is organized as two 12-bit bus switches with separate output-enable (1OE, 2OE) inputs. It can be used as two 12-bit bus switches or as one 24-bit bus switch. When OE is low, the associated 12-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 12-bit bus switch is OFF, and the high-impedance state exists between the A and B ports. This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. FUNCTION TABLE (each 12-bit bus switch) INPUT OE INPUT/OUTPUT A FUNCTION L B A port = B port H Z Disconnect logic diagram (positive logic) 54 2 1A1 1B1 SW 42 14 1A12 1B12 SW 56 1OE 15 2A1 41 2B1 SW 28 2A12 29 SW 55 2OE 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2B12 
    

  

    
  SCDS116C − JANUARY 2003 − REVISED OCTOBER 2003 simplified schematic, each FET switch (SW) A B Undershoot Protection Circuit EN† † EN is the internal enable signal applied to the switch. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Control input voltage range, VIN (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Switch I/O voltage range, VI/O (see Notes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Control input clamp current, IIK (VIN < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA I/O port clamp current, II/OK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA ON-state switch current, II/O (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±128 mA Continuous current through VCC or GND terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 5): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltages are with respect to ground unless otherwise specified. 2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. VI and VO are used to denote specific conditions for VI/O. 4. II and IO are used to denote specific conditions for II/O. 5. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 6) MIN MAX VCC VIH Supply voltage 4 5.5 UNIT V High-level control input voltage 2 5.5 V VIL VI/O Low-level control input voltage 0 0.8 V Data input/output voltage 0 5.5 V TA Operating free-air temperature −40 85 °C NOTE 6: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 
    

  

    
  SCDS116C − JANUARY 2003 − REVISED OCTOBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK Control inputs VCC = 4.5 V, VIKU Data inputs VCC = 5 V, IIN Control inputs VCC = 5.5 V, IOZ‡ VCC = 5.5 V, Ioff VCC = 0, ICC VCC = 5.5 V, IIN = −18 mA 0 mA > II ≥ −50 mA, VIN = VCC or GND, VIN = VCC or GND VO = 0 to 5.5 V, VI = 0, MIN Switch OFF Switch OFF, VIN = VCC or GND VO = 0 to 5.5 V, II/O = 0, VIN = VCC or GND, VI = 0 VCC = 5.5 V, VIN = 3 V or 0 One input at 3.4 V, Other inputs at VCC or GND Cio(OFF) VI/O = 3 V or 0, Switch OFF, Cio(ON) VI/O = 3 V or 0, VCC = 4 V, TYP at VCC = 4 V ∆ICC§ Cin Control inputs Control inputs ron¶ VCC = 4.5 V TYP† MAX UNIT −1.8 V −2 V ±1 µA ±10 µA 10 µA 3 µA 2.5 mA Switch ON or OFF 4.5 pF VIN = VCC or GND 5.5 pF Switch ON, VIN = VCC or GND 14.5 pF VI = 2.4 V, IO = −15 mA 8 12 IO = 64 mA IO = 30 mA 3 6 VI = 0 3 6 Ω VI = 2.4 V, IO = −15 mA 5 10 VIN and IIN refer to control inputs. VI, VO, II, and IO refer to data pins. † All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C. ‡ For I/O ports, the parameter IOZ includes the input leakage current. § This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND. ¶ Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is determined by the lower of the voltages of the two (A or B) terminals. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3) VCC = 4 V VCC = 5 V ± 0.5 V MIN MIN FROM (INPUT) TO (OUTPUT) tpd# A or B B or A 0.24 ten OE A or B 6.5 PARAMETER MAX 1.5 UNIT MAX 0.15 ns 6 ns tdis A or B 6.5 1.5 6 ns OE # The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 
    

  

    
  SCDS116C − JANUARY 2003 − REVISED OCTOBER 2003 undershoot characteristics (see Figures 1 and 2) PARAMETER TEST CONDITIONS VOUTU VCC = 5.5 V, Switch OFF, † All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C. VCC Input Generator Ax VS DUT TYP† 2 VOH−0.3 VIN = VCC or GND MAX UNIT V 11 V Input (Open Socket) 100 kΩ 50 Ω MIN Bx 100 kΩ 90 % 2 ns 10 % −2 V 20 ns Output (VOUTU) POST OFFICE BOX 655303 5.5 V 2 ns 10 % 10 pF Figure 1. Device Test Setup 90 % VOH VOH − 0.3 Figure 2. Transient Input Voltage (VI) and Output Voltage (VOUTU) Waveforms (Switch OFF) • DALLAS, TEXAS 75265 5 
    

  

    
  SCDS116C − JANUARY 2003 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION VCC Input Generator VIN 50 Ω 50 Ω VG1 TEST CIRCUIT DUT 7V Input Generator VI S1 RL VO GND 50 Ω 50 Ω VG2 CL (see Note A) RL TEST VCC S1 RL VI CL tpd(s) 5 V ± 0.5 V 4V Open Open 500 Ω 500 Ω VCC or GND VCC or GND 50 pF 50 pF tPLZ/tPZL 5 V ± 0.5 V 4V 7V 7V 500 Ω 500 Ω GND GND 50 pF 50 pF 0.3 V 0.3 V tPHZ/tPZH 5 V ± 0.5 V 4V Open Open 500 Ω 500 Ω VCC VCC 50 pF 50 pF 0.3 V 0.3 V Output Control (VIN) V∆ 3V 1.5 V 3V 1.5 V 1.5 V 0V tPLH VOH Output 1.5 V Output Waveform 1 S1 at 7 V (see Note B) tPLZ 3.5 V 1.5 V tPZH tPHL 1.5 V VOL Output Waveform 2 S1 at Open (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (tpd(s)) 1.5 V 0V tPZL Output Control (VIN) Open VOL + V∆ VOL tPHZ 1.5 V VOH − V∆ VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd(s). The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). H. All parameters and waveforms are not applicable to all devices. Figure 3. Test Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) SN74CBT16211CDGGR ACTIVE TSSOP DGG 56 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CBT16211C SN74CBT16211CDGVR ACTIVE TVSOP DGV 56 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CY211C SN74CBT16211CDL ACTIVE SSOP DL 56 20 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CBT16211C SN74CBT16211CDLR ACTIVE SSOP DL 56 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 CBT16211C (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of