SN74HC574NS

SN54HC574, SN74HC574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS148F − DECEMBER 1982 − REVISED AUGUST 2003 D Wide Operating Voltage Range of 2 V to 6 V D High-Current 3-State Noninverting Outputs Drive Bus Lines Directly or Up To 15 LSTTL Loads Low Power Consumption, 80-μA Max ICC Typical tpd = 22 ns ±6-mA Output Drive at 5 V Low Input Current of 1 μA Max Bus-Structured Pinout OE 1D 2D 3D 4D 5D 6D 7D 8D GND description/ordering information These octal edge-triggered D-type flip-flops feature 3-state outputs designed specifically for bus driving. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q CLK 2D 1D SN54HC574 . . . FK PACKAGE (TOP VIEW) The eight flip-flops enter data on the low-to-high transition of the clock (CLK) input. 3D 4D 5D 6D 7D 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2Q 3Q 4Q 5Q 6Q 8D GND CLK 8Q 7Q A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE VCC 1Q D D D D D SN54HC574 . . . J OR W PACKAGE SN74HC574 . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW) ORDERING INFORMATION PDIP − N SN74HC574N Tube of 25 SN74HC574DW Reel of 2000 SN74HC574DWR SSOP − DB Reel of 2000 SN74HC574DBR HC574 SOP − NS Reel of 2000 SN74HC574NSR HC574 Tube of 70 SN74HC574PW Reel of 2000 SN74HC574PWR Reel of 250 SN74HC574PWT CDIP − J Tube of 20 SNJ54HC574J SNJ54HC574J CFP − W Tube of 85 SNJ54HC574W SNJ54HC574W LCCC − FK Tube of 55 SNJ54HC574FK SNJ54HC574FK TSSOP − PW −55°C to 125°C † TOP-SIDE MARKING Tube of 20 SOIC − DW 40°C to 85°C −40°C ORDERABLE PART NUMBER PACKAGE† TA SN74HC574N HC574 HC574 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 2003, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54HC574, SN74HC574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS148F − DECEMBER 1982 − REVISED AUGUST 2003 description/ordering information (continued) OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. FUNCTION TABLE (each flip-flop) INPUTS OE CLK D OUTPUT Q L ↑ H H L ↑ L L L H or L X Q0 H X X Z logic diagram (positive logic) OE CLK 1 11 C1 1D 2 19 1Q 1D To Seven Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54HC574, SN74HC574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS148F − DECEMBER 1982 − REVISED AUGUST 2003 recommended operating conditions (see Note 3) SN54HC574 VCC Supply voltage VCC = 2 V VIH VCC = 4.5 V High-level High level input voltage VCC = 6 V MIN NOM MAX 2 5 6 Input voltage VO Output voltage TA 5 6 3.15 4.2 0 0 Input transition rise/fall time 2 4.2 VCC = 2 V Δt/Δv MAX 3.15 VCC = 6 V VI NOM 1.5 VCC = 4.5 V Low-level Low level input voltage MIN 1.5 VCC = 2 V VIL SN74HC574 0.5 1.35 1.35 1.8 1.8 0 VCC 0 V VCC V 1000 VCC = 4.5 V 500 500 VCC = 6 V 400 400 −55 125 −40 V VCC 1000 Operating free-air temperature V V 0.5 VCC UNIT 85 ns °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH TEST CONDITIONS TA = 25°C MIN TYP SN54HC574 MAX MIN MAX SN74HC574 MIN 2V 1.9 1.998 1.9 1.9 IOH = −20 20 μA 4.5 V 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 IOH = −6 mA 4.5 V 3.98 4.3 3.7 3.84 6V 5.48 5.8 5.2 5.34 VI = VIH or VIL IOH = −7.8 mA IOL = 20 μA VOL VCC VI = VIH or VIL IOL = 6 mA IOL = 7.8 mA MAX UNIT V 2V 0.002 0.1 0.1 0.1 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 0.33 V II VI = VCC or 0 6V ±0.1 ±100 ±1000 ±1000 nA IOZ VO = VCC or 0 6V ±0.01 ±0.5 ±10 ±5 μA ICC VI = VCC or 0, 8 160 80 μA 10 10 10 pF Ci IO = 0 6V 2 V to 6 V POST OFFICE BOX 655303 3 • DALLAS, TEXAS 75265 3 SN54HC574, SN74HC574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS148F − DECEMBER 1982 − REVISED AUGUST 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) TA = 25°C VCC fclock Clock frequency tw Pulse duration, CLK high or low tsu Setup time, data before CLK↑ th Hold time,, data after CLK↑ MIN SN54HC574 MAX MIN MAX SN74HC574 MIN MAX 2V 6 4 5 4.5 V 30 20 24 6V 38 24 28 2V 80 120 100 4.5 V 16 24 20 6V 14 20 17 2V 100 150 125 4.5 V 20 30 25 6V 17 26 21 2V 5 5 5 4.5 V 5 5 5 6V 5 5 5 UNIT MHz ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd ten tdis tt 4 CLK OE OE Any Q Any Q Any Q Any yQ VCC TA = 25°C MIN TYP SN54HC574 MAX MIN MAX SN74HC574 MIN 2V 6 11 4 5 4.5 V 30 36 20 24 6V 36 40 24 28 MAX MHz 2V 90 180 270 225 4.5 V 28 36 54 45 6V 24 31 46 38 2V 77 150 225 190 4.5 V 26 30 45 38 6V 23 26 38 32 2V 52 150 225 190 4.5 V 24 30 45 38 6V 22 26 38 32 2V 28 60 90 75 4.5 V 8 12 18 15 6V 6 10 15 13 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns ns ns ns SN54HC574, SN74HC574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS148F − DECEMBER 1982 − REVISED AUGUST 2003 switching characteristics over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd ten tt CLK OE Any Q Any Q Any yQ VCC TA = 25°C MIN TYP SN54HC574 MAX MIN MAX SN74HC574 MIN 2V 6 5 4.5 V 30 24 6V 36 28 MAX UNIT MHz 2V 105 265 400 330 4.5 V 36 53 80 66 6V 31 46 68 57 2V 95 235 355 295 4.5 V 32 47 71 59 6V 28 41 60 51 2V 60 210 315 265 4.5 V 17 42 63 53 6V 14 36 53 45 ns ns ns operating characteristics, TA = 25°C PARAMETER Cpd Power dissipation capacitance per flip-flop POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TEST CONDITIONS TYP UNIT No load 100 pF 5 SN54HC574, SN74HC574 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS SCLS148F − DECEMBER 1982 − REVISED AUGUST 2003 PARAMETER MEASUREMENT INFORMATION VCC From Output Under Test CL (see Note A) PARAMETER S1 Test Point tPZH ten RL RL 1 kΩ tPZL tPHZ tdis tPLZ S2 1 kΩ Data Input VCC 50% 10% 50% VCC 0V In-Phase Output 50% 10% tPHL 90% 90% tr tPHL Out-ofPhase Output 90% Output Control (Low-Level Enabling) tf Closed Closed Open Open Open th 90% 90% VCC 50% 10% 0 V tf 50% 10% VCC 50% 50% 0V tPZL VOH 50% 10% V OL tf 90% VOH VOL tPLZ ≈VCC 50% Output Waveform 1 (See Note B) ≈VCC 10% tPZH tPLH 50% 10% Open VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES 50% tPLH Open tr VOLTAGE WAVEFORMS PULSE DURATIONS 50% Closed 0V 0V Input Closed tsu 0V 50% Open 50% 50% tw Low-Level Pulse 50 pF or 150 pF VCC Reference Input VCC 50% S2 50 pF or 150 pF LOAD CIRCUIT High-Level Pulse S1 50 pF −− tpd or tt CL Output Waveform 2 (See Note B) VOL tPHZ 50% 90% VOH ≈0 V tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured when the input duty cycle is 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 14-Aug-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) JM38510/65604BRA ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 65604BRA M38510/65604BRA ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 JM38510/ 65604BRA SN54HC574J ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 SN54HC574J SN74HC574APWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC574A SN74HC574DBR ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC574 SN74HC574DBRG4 ACTIVE SSOP DB 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC574 SN74HC574DW ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC574 SN74HC574DWG4 ACTIVE SOIC DW 20 25 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC574 SN74HC574DWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC574 SN74HC574N ACTIVE PDIP N 20 20 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC574N SN74HC574NE4 ACTIVE PDIP N 20 20 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC574N SN74HC574NSR ACTIVE SO NS 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC574 SN74HC574PW ACTIVE TSSOP PW 20 70 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC574 SN74HC574PWR ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC574 SN74HC574PWRG4 ACTIVE TSSOP PW 20 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC574 SN74HC574PWT ACTIVE TSSOP PW 20 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC574 SNJ54HC574FK ACTIVE LCCC FK 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 SNJ54HC 574FK SNJ54HC574J ACTIVE CDIP J 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 SNJ54HC574J SNJ54HC574W ACTIVE CFP W 20 1 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 SNJ54HC574W Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 14-Aug-2021 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of