SN74HCS05-Q1
SN74HCS05-Q1
SCLS770A – JUNE 2020 – REVISED
OCTOBER 2020
SCLS770A – JUNE 2020 – REVISED OCTOBER 2020
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SN74HCS05-Q1 Automotive Hex Inverter with Open-Drain Outputs and SchmittTrigger Inputs
1 Features
2 Applications
•
•
•
•
This device contains six independent inverter with
open-drain outputs and Schmitt-trigger inputs. Each
gate performs the Boolean function Y = A in positive
logic.
Device Information (1)
PART NUMBER
SN74HCS05QDRQ1
8.70 mm × 3.90 mm
Voltage
Output
Current
Voltage
Current
Output
Input Voltage
Time
Time
Voltage
Input Voltage
Output
Response
Waveforms
Time
Time
Current
Schmitt-trigger
CMOS Input
Supply Current
Response
Waveforms
Supply Current
Standard
CMOS Input
Supports Slow Inputs
Input
Voltage
Noise Rejection
Input Voltage
SOIC (14)
For all available packages, see the orderable addendum at
the end of the data sheet.
Input
Voltage
Input
Voltage
Input Voltage
Waveforms
BODY SIZE (NOM)
5.00 mm × 4.40 mm
(1)
Low Power
PACKAGE
SN74HCS05QPWRQ1 TSSOP (14)
Time
Voltage
•
3 Description
Output
•
Drive indicator LEDs
Level-shift using open-drain outputs
Invert a digital signal
Current
•
•
AEC-Q100 Qualified for automotive applications:
– Device temperature grade 1: –40°C to +125°C,
TA
– Device HBM ESD Classification Level 2
– Device CDM ESD Classifcation Level C6
Wide operating voltage range: 2 V to 6 V
Schmitt-trigger inputs allow for slow or noisy input
signals
Low power consumption
– Typical ICC of 100 nA
– Typical input leakage current of ±100 nA
±7.8-mA output drive at 5 V
Time
Benefits of Schmitt-trigger Inputs
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
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Incorporated
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property
matters
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 3
6.1 Absolute Maximum Ratings ....................................... 3
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................4
6.5 Electrical Characteristics ............................................4
6.6 Switching Characteristics ...........................................5
6.7 Operating Characteristics .......................................... 5
6.8 Typical Characteristics................................................ 6
7 Parameter Measurement Information............................ 7
8 Detailed Description........................................................8
8.1 Overview..................................................................... 8
8.2 Functional Block Diagram........................................... 8
8.3 Feature Description.....................................................8
8.4 Device Functional Modes............................................9
9 Application and Implementation.................................. 10
9.1 Application Information............................................. 10
9.2 Typical Application.................................................... 10
10 Power Supply Recommendations..............................12
11 Layout........................................................................... 12
11.1 Layout Guidelines................................................... 12
11.2 Layout Example...................................................... 12
12 Device and Documentation Support..........................13
12.1 Documentation Support.......................................... 13
12.2 Related Links.......................................................... 13
12.3 Support Resources................................................. 13
12.4 Trademarks............................................................. 13
12.5 Electrostatic Discharge Caution..............................13
12.6 Glossary..................................................................13
13 Mechanical, Packaging, and Orderable
Information.................................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from June 25, 2020 to October 22, 2020 (from Revision * (June 2020) to Revision A
(October 2020))
Page
• Updated the numbering format for tables, figures and cross-references throughout the document...................1
• Improved clarity of functionality for the device....................................................................................................8
2
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5 Pin Configuration and Functions
1A
1
14
VCC
1Y
2
13
6A
2A
3
12
6Y
2Y
4
11
5A
3A
5
10
5Y
3Y
6
9
GND
7
8
4A
4Y
Figure 5-1. PW or D Package 14-Pin TSSOP or SOIC Top View
Pin Functions
PIN
NAME
I/O
NO.
1A
1
Input
1Y
2
Output
2A
3
Input
2Y
4
Output
3A
5
Input
3Y
6
Output
GND
7
—
4Y
8
Output
4A
9
Input
5Y
10
Output
5A
11
Input
6Y
12
Output
6A
13
Input
VCC
14
—
DESCRIPTION
Channel 1, Input A
Channel 1, Output Y
Channel 2, Input A
Channel 2, Output Y
Channel 3, Input A
Channel 3, Output Y
Ground
Channel 4, Output Y
Channel 4, Input A
Channel 5, Output Y
Channel 5, Input A
Channel 6, Output Y
Channel 6, Input A
Positive Supply
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
Supply voltage
IIK
Input clamp current(2)
VI < 0 or VI > VCC + 0.5
±20
mA
IOK
Output clamp current(2)
VO < 0 or VO > VCC + 0.5
±20
mA
IO
Continuous output current
VO = 0 to VCC
±35
mA
Continuous current through VCC or GND
±70
mA
TJ
Junction temperature(3)
150
°C
Tstg
Storage temperature
150
°C
(2)
(3)
–65
7
UNIT
VCC
(1)
–0.5
MAX
V
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Guaranteed by design.
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6.2 ESD Ratings
VALUE
Human body model (HBM), per AEC
HBM ESD Classification Level 2
V(ESD)
(1)
Electrostatic discharge
Q100-002(1)
UNIT
±4000
V
Charged device model (CDM), per AEC
Q100-011
CDM ESD Classification Level C6
±1500
AEC Q100-002 indicate that HBM stressing shall be in accordrance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
5
MAX
UNIT
VCC
Supply voltage
2
6
V
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
TA
Ambient temperature
–40
125
°C
6.4 Thermal Information
SN74HCS05-Q1
THERMAL METRIC(1)
PW (TSSOP)
D (SOIC)
UNIT
14 PINS
14 PINS
RθJA
Junction-to-ambient thermal resistance
151.7
133.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
79.4
89.0
°C/W
RθJB
Junction-to-board thermal resistance
94.7
89.5
°C/W
ΨJT
Junction-to-top characterization parameter
25.2
45.5
°C/W
ΨJB
Junction-to-board characterization parameter
94.1
89.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER
VT+
VT-
ΔVT
TEST CONDITIONS
Positive switching threshold
Negative switching threshold
Hysteresis (VT+ - VT-)
IOL = 20 µA
VOL
4
Low-level output voltage
VI = VIH or VIL
VCC
MIN
TYP
MAX UNIT
2V
0.7
1.5
4.5 V
1.7
3.15
6V
2.1
4.2
2V
0.3
1.0
4.5 V
0.9
2.2
6V
1.2
3.0
2V
0.2
1.0
4.5 V
0.4
1.4
6V
0.6
2 V to 6 V
V
V
V
1.6
0.002
0.1
IOL = 6 mA
4.5 V
0.18
0.30
IOL = 7.8 mA
6V
0.22
0.33
V
II
Input leakage current
VI = VCC or 0
6V
±100
±1000
nA
ICC
Supply current
VI = VCC or 0, IO = 0
6V
0.1
2
µA
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over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER
Ci
TEST CONDITIONS
VCC
Input capacitance
MIN
TYP
MAX UNIT
2 V to 6 V
5
pF
6.6 Switching Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). See Parameter
Measurement Information.
PARAMETER
tpd
tt
Propagation delay
FROM (INPUT)
A
TO (OUTPUT)
Y
Transition-time
Y
TYP
MAX
2V
VCC
MIN
18
39
4.5 V
13
15
6V
12
15
2V
9
16
4.5 V
5
9
6V
4
8
UNIT
ns
ns
6.7 Operating Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance per gate
No load
MIN
TYP
10
MAX
UNIT
pF
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6.8 Typical Characteristics
TA = 25°C
46
0.2
VCC = 2 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 6 V
Output Resistance (:)
42
VCC = 2 V
0.18
ICC ± Supply Current (mA)
44
40
38
36
34
32
30
0.16
VCC = 2.5 V
0.14
VCC = 3.3 V
0.12
0.1
0.08
0.06
0.04
0.02
28
0
26
0
2.5
5
7.5 10 12.5 15 17.5
Output Sink Current (mA)
20
22.5
25
ICC ± Supply Current (mA)
Figure 6-1. Output driver resistance in Low state
0
0.5
1
1.5
2
2.5
VI ± Input Voltage (V)
3
3.5
Figure 6-2. Typical supply current versus input
voltage across common supply values (2 V to 3.3
V)
0.65
0.6
0.55
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
VCC = 4.5 V
VCC = 5 V
VCC = 6 V
0
0.5
1
1.5
2 2.5 3 3.5 4
VI ± Input Voltage (V)
4.5
5
5.5
6
Figure 6-3. Typical supply current versus input voltage across common supply values (4.5 V to 6 V)
6
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7 Parameter Measurement Information
•
•
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
The outputs are measured one at a time, with one input transition per measurement.
VCC
Test
Point
90%
VCC
90%
Input
10%
10%
S1
tr(1)
RL
From Output
Under Test
90%
CL(1)
0V
tf(1)
VOH
90%
Output
10%
10%
tr(1)
A. CL= 50 pF and includes probe and jig capacitance.
tf(1)
VOL
Figure 7-2. Voltage Waveforms Transition Times
Figure 7-1. Load Circuit
VCC
Input
50%
50%
0V
tPLZ(1)
tPZL(2)
VOH
Output
50%
10% VCC
tPZL(2)
VOL
tPLZ(1)
VOH
Output
50%
10%
VOL
A. The maximum between tPLH and tPHL is used for tpd.
Figure 7-3. Voltage Waveforms Propagation Delays
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8 Detailed Description
8.1 Overview
This device contains six independent inverter with open-drain outputs and Schmitt-trigger inputs. Each gate
performs the Boolean function Y = A in positive logic.
8.2 Functional Block Diagram
One of Six Channels
xA
xY
8.3 Feature Description
8.3.1 Open-Drain CMOS Outputs
This device includes open-drain CMOS outputs. Open-drain outputs can only drive the output low. When in the
high logical state, open-drain outputs will be in a high-impedance state. The drive capability of this device may
create fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the output power of the device to be limited to avoid damage due to
overcurrent. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all
times.
When placed into the high-impedance state, the output will neither source nor sink current, with the exception of
minor leakage current as defined in the Electrical Characteristics table. In the high-impedance state, the output
voltage is not controlled by the device and is dependent on external factors. If no other drivers are connected to
the node, then this is known as a floating node and the voltage is unknown. A pull-up resistor can be connected
to the output to provide a known voltage at the output while it is in the high-impedance state. The value of the
resistor will depend on multiple factors, including parasitic capacitance and power consumption limitations.
Typically, a 10 kΩ resistor can be used to meet these requirements.
Unused open-drain CMOS outputs should be left disconnected.
8.3.2 CMOS Schmitt-Trigger Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor from the input to ground in
parallel with the input capacitance given in the Electrical Characteristics. The worst case resistance is calculated
with the maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage
current, given in the Electrical Characteristics, using ohm's law (R = V ÷ I).
The Schmitt-trigger input architecture provides hysteresis as defined by ΔV T in the Electrical Characteristics,
which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much slower
than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the inputs
slowly will also increase dynamic current consumption of the device. For additional information regarding
Schmitt-trigger inputs, please see Understanding Schmitt Triggers.
8
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8.3.3 Clamp Diode Structure
The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Figure 8-1.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to
the device. The recommended input and output voltage ratings may be exceeded if the input and
output clamp-current ratings are observed.
VCC
Device
+IIK
+IOK
Logic
Input
Output
-IIK
-IOK
GND
Figure 8-1. Electrical Placement of Clamping Diodes for Each Input and Output
8.4 Device Functional Modes
Table 8-1. Function Table
INPUT
OUTPUT
A
Y
L
Z
H
L
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
In this application, the device is used to drive an indicator LED directly. Unused channels should have the inputs
terminated at either VCC or GND, whichever is more convenient, and the outputs should be left disconnected.
9.2 Typical Application
VCC
R1
VCC
Input
Figure 9-1. Typical application block diagram
9.2.1 Design Requirements
9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics.
The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the
SN74HCS05-Q1 plus the maximum supply current, I CC, listed in Electrical Characteristics. The logic device can
only sink as much current as is provided by the external pull-up resistor or other supply source. Be sure not to
exceed the maximum total current through GND listed in the Absolute Maximum Ratings.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and C
pd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
CAUTION
The maximum junction temperature, T J(max) listed in the Absolute Maximum Ratings, is an
additional limitation to prevent damage to the device. Do not violate any values listed in the Absolute
Maximum Ratings. These limits are provided to prevent damage to the device.
9.2.1.2 Input Considerations
Input signals must cross Vt-(min) to be considered a logic LOW, and Vt+(max) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either V CC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the
SN74HCS05-Q1, as specified in the Electrical Characteristics, and the desired input transition rate. A 10-kΩ
resistor value is often used due to these factors.
10
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The SN74HCS05-Q1 has no input signal transition rate requirements because it has Schmitt-trigger inputs.
Another benefit to having Schmitt-trigger inputs is the ability to reject noise. Noise with a large enough amplitude
can still cause issues. To know how much noise is too much, please refer to the ΔV T(min) in the Electrical
Characteristics. This hysteresis value will provide the peak-to-peak limit.
Unlike what happens with standard CMOS inputs, Schmitt-trigger inputs can be held at any valid value without
causing huge increases in power consumption. The typical additional current caused by holding an input at a
value other than VCC or ground is plotted in the Typical Characteristics.
Refer to the Feature Description for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the
output voltage as specified by the V OL specification in the Electrical Characteristics. The plot in Typical
Characteristics provides a typical relationship between output voltage and current for this device.
Open-drain outputs can be directly connected together to produce a wired-AND. This is possible because the
outputs cannot source current, and thus can never be in bus-contention.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to Feature Description for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout.
2. Ensure the capacitive load at the output is ≤ 70 pF. This is not a hard limit, however it will ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the SN74HCS05Q1 to the receiving device.
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in megaohms; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation
9.2.3 Application Curves
Input
Output
LED Status
OFF
ON
OFF
ON
Figure 9-2. Application timing diagram
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10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Condtions. Each V CC terminal should have a bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in
Figure 11-1.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used. Such unused input pins must not be left unconnected because the undefined
voltages at the outside connections result in undefined operational states. All unused inputs of digital logic
devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to
prevent them from floating. The logic level that must be applied to any particular unused input depends on the
function of the device. Generally, the inputs are tied to GND or V CC, whichever makes more sense for the logic
function or is more convenient.
11.2 Layout Example
GND
VCC
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
0.1 F
Unused input
tied to GND
Avoid 90°
corners for
signal lines
Bypass capacitor
placed close to
the device
1A
1
14
1Y
2
13
VCC Unused input
tied to VCC
6A
2A
3
12
6Y
2Y
4
11
5A
3A
5
10
5Y
3Y
6
9
4A
GND
7
8
4Y
Unused output
left floating
Figure 11-1. Example layout for the SN74HCS05-Q1
12
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Reduce Noise and Save Power with the New HCS Logic Family
• CMOS Power Consumption and CPD Calculation
• Designing with Logic
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74HCS05QDRQ1
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HCS05Q1
SN74HCS05QPWRQ1
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HCS05Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
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RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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