SN74HCS237-Q1
SCLS809A – SEPTEMBER 2020 – REVISED JUNE 2021
SN74HCS237-Q1 Automotive Qualified 3- to 8-Line Decoder/Demultiplexer with
Address Latches and Schmitt-Trigger Inputs
1 Features
3 Description
•
The SN74HCS237-Q1 is a three to eight decoder with
latched address inputs, one standard output strobe
(G0), and one active low output strobe (G 1). When
the latch enable (LE) input is low, the device acts as
a standard three to eight decoder. When the latch
enable (LE) input is high, the address latch retains its
previous state. When the outputs are gated by either
strobe input, they are all forced into the low state.
When the outputs are not disabled by one or both
of the strobe inputs, only the selected output is high
while all others are low.
Device Information
2 Applications
Response
Waveforms
5.00 mm × 4.40 mm
SOIC (16)
9.90 mm × 3.90 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
Input
Voltage
Time
Voltage
Output
Voltage
Output
Current
Current
Time
Time
Voltage
Input Voltage
Input Voltage
Supports Slow Inputs
Time
Output
Schmitt-trigger
CMOS Input
TSSOP (16)
SN74HCS237D-Q1
Current
Response
Waveforms
SN74HCS237PW-Q1
Noise Rejection
Input Voltage
Standard
CMOS Input
BODY SIZE (NOM)
Input
Voltage
Input
Voltage
Input Voltage
Waveforms
PACKAGE(1)
(1)
Low Power
Supply Current
•
Memory device selection with shared data bus
Reduce required number of outputs for chip select
applications
Route data
Supply Current
•
•
PART NUMBER
Time
Voltage
•
Output
•
Current
•
•
AEC-Q100 Qualified for automotive applications:
– Device temperature grade 1: –40°C to +125°C,
TA
– Device HBM ESD Classification Level 2
– Device CDM ESD Classifcation Level C6
Wide operating voltage range: 2 V to 6 V
Schmitt-trigger inputs allow for slow or noisy input
signals
Low power consumption
– Typical ICC of 100 nA
– Typical input leakage current of ±100 nA
±7.8-mA output drive at 6 V
Time
Benefits of Schmitt-trigger inputs
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74HCS237-Q1
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SCLS809A – SEPTEMBER 2020 – REVISED JUNE 2021
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................4
6.5 Electrical Characteristics ............................................5
6.6 Timing Characteristics ................................................5
6.7 Switching Characteristics ...........................................6
6.8 Operating Characteristics .......................................... 6
6.9 Typical Characteristics................................................ 7
7 Parameter Measurement Information............................ 8
8 Detailed Description........................................................9
8.1 Overview..................................................................... 9
8.2 Functional Block Diagram........................................... 9
8.3 Feature Description.....................................................9
8.4 Device Functional Modes..........................................11
9 Application and Implementation.................................. 12
9.1 Application Information............................................. 12
9.2 Typical Application.................................................... 12
10 Power Supply Recommendations..............................15
11 Layout........................................................................... 15
11.1 Layout Guidelines................................................... 15
11.2 Layout Example...................................................... 15
12 Device and Documentation Support..........................16
12.1 Documentation Support.......................................... 16
12.2 Receiving Notification of Documentation Updates..16
12.3 Support Resources................................................. 16
12.4 Trademarks............................................................. 16
12.5 Electrostatic Discharge Caution..............................16
12.6 Glossary..................................................................16
13 Mechanical, Packaging, and Orderable
Information.................................................................... 17
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (July 2020) to Revision A (May 2021)
Page
• The following change was made in the description section. Swapped "high" for "low" before, "the device acts
as a standard three to eight decoder". Swapped "low" for "high" before, "the address latch retains its previous
state"...................................................................................................................................................................1
• Changed active high latch enable pin name (LE) to active low (LE) for clarity. Effected sections: Pinout image,
pin description, timing characteristics table, switching characteristics table, functional block diagram, device
functional modes, typical application, application curve, and layout example.................................................... 1
• The following change was made in the overview section. Swapped "high" for "low" before, "the circuit
functions as a normal one-of-eight decoder". Swapped "low" for "high" before, "the address latches will
maintain their previous states"............................................................................................................................9
2
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5 Pin Configuration and Functions
A0
A1
1
16
VCC
2
Y0
A2
3
15
14
LE
G1
4
13
Y2
5
12
Y3
G0
6
11
Y7
GND
7
8
10
Y4
Y5
Y6
9
Y1
D or PW Package 16-Pin SOIC or TSSOP Top View
Table 5-1. Pin Functions
PIN
SOIC or TSSOP
NO.
NAME
I/O
DESCRIPTION
1
A0
I
Address select 0
2
A1
I
Address select 1
3
A2
I
Address select 2
4
LE
I
Latch enable, active low
5
G1
I
Strobe input 1, active low
6
G0
I
Strobe input 0
7
Y7
O
Output 7
8
GND
—
Ground
9
Y6
O
Output 6
10
Y5
O
Output 5
11
Y4
O
Output 4
12
Y3
O
Output 3
13
Y2
O
Output 2
14
Y1
O
Output 1
15
Y0
O
Output 0
16
VCC
—
Positive supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
–0.5
7
UNIT
VCC
Supply voltage
IIK
Input clamp current(2)
VI < –0.5 V or VI > VCC + 0.5 V
±20
mA
V
IOK
Output clamp current(2)
VI < –0.5 V or VI > VCC + 0.5 V
±20
mA
IO
Continuous output current
VO = 0 to VCC
±35
mA
Continuous current through VCC or GND
±70
mA
TJ
Junction temperature(3)
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Guaranteed by design.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 2
±4000
Charged device model (CDM), per AEC
Q100-011 CDM ESD Classification Level C6
±1500
UNIT
V
AEC Q100-002 indicate that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
VCC
Supply voltage
2
5
6
UNIT
V
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
TA
Ambient temperature
–40
125
°C
6.4 Thermal Information
SN74HCS237-Q1
THERMAL METRIC(1)
D (SOIC)
UNIT
16 PINS
16 PINS
RθJA
Junction-to-ambient thermal resistance
141.2
122.2
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
78.8
80.9
°C/W
RθJB
Junction-to-board thermal resistance
85.8
80.6
°C/W
ΨJT
Junction-to-top characterization parameter
27.7
40.4
°C/W
ΨJB
Junction-to-board characterization parameter
85.5
80.3
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
(1)
4
PW (TSSOP)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER
VT+
VT-
ΔVT
VOH
VOL
TEST CONDITIONS
Positive switching threshold
Negative switching threshold
Hysteresis (VT+ - VT-
)(1)
High-level output voltage
Low-level output voltage
VI = VIH or VIL
VI = VIH or VIL
VCC
MIN
TYP
MAX UNIT
2V
0.7
1.5
4.5 V
1.7
3.15
6V
2.1
4.2
2V
0.3
1.0
4.5 V
0.9
2.2
6V
1.2
3.0
2V
0.2
1.0
4.5 V
0.4
1.4
6V
0.6
1.6
IOH = -20 µA
2 V to 6 V
VCC – 0.1
VCC – 0.002
IOH = -6 mA
4.5 V
4.0
4.3
IOH = -7.8 mA
6V
5.4
IOL = 20 µA
2 V to 6 V
IOL = 6 mA
IOL = 7.8 mA
V
V
V
V
5.75
0.002
0.1
4.5 V
0.18
0.30
6V
0.22
0.33
V
II
Input leakage current
VI = VCC or 0
6V
±100
±1000
nA
ICC
Supply current
VI = VCC or 0, IO = 0
6V
0.1
2
µA
Ci
Input capacitance
5
pF
(1)
Guaranteed by design.
2 V to 6 V
6.6 Timing Characteristics
CL = 50 pF; over operating free-air temperature range (unless otherwise noted). See Parameter Measurement Information.
Operating free-air temperature (TA)
PARAMETER
VCC
25°C
MIN
tw
tsu
th
Pulse duration
Setup time
Hold time
LE pulse width
An to LE setup time
An to LE hold time
–40°C to 125°C
MAX
MIN
2V
6
9
4.5 V
5
7
6V
5
7
2V
4
5
4.5 V
3
4
6V
3
4
2V
4
5
4.5 V
4
5
6V
4
5
UNIT
MAX
ns
ns
ns
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6.7 Switching Characteristics
CL = 50 pF; over operating free-air temperature range (unless otherwise noted). See Parameter Measurement Information.
Operating free-air temperature (TA)
PARAMETER
FROM
TO
VCC
25°C
MIN
TYP
MAX
17
35
51
4.5 V
7
14
20
6V
6
12
17
2V
15
30
48
7
11
17
2V
An
tpd
Propagation delay
Y
G or G
LE
Y or Y
Y or Y
4.5 V
Transition-time
MIN
TYP
MAX
6V
6
9
15
2V
18
39
60
4.5 V
8
16
24
6V
7
15
21
9
16
5
9
4
8
2V
tt
UNIT
–40°C to 125°C
Any output 4.5 V
6V
ns
ns
6.8 Operating Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER
Cpd
6
TEST CONDITIONS
Power dissipation capacitance
No load
per gate
VCC
2 V to 6 V
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MIN
TYP
40
MAX UNIT
pF
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6.9 Typical Characteristics
TA = 25°C
70
46
VCC = 2 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 6 V
Output Resistance (:)
42
VCC = 2 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 6 V
65
Output Resistance (:)
44
40
38
36
34
32
60
55
50
45
40
30
35
28
26
30
0
2.5
5
7.5 10 12.5 15 17.5
Output Sink Current (mA)
20
22.5
25
Figure 6-1. Output driver resistance in LOW state.
0
ICC ± Supply Current (mA)
VCC = 2.5 V
0.14
VCC = 3.3 V
ICC ± Supply Current (mA)
VCC = 2 V
0.16
0.12
0.1
0.08
0.06
0.04
0.02
0
0
0.5
1
1.5
2
2.5
VI ± Input Voltage (V)
3
3.5
Figure 6-3. Supply current across input voltage, 2-,
2.5-, and 3.3-V supply
5
7.5 10 12.5 15 17.5
Output Source Current (mA)
20
22.5
25
Figure 6-2. Output driver resistance in HIGH state.
0.2
0.18
2.5
0.65
0.6
0.55
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
VCC = 4.5 V
VCC = 5 V
VCC = 6 V
0
0.5
1
1.5
2 2.5 3 3.5 4
VI ± Input Voltage (V)
4.5
5
5.5
6
Figure 6-4. Supply current across input voltage,
4.5-, 5-, and 6-V supply
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7 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 2.5 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
tw
Test
Point
VCC
Input
From Output
Under Test
50%
50%
0V
Figure 7-2. Voltage Waveforms, Pulse Duration
CL(1)
(1) CL includes probe and test-fixture capacitance.
Figure 7-1. Load Circuit
VCC
VCC
Clock
Input
Input
50%
50%
50%
0V
0V
tsu
tPLH
th
(1)
tPHL
(1)
VOH
VCC
Data
Input
50%
Output
50%
50%
50%
VOL
0V
Figure 7-3. Voltage Waveforms, Setup and Hold
Times
tPLH(1)
tPHL(1)
VOH
Output
50%
50%
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 7-4. Voltage Waveforms Propagation Delays
90%
VCC
90%
Input
10%
10%
tr(1)
0V
tf(1)
90%
VOH
90%
Output
10%
10%
tr(1)
tf(1)
VOL
(1) The greater between tr and tf is the same as tt.
Figure 7-5. Voltage Waveforms, Input and Output Transition Times
8
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8 Detailed Description
8.1 Overview
The SN74HCS237-Q1 is a high speed silicon gate CMOS decoder well suited to memory address decoding or
data routing applications. It contains a single 3:8 decoder. All inputs include Schmitt-triggers allowing for slow
input transitions and providing additional noise margin.
The SN74HCS237-Q1 has three address select inputs (A2, A1, and A0). When the latch enable (LE) input is low,
the circuit functions as a normal one-of-eight decoder. When the latch enable (LE) input is high, the address
latches will maintain their previous states, regardless of any changes at the address select inputs.
Two strobe inputs (G 1 and G0) are provided to simplify cascading and to facilitate demultiplexing. When any
input strobe is active, all outputs are forced into the low state.
The demultiplexing function is accomplished by first using the select inputs to choose the desired output, and
then using one of the strobe inputs as the data input.
The outputs for the SN74HCS237-Q1 are normally low, and high when selected.
8.2 Functional Block Diagram
LE
3-BIT
LATCH
A0
D
LE
Q
Q
A1
D
LE
Q
Q
A2
D
LE
Q
Q
3:8 DECODER
OUTPUT
ENABLE
000
Y0
001
Y1
010
Y2
011
Y3
100
Y4
OE0
101
Y5
OE1
110
Y6
111
Y7
Figure 8-1. Logic Diagram (Positive Logic) for the SN74HCS237-Q1
8.3 Feature Description
8.3.1 Balanced CMOS Push-Pull Outputs
This device includes balanced CMOS push-pull outputs. The term "balanced" indicates that the device can sink
and source similar currents. The drive capability of this device may create fast edges into light loads so routing
and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable
of driving larger currents than the device can sustain without being damaged. It is important for the output power
of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the
Absolute Maximum Ratings must be followed at all times.
Unused push-pull CMOS outputs should be left disconnected.
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8.3.2 CMOS Schmitt-Trigger Inputs
This device includes inputs with the Schmitt-trigger architecture. These inputs are high impedance and are
typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics table
from the input to ground. The worst case resistance is calculated with the maximum input voltage, given in the
Absolute Maximum Ratings table, and the maximum input leakage current, given in the Electrical Characteristics
table, using Ohm's law (R = V ÷ I).
The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics
table, which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much
slower than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the
inputs with slow transitioning signals will increase dynamic current consumption of the device. For additional
information regarding Schmitt-trigger inputs, please see Understanding Schmitt Triggers.
8.3.3 Clamp Diode Structure
The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Electrical
Placement of Clamping Diodes for Each Input and Output.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage
to the device. The input and output voltage ratings may be exceeded if the input and output clampcurrent ratings are observed.
Device
VCC
+IIK
+IOK
Logic
Input
-IIK
Output
-IOK
GND
Figure 8-2. Electrical Placement of Clamping Diodes for Each Input and Output
10
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8.4 Device Functional Modes
Function Table lists the functional modes of the SN74HCS237-Q1.
Table 8-1. Function Table
INPUTS(1)
(1)
OUTPUTS
LE
G0
G1
A2
A1
A0
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
X
X
H
X
X
X
L
L
L
L
L
L
L
L
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
H
L
H
L
L
L
L
L
L
L
H
L
L
H
L
L
L
H
L
L
L
L
L
L
H
L
L
H
H
L
L
L
H
L
L
L
L
L
H
L
H
L
L
L
L
L
L
H
L
L
L
L
H
L
H
L
H
L
L
L
L
L
H
L
L
L
H
L
H
H
L
L
L
L
L
L
L
H
L
L
H
L
H
H
H
L
L
L
L
L
L
L
H
H
H
L
X
X
X
Depends upon the address previously applied while LE was at a logic low.
H = High Voltage Level, L = Low Voltage Level, X = Don't Care
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
The SN74HCS237-Q1 is used to control multiple devices that operate on a shared data bus. A decoder provides
the capability to have a binary encoded input activate only one of the device's outputs. This is ideal for solid state
memory applications where multiple devices have to be read or written to with a limited number of GPIO pins
used on the system controller. The decoder is used to activate the chip select (CS) input to the selected memory
device, and the controller can then read or write from that device alone when using a shared bus.
9.2 Typical Application
Device 1
A0
Y1
Device 2
Y2
Device 3
Y3
Device 4
Y4
Device 5
Y5
Device 6
Y6
Device 7
Y7
Device 8
A1
3-BIT
LATCH
A2
G0
G1
CONTROL
LOGIC
OUTPUT ENABLE
Y0
3:8 DECODER
System
Controller
LE
Data Bus
Figure 9-1. Typical application block diagram
9.2.1 Design Requirements
9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics.
The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all
outputs of the SN74HCS237-Q1 plus the maximum static supply current, ICC, listed in Electrical Characteristics
and any transient current required for switching. The logic device can only source as much current as is provided
by the positive supply source. Be sure not to exceed the maximum total current through VCC listed in the
Absolute Maximum Ratings.
The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the
SN74HCS237-Q1 plus the maximum supply current, ICC, listed in Electrical Characteristics, and any transient
current required for switching. The logic device can only sink as much current as can be sunk into its ground
connection. Be sure not to exceed the maximum total current through GND listed in the Absolute Maximum
Ratings.
The SN74HCS237-Q1 can drive a load with a total capacitance less than or equal to 50 pF while still meeting
all of the datasheet specifications. Larger capacitive loads can be applied, however it is not recommended to
exceed 50 pF.
The SN74HCS237-Q1 can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage
and current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the high state,
12
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the output voltage in the equation is defined as the difference between the measured output voltage and the
supply voltage at the VCC pin.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional
limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum
Ratings. These limits are provided to prevent damage to the device.
9.2.1.2 Input Considerations
Input signals must cross Vt-(min) to be considered a logic LOW, and Vt+(max) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the
SN74HCS237-Q1, as specified in the Electrical Characteristics, and the desired input transition rate. A 10-kΩ
resistor value is often used due to these factors.
The SN74HCS237-Q1 has no input signal transition rate requirements because it has Schmitt-trigger inputs.
Another benefit to having Schmitt-trigger inputs is the ability to reject noise. Noise with a large enough amplitude
can still cause issues. To know how much noise is too much, please refer to the ΔVT(min) in the Electrical
Characteristics. This hysteresis value will provide the peak-to-peak limit.
Unlike what happens with standard CMOS inputs, Schmitt-trigger inputs can be held at any valid value without
causing huge increases in power consumption. The typical additional current caused by holding an input at a
value other than VCC or ground is plotted in the Typical Characteristics.
Refer to the Feature Description section for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. The ground
voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output
voltage as specified by the VOL specification in the Electrical Characteristics.
Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected
directly together. This can cause excessive current and damage to the device.
Two channels within the same device with the same input signals can be connected in parallel for additional
output drive strength.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to Feature Description section for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout
section.
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2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit, however it will ensure
optimal performance. This can be accomplished by providing short, appropriately sized traces from the
SN74HCS237-Q1 to the receiving device(s).
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in megaohms; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation.
9.2.3 Application Curve
LE
G0
A[2:0]
b000
Y[7:0]
0x00
b010
0x04
b111
0x80
b001
b101
0x02
b100
0x10
0x00
Figure 9-2. Application timing diagram
14
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10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in
given example layout image.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
11.2 Layout Example
GND VCC
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
F
Avoid 90°
corners for
signal lines
Bypass capacitor
placed close to the
device
A0
1
16
VCC
A1
2
15
Y0
A2
3
14
Y1
LE
4
13
Y2
G1
5
12
Y3
G0
6
11
Y4
Y7
GND
7
8
10
9
Y5
Y6
Unused
inputs tied to
VCC
Unused
output left
floating
Figure 11-1. Example layout for the SN74HCS237-Q1 in the PW package.
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12 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
•
•
•
Texas Instruments, HCMOS Design Considerations application report (SCLA007)
Texas Instruments, CMOS Power Consumption and Cpd Calculation application report (SDYA009)
Texas Instruments, Designing With Logic application report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
16
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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16-Jun-2021
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74HCS237QDRQ1
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HCS237Q
SN74HCS237QPWRQ1
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HCS237Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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