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SN74HCS72-Q1
SCLS774 – OCTOBER 2019
SN74HCS72-Q1 Automotive Qualified Schmitt-Trigger Input Dual D-Type
Negative-Edge-Triggered Flip-Flops With Clear and Preset
1 Features
3 Description
•
This device contains two independent D-type
negative-edge-triggered flip-flops. All inputs include
Schmitt-triggers, allowing for slow or noisy input
signals. A low level at the preset (PRE) input sets the
output high. A low level at the clear (CLR) input
resets the output low. Preset and clear functions are
asynchronous and not dependent on the levels of the
other inputs. When PRE and CLR are inactive (high),
data at the data (D) input meeting the setup time
requirements is transferred to the outputs (Q, Q) on
the negative-going edge of the clock (CLK) pulse.
Following the hold-time interval, data at the data (D)
input can be changed without affecting the levels at
the outputs (Q, Q).
1
•
•
•
•
AEC-Q100 Qualified for automotive applications:
– Device temperature grade 1: –40°C to +125°C,
TA
– Device HBM ESD Classification Level 2
– Device CDM ESD Classifcation Level C6
Wide operating voltage range: 2 V to 6 V
Schmitt-trigger inputs allow for slow or noisy input
signals
Low power consumption
– Typical ICC of 100 nA
– Typical input leakage current of ±100 nA
±7.8-mA output drive at 5 V
Device Information(1)
2 Applications
•
•
•
•
PART NUMBER
SN74HCS72QDRQ1
Convert a momentary switch to a toggle switch
Input slow edge-rate signals
Operate in noisy environments
Enable CAN Controller Power with wake-up
pattern
PACKAGE
SOIC (14)
SN74HCS72QPWRQ1 TSSOP (14)
BODY SIZE (NOM)
8.70 mm x 3.90 mm
5.00 mm x 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Benefits of Schmitt-trigger Inputs
Voltage
Output
Current
Voltage
Current
Output
Input Voltage
Voltage
Output
Voltage
Time
Current
Response
Waveforms
Time
Time
Input Voltage
Output
Schmitt-trigger
CMOS Input
Time
Time
Current
Response
Waveforms
Supply Current
Standard
CMOS Input
Supply Current
Input Voltage
Supports Slow Inputs
Input
Voltage
Noise Rejection
Input
Voltage
Input Voltage
Waveforms
Input
Voltage
Low Power
Time
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74HCS72-Q1
SCLS774 – OCTOBER 2019
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
4
4
4
4
5
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Timing Characteristics...............................................
Typical Characteristics ..............................................
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 10
9
Application and Implementation ........................ 11
9.1 Application Information .......................................... 11
9.2 Typical Application ................................................. 11
10 Power Supply Recommendations ..................... 13
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Example .................................................... 13
12 Device and Documentation Support ................. 14
12.1
12.2
12.3
12.4
12.5
12.6
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
14
14
14
14
14
14
13 Mechanical, Packaging, and Orderable
Information ........................................................... 14
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
4 Revision History
2
DATE
REVISION
NOTES
October 2019
*
Initial release.
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5 Pin Configuration and Functions
D and PW Package
14-Pin SOIC and TSSOP
Top View
1CLR
1D
1
14
VCC
2
13
2CLR
1CLK
3
12
1PRE
4
11
2D
2CLK
1Q
5
10
1Q
6
9
2Q
GND
7
8
2Q
2PRE
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
NO.
1CLR
1
Input
Clear for channel 1, active low
1D
2
Input
Data for channel 1
1CLK
3
Input
Clock for channel 1, falling edge triggered
1PRE
4
Input
Preset for channel 1, active low
1Q
5
Output
Output for channel 1
1Q
6
Output
Inverted output for channel 1
GND
7
—
2Q
8
Output
Inverted output for channel 2
2Q
9
Output
Output for channel 2
2PRE
10
Input
Preset for channel 2, active low
2CLK
11
Input
Clock for channel 2, falling edge triggered
2D
12
Input
Data for channel 2
2CLR
13
Input
Clear for channel 2, active low
VCC
14
—
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Ground
Positive supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
IIK
Input clamp current
(2)
(2)
IOK
Output clamp current
IO
Continuous output current
MIN
MAX
–0.5
7
UNIT
V
VI < 0 or VI > VCC + 0.5 V
±20
mA
VO < 0 or VO > VCC + 0.5
V
±20
mA
VO = 0 to VCC
±25
mA
Continuous current through VCC or GND
±50
mA
Tj
Junction temperature (3)
150
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
Guaranteed by design
6.2 ESD Ratings
VALUE
V(ESD)
(1)
Electrostatic discharge
Human body model (HBM), per AEC Q100-002 (1)
HBM ESD Classification Level 2
±4000
Charged device model (CDM), per AEC Q100011
CDM ESD Classification Level C4B
±1000
UNIT
V
AEC Q100-002 indicate that HBM stressing shall be in accordrance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
5
MAX
UNIT
VCC
Supply voltage
2
6
V
VI
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
Δt/Δv
Input transition rise and fall rate
TA
Ambient temperature
Unlimited
–40
125
ns/V
°C
6.4 Thermal Information
SN74HCS72-Q1
THERMAL METRIC
D (SOIC)
PW (TSSOP)
14 PINS
14 PINS
UNIT
133.6
151.7
°C/W
89
79.4
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
89.5
94.7
°C/W
ΨJT
Junction-to-top characterization parameter
45.5
25.2
°C/W
ΨJB
Junction-to-board characterization parameter
89.1
94.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
N/A
°C/W
4
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6.5 Electrical Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted)
PARAMETER
VT+
VT-
ΔVT
VOH
TEST CONDITIONS
Positive switching threshold
Negative switching threshold
Hysteresis (VT+ - VT-)
(1)
High-level output voltage
VI = VIH or VIL
VCC
MIN
TYP
MAX UNIT
2V
0.7
1.5
4.5 V
1.7
3.15
6V
2.1
4.2
2V
0.3
1.0
4.5 V
0.9
2.2
6V
1.2
3.0
2V
0.2
1.0
4.5 V
0.4
1.4
6V
0.6
1.6
IOH = -20 µA
2 V to 6 V
IOH = -6 mA
4.5 V
IOH = -7.8 mA
6V
IOL = 20 µA
2 V to 6 V
IOL = 6 mA
4.5 V
IOL = 7.8 mA
VCC – 0.1
V
V
V
VCC – 0.002
4
4.3
5.4
5.75
V
0.002
0.1
0.18
0.30
VOL
Low-level output voltage
VI = VIH or VIL
6V
0.22
0.33
II
Input leakage current
VI = VCC or 0
6V
±100
±1000
nA
ICC
Supply current
VI = VCC or 0, IO = 0
6V
0.1
2
µA
Ci
Input capacitance
5
pF
Cpd
Power dissipation capacitance
per gate
(1)
2 V to 6 V
No load
2 V to 6 V
10
V
pF
Guaranteed by design.
6.6 Switching Characteristics
CL = 50 pF; over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). See
Parameter Measurement Information
PARAMETER
fmax
FROM (INPUT)
TO (OUTPUT)
Max switching frequency
MIN
TYP
2V
VCC
20
31
4.5 V
64
95
6V
74
105
2V
PRE or CLR
tpd
Propagation delay
CLK
tt
(1)
Q or Q
Transition-time (1)
Q or Q
Q or Q
MAX
MHz
19
42
8
19
6V
7
15
2V
19
42
4.5 V
8
19
6V
7
15
2V
9
16
4.5 V
5
9
6V
4
8
4.5 V
UNIT
ns
ns
ns
tt = tr or tf, whichever is larger
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6.7 Timing Characteristics
CL = 50 pF; over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). See
Parameter Measurement Information.
PARAMETER
fclock
VCC
Clock frequency
PRE or CLR low
tw
Pulse duration
CLK high or low
Data
tsu
Setup time before CLK low
PRE or CLR inactive
th
6
Hold time
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Data after CLK ↓
MIN
TYP
MAX
2V
20
4.5 V
64
6V
74
2V
8
7
4.5 V
7
5
6V
7
5
2V
10
5
9
3
4.5 V
6V
8
2
2V
16
11
4.5 V
6
1
6V
3
1
2V
7
4.5 V
0
6V
0
2V
5
4.5 V
3
6V
2
UNIT
MHz
ns
ns
ns
ns
ns
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6.8 Typical Characteristics
TA = 25°C
70
46
VCC = 2 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 6 V
Output Resistance (:)
42
VCC = 2 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 6 V
65
Output Resistance (:)
44
40
38
36
34
32
60
55
50
45
40
30
35
28
26
30
0
2.5
5
7.5 10 12.5 15 17.5
Output Sink Current (mA)
20
22.5
25
Figure 1. Output driver resistance in LOW state.
0
ICC ± Supply Current (mA)
VCC = 2.5 V
0.14
VCC = 3.3 V
ICC ± Supply Current (mA)
VCC = 2 V
0.16
0.12
0.1
0.08
0.06
0.04
0.02
0
0
0.5
1
1.5
2
2.5
VI ± Input Voltage (V)
3
3.5
Figure 3. Supply current across input voltage, 2-,
2.5-, and 3.3-V supply
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5
7.5 10 12.5 15 17.5
Output Source Current (mA)
20
22.5
25
Figure 2. Output driver resistance in HIGH state.
0.2
0.18
2.5
0.65
0.6
0.55
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
VCC = 4.5 V
VCC = 5 V
VCC = 6 V
0
0.5
1
1.5
2 2.5 3 3.5 4
VI ± Input Voltage (V)
4.5
5
5.5
6
Figure 4. Supply current across input voltage, 4.5-,
5-, and 6-V supply
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7 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 2.5 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
VCC
RL
From Output
Under Test
tw
VCC
Test
Point
S1
Input
50%
50%
0V
Figure 6. Voltage Waveforms, Pulse Duration
CL(1)
S2
CL includes probe and test-fixture capacitance.
Figure 5. Load Circuit
VCC
VCC
Clock
Input
50%
Input
50%
50%
0V
tsu
0V
tPHL(1)
tPLH(1)
th
VCC
Data
Input
50%
VOH
50%
Output
50%
50%
0V
VOL
Figure 7. Voltage Waveforms, Setup and Hold Times
tPLH(1)
tPHL(1)
VOH
Output
50%
50%
VOL
Voltage Waveforms, Propagation Delay specifications tPLH and tPHL
are the same as tpd.
Figure 8. Voltage Waveforms Propagation Delays
90%
VCC
90%
Input
10%
10%
tf
tr
90%
0V
90%
VOH
Output
10%
tr
10%
tf
VOL
Figure 9. Voltage Waveforms, Input and Output Transition Times
8
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8 Detailed Description
8.1 Overview
Figure 10 describes the SN74HCS72-Q1. As the SN74HCS72-Q1 is a dual D-Type negative-edge-triggered flipflop with clear and preset, the diagram below describes one of the two device flip-flops.
8.2 Functional Block Diagram
CLK
C
C
PRE
C
Q
C
C
D
C
C
C
C
Q
C
CLR
Figure 10. Logic Diagram (Positive Logic) for one channel of SN74HCS72-Q1
8.3 Feature Description
8.3.1 Balanced CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The drive capability of this device may
create fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the output power of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined the in the Absolute Maximum Ratings must be followed at all
times.
8.3.2 CMOS Schmitt-Trigger Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum
input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the
Electrical Characteristics, using ohm's law (R = V ÷ I).
The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics,
which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much slower
than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the inputs slowly
will also increase dynamic current consumption of the device. For additional information regarding Schmitt-trigger
inputs, please see Understanding Schmitt Triggers.
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Feature Description (continued)
8.3.3 Positive and Negative Clamping Diodes
The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Figure 11.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can
cause damage to the device. The input negative-voltage and output voltage ratings
may be exceeded if the input and output clamp-current ratings are observed.
Device
VCC
+IIK
+IOK
Logic
Input
Output
-IIK
-IOK
GND
Figure 11. Electrical Placement of Clamping Diodes for Each Input and Output
8.4 Device Functional Modes
Table 1 lists the functional modes of the SN74HCS72-Q1.
Table 1. Function Table
INPUTS
(1)
10
OUTPUTS
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H (1)
H (1)
H
H
↓
H
H
L
H
H
↓
L
L
H
H
H
L
X
Q0
Q0
H
H
H
X
Q0
Q0
This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive
(high) level.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74HCS72-Q1 is an ideal device for taking a CAN wake-up request and converting it to a power supply
enable due to its low power consumption and noise rejecting inputs, which eliminate false triggers. CAN
communication can occur when the vehicle ignition is off. Therefore, many circuits are designed to work in a
standby or low power mode. Because a CAN wake-up request causes the RX pin to pulse LOW, the
SN74HCS72-Q1 will trigger off the falling edge enabling the power for the CAN controller. Then the CAN
controller powers on for the incoming communication. When communications are finished, the controller sends a
reset pulse to the SN74HCS72-Q1 and CAN transceiver putting the circuit back into a standby mode.
9.2 Typical Application
VCC
CAN Controller
Power
CAN Transceiver
RX
VCC
PRE
CLK
R1
nSTB
TX
EN
VCC
C1
R2
D
Q
CLR
Q
GND
RX
CAN Controller
I/O
TX
Figure 12. Power Enable Using CAN Wake-up Request
9.2.1 Design Requirements
The SN74HCS72-Q1 device allows flexibility by having complementary outputs for active-high or active-low
enables. The supply should be selected such that the device is always powered along with the CAN transceiver.
The same supply for both devices is recommended.
With the SN74HCS72-Q1, a power on reset circuit only requires a resistor (R) and capacitor (C) to create a
delay. The R and C values create a delay that is approximately 2.2×RC. In this application, it is desired to have
the output (Q) in the HIGH state at startup, so R1 and C1 are connected directly to the CLR pin, as shown in
Figure 12. A second resistor is needed to limit the current into the CAN controller when it sets the circuit back
into standby mode. It is required for the R1 resistor to be at least ten times larger than R2 to avoid a divider
circuit (R2 ≤ 10R1).
The D input can be tied either to VCC or ground depending on the desired implementation. In this example, it is
tied to VCC to obtain a HIGH signal from Q when a wake-up request occurs.
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Typical Application (continued)
9.2.1.1 Output Considerations
In general, the load needs to be considered in the design to determine if the device will have the capability to
drive it. For this application, we assume that the flip-flop output is transmitting over a relatively short trace (under
10 cm) to a CMOS input.
Primary load factors to consider:
• Load Capacitance: approximately 15 pF
– See the Switching Characteristics section for the capacitive loads tested with this device.
– Increasing capacitance will proportionally increase output transition times.
– Decreasing capacitance will proportionally decrease output transition times, and can produce ringing due
to very fast transition rates. A 25-Ω resistor can be added in series with the output if ringing needs to be
dampened.
• Load Current: expected maximum of 10 µA
– Leakage current into connected devices.
– Parasitic current from other components.
– Resistive load current.
• Output Voltage: see Electrical Characteristics for output voltage ratings at a given current.
– Output HIGH (VOH) and output LOW (VOL) voltage levels affect the input voltage, VIH and VIL, respectively,
to subsequent devices.
9.2.1.2 Input Considerations
The SN74HCS72-Q1 has Schmitt-trigger inputs. Schmitt-trigger inputs have no limitation on transition rate,
however the input voltage must be larger than VT+(max) to be guaranteed to be read as a logic high, and below
VT-(min) to be guaranteed to be read as a logic low, as defined in the Electrical Characteristics. Do not exceed the
values specified in the Absolute Maximum Ratings or the device could be damaged.
9.2.1.3 Timing Considerations
The SN74HCS72-Q1 is a clocked device. As such, it requires special timing considerations to ensure normal
operation.
Primary timing factors to consider:
• Maximum clock frequency: the maximum operating clock frequency defined in Timing Characteristics is the
maximum frequency at which the device is guaranteed to function. This value refers specifically to the
triggering waveform, measuring from one trigger level to the next.
• Pulse duration: ensure that the triggering event duration is larger than the minimum pulse duration, as defined
in the Timing Characteristics.
• Setup time: ensure that the data has changed at least one setup time prior to the triggering event, as defined
in the Timing Characteristics.
• Hold time: ensure that the data remains in the desired state at least one hold time after the triggering event,
as defined in the Timing Characteristics.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
– Input signals to Schmitt-trigger inputs, like those found on the HCS family of devices, can support
unlimited edge rates.
– Input thresholds are listed in the Electrical Characteristics.
– Inputs include positive clamp diodes. Input voltages can exceed the device's supply so long as the clamp
current ratings are observed from the Absolute Maximum Ratings. Do not exceed the absolute maximum
voltage rating of the device or it could be damaged.
2. Recommended Output Conditions:
– Load currents should not exceed the value listed in the Absolute Maximum Ratings.
– Series resistors on the output may be used if the user desires to slow the output edge signal or limit the
12
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Typical Application (continued)
output current.
9.2.3 Application Curve
CAN WUP*
Q
*Wake-up Pattern
Commu nicatio n Finishe d
RX
I/O
Figure 13. Application timing diagram
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Absolute Maximum Ratings table. Each VCC terminal should have a bypass capacitor to prevent power
disturbance. For this device, a 0.1-μF capacitor is recommended. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminals as possible for best results.
11 Layout
11.1 Layout Guidelines
In many cases, functions or parts of functions of digital logic devices are unused. Some examples are when only
two inputs of a triple-input AND gate are used, or when only 3 of the 4 channels are used. Such input pins should
not be left completely unconnected because the unknown voltages result in undefined operational states.
Specified in Figure 14 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that must be
applied to any particular unused input depends on the function of the device. Generally they are tied to GND or
VCC, whichever makes more sense or is more convenient. It is recommended to float outputs unless the part is a
transceiver. If the transceiver has an output enable pin, it disables the output section of the part when asserted.
This pin keeps the input section of the I/Os from being disabled and floated.
11.2 Layout Example
GND VCC
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
0.1 F
Avoid 90°
corners for
signal lines
Bypass capacitor
placed close to
the device
1CLR
1
14
VCC
Unused inputs
tied to VCC
1D
2
13
2CLR
1CLK
3
12
2D
1PRE
4
11
2CLK
1Q
5
10
2PRE
1Q
6
9
2Q
GND
7
8
2Q
Unused output
left floating
Figure 14. Layout Example
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13
SN74HCS72-Q1
SCLS774 – OCTOBER 2019
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Implications of Slow or Floating CMOS Inputs application report
• Texas Instruments, Reduce Noise and Save Power with the New HCS Logic Family application report
• Texas Instruments, Understanding Schmitt Triggers application report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
14
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
SN74HCS72QDRQ1
ACTIVE
SOIC
D
14
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HCS72Q1
SN74HCS72QPWRQ1
ACTIVE
TSSOP
PW
14
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HCS72Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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