SN74HCT02NSRG4

SN54HCT02, SN74HCT02 SCLS065G – NOVEMBER 1988 – REVISED OCTOBER 2022 SNx4HCT02 Quadruple 2-Input Positive-Nor Gates 1 Features 2 Description • • • • • • • These devices contain four independent 2-input NOR gates. They perform the Boolean function Y = A • B or Y = A + B in positive logic. Operating voltage range of 4.5V to 5.5V Outputs can drive up to 10 LSTTL loads Low power consumption, 20-µA max ICC Typical tpd = 10ns ±4-mA output drive at 5V Low input current of 1µA max Inputs are TTL-Voltage compatible (1) Device Information PART NUMBER PACKAGE BODY SIZE (NOM) SN74HCT02D SOIC (14) 8.65 mm × 3.90 mm SN74HCT02N PDIP (14) 19.31 mm × 6.35 mm SN74HCT02NSR SO (14) 10.20 mm × 5.30 mm SN74HCT02PW TSSOP (14) 5.00 mm × 4.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Functional Block Diagram An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. SN54HCT02, SN74HCT02 www.ti.com SCLS065G – NOVEMBER 1988 – REVISED OCTOBER 2022 Table of Contents 1 Features............................................................................1 2 Description.......................................................................1 3 Revision History.............................................................. 2 4 Pin Configuration and Functions...................................3 5 Specifications.................................................................. 4 5.1 Absolute Maximum Ratings........................................ 4 (1) 5.2 Recommended Operating Conditions ..................... 4 5.3 Thermal Information....................................................4 5.4 Electrical Characteristics.............................................5 5.5 Switching Characteristics ...........................................5 5.6 Operating Characteristics........................................... 5 6 Parameter Measurement Information............................ 6 7 Detailed Description........................................................7 7.1 Overview..................................................................... 7 7.2 Functional Block Diagram........................................... 7 7.3 Device Functional Modes............................................7 8 Power Supply Recommendations..................................8 9 Layout...............................................................................8 9.1 Layout Guidelines....................................................... 8 10 Device and Documentation Support............................9 10.1 Documentation Support............................................ 9 10.2 Receiving Notification of Documentation Updates....9 10.3 Support Resources................................................... 9 10.4 Trademarks............................................................... 9 10.5 Electrostatic Discharge Caution................................9 10.6 Glossary....................................................................9 11 Mechanical, Packaging, and Orderable Information...................................................................... 9 3 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (February 2022) to Revision G (October 2022) Page • Increased RθJA for packages: D (86 to 138.7); N (80 to 67); NS (76 to 93.3); PW (113 to 120.1) ................... 4 Changes from Revision E (July 2003) to Revision F (February 2022) Page • Updated the numbering, formatting, tables, figures, and cross-references throughout the doucment to reflect modern data sheet standards............................................................................................................................. 1 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HCT02 SN74HCT02 SN54HCT02, SN74HCT02 www.ti.com SCLS065G – NOVEMBER 1988 – REVISED OCTOBER 2022 4 Pin Configuration and Functions D, N, NS, PW, J or W Package 14-Pin SOIC, PDIP, SO, TSSOP, CDIP, or CFP Top View FK Package 20-Pin LCCC Top View Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HCT02 SN74HCT02 3 SN54HCT02, SN74HCT02 www.ti.com SCLS065G – NOVEMBER 1988 – REVISED OCTOBER 2022 5 Specifications 5.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted)(1) VCC Supply voltage range MIN MAX -0.5 7 )(2) UNIT V IIK Input clamp current (VI < 0 or VI > VCC ±20 mA IOK Output clamp current (VO < 0 or VO > VCC)(2) ±20 mA IO Continuous output current (VO = 0 to VCC) ±25 mA Continuous current through VCC or ground current ±50 mA 150 °C 150 °C TJ Junction temperature Tstg Storage temperature (1) (2) -65 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. (1) 5.2 Recommended Operating Conditions SN54HCT02(2) MIN NOM MIN NOM MAX 5.5 4.5 5 5.5 Supply voltage VIH High-level input voltage VCC = 4.5 V to 5.5 V VIL Low-level input voltage VCC = 4.5 V to 5.5 V 0.8 V VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V Δt/Δv Input transition rise/fall time 500 ns TA Operating free-air temperature 85 °C (2) 5 UNIT VCC (1) 4.5 SN74HCT02 MAX 2 2 0.8 500 -55 125 -40 V V All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report Implications of Slow or Floating SMOS Inputs, literature number SCBA004. SN54HCT02 is in product preview. 5.3 Thermal Information THERMAL METRIC N (PDIP) NS (SO) PW (TSSOP) 14 PINS 14 PINS 14 PINS 14 PINS UNIT RθJA Junction-to-ambient thermal (1) resistance 138.7 67 93.3 120.1 °C/W RθJC (top) Junction-to-case (top) thermal resistance 93.8 55 50.9 49.4 °C/W RθJB Junction-to-board thermal resistance 94.7 46.7 53.8 63.1 °C/W ΨJT Junction-to-top characterization parameter 49.1 35.1 17.8 6.7 °C/W ΨJB Junction-to-board characterization parameter 94.3 46.5 53.3 62.5 °C/W RθJC (bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A N/A °C/W (1) 4 D (SOIC) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application report. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HCT02 SN74HCT02 SN54HCT02, SN74HCT02 www.ti.com SCLS065G – NOVEMBER 1988 – REVISED OCTOBER 2022 5.4 Electrical Characteristics PARAMETER TEST CONDITIONS(1) IOH = –20 μA VOH High-level output voltage VOL Low-level output voltage II Input hold current VI = VCC or 0 5.5 ICC Supply current VI = VCC or 0. IO = 0 5.5 One input at 0.5V or 2.4 V, Other inputs at 0 or VCC 5.5 ΔICC(2) Supply-current change Ci (1) (2) (3) 4.5 IOH = –4 mA IOL = 20 μA 5.5 IOL = 4 mA MAX MIN MAX SN74HCT00 MIN TYP 4.4 4.499 4.4 4.4 3.98 4.3 3.7 3.84 MIN MAX UNIT V 0.001 0.1 0.1 0.1 0.17 0.26 0.4 0.33 ±0.1 ±100 ±1000 ±1000 nA 2 40 20 μA 1.4 2.4 3 2.9 mA 3 10 10 10 pF 4.5 to 5.5 Input capacitance SN54HCT00(3) TA = 25°C VCC (V) V VI = VIH or VIL, unless otherwise noted. This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC. SN54HCT02 is in product preview. 5.5 Switching Characteristics CL = 50 pF. See Parameter Measurement Information PARAMETER tpd Propagation delay tt Transition time (1) FROM (INPUT) TO (OUTPUT) A or B Y Y VCC (V) SN54HCT02(1) TA = 25°C MIN MIN MAX SN74HCT00 TYP MAX MIN MAX 4.5 11 20 30 25 5.5 10 18 27 22 4.5 9 15 22 19 5.5 8 14 20 17 ns ns SN54HCT02 is in product preview. 5.6 Operating Characteristics TA = 25°C Cpd Power dissipation capacitance Test Conditions TYP UNIT No load 20 pF Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HCT02 SN74HCT02 5 SN54HCT02, SN74HCT02 www.ti.com SCLS065G – NOVEMBER 1988 – REVISED OCTOBER 2022 6 Parameter Measurement Information Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns. For clock inputs, fmax is measured when the input duty cycle is 50%. The outputs are measured one at a time with one input transition per measurement. Test Point From Output Under Test CL(1) (1) CL includes probe and test-fixture capacitance. Figure 6-1. Load Circuit for Push-Pull Outputs 3V Input 1.3V 1.3V 0V tPLH (1) tPHL(1) VOH Output Waveform 1 50% 50% VOL tPLH(1) tPHL(1) VOH Output Waveform 2 50% 50% VOL (1) The greater between tPLH and tPHL is the same as tpd. Figure 6-2. Voltage Waveforms, Propagation Delays for TTL-Compatible Inputs 6 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HCT02 SN74HCT02 SN54HCT02, SN74HCT02 www.ti.com SCLS065G – NOVEMBER 1988 – REVISED OCTOBER 2022 7 Detailed Description 7.1 Overview These devices contain four independent 2-input NOR gates. They perform the Boolean function Y = A • B or Y = A + B in positive logic. 7.2 Functional Block Diagram 7.3 Device Functional Modes Table 7-1. Function Table (each gate) INPUTS OUTPUT A B Y H X L X H L L L H Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HCT02 SN74HCT02 7 SN54HCT02, SN74HCT02 SCLS065G – NOVEMBER 1988 – REVISED OCTOBER 2022 www.ti.com 8 Power Supply Recommendations The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results. 9 Layout 9.1 Layout Guidelines When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic function or is more convenient. 8 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HCT02 SN74HCT02 SN54HCT02, SN74HCT02 www.ti.com SCLS065G – NOVEMBER 1988 – REVISED OCTOBER 2022 10 Device and Documentation Support TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below. 10.1 Documentation Support 10.1.1 Related Documentation 10.2 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 10.3 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 10.4 Trademarks TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 10.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 10.6 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. 11 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: SN54HCT02 SN74HCT02 9 PACKAGE OPTION ADDENDUM www.ti.com 20-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) Samples (4/5) (6) SN74HCT02D ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT02 Samples SN74HCT02DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HCT02 Samples SN74HCT02DRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT02 Samples SN74HCT02DT ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT02 Samples SN74HCT02N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HCT02N Samples SN74HCT02NE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HCT02N Samples SN74HCT02NSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT02 Samples SN74HCT02PW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HT02 Samples SN74HCT02PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HT02 Samples SN74HCT02PWT ACTIVE TSSOP PW 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HT02 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of